[gem5-dev] Vector register file

2016-12-10 Thread Rekai Gonzalez Alberquilla 
Hi folks,

   Yesterday I submitted five patches to the review board. The idea of the 
patches is to implement a proper vector register file. To enable cleaner 
implementations of the SIMD ISAs.


The first patch extends what Nathanael Premillieu did in spring, taking the 
hierarchical RegIds, and generalising the usage of them.


The second patch is an 'enabler'. It is a refactorisation of the InstResult, as 
having Vector Regs, and being able to define operations that operate on a 
vector register, we need to contemplate the possibility of instructions 
generating vector results. There are a couple points in the code that require 
bearing in mind that this change is right before adding vector registers to 
make sense.


The third patch adds the vector register class. For the implementation we 
decided to decouple the uarch entity that is the register, codified in the 
VecRegContainer class, which is just a group of bytes, from the interpretation 
of it, which belongs to the arch world. To do that, VecRegContainers have 
methods to create a view of the bytes as a vector of any plain type. This 
views, VecRegT have the expected functionality to inspect and modify the 
contents of the register.


The fourth patch (cpu: Added interface for vector reg file) creates a vector 
register file in the cpu models, and adds all the interface functions required 
across classes that implement ThreadContext or ExecContext interfaces. The 
rename is extended. Due to the particularities of some ISAs, the same set of 
registers can be accessed at register level, or at 'native element' level. 
Therefore, the rename stage and the rename map are updated in this patch to 
address that need. One particularly odd piece of functionality is a function to 
change the mode, as different 'chunks' may need to be consolidated into one 
physical vector register to preserve ISA semantics.


Finally, the last patch proposes updates to the parsing of the operands in Neon 
instructions for ARM to use the newly added Vector Register file.


Cheers,

Rekai

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[gem5-dev] Review Request 3757: arch: added generic vector register

2016-12-10 Thread Rekai Gonzalez Alberquilla 

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3757/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11762:51e68b2eed8a
---
arch: added generic vector register

This commit adds a new generic vector register to have a cleaner
implementation of SIMD ISAs.

Nathanael's idea, Rekai's implementation.

Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b
Reviewed-by: Andreas Sandberg 


Diffs
-

  src/arch/generic/vec_reg.hh PRE-CREATION 

Diff: http://reviews.gem5.org/r/3757/diff/


Testing
---

Builtin regressions


Thanks,

Rekai Gonzalez Alberquilla

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Re: [gem5-dev] Review Request 3762: config: Fix missing include in fs.py

2016-12-10 Thread Matthias Jung 

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http://reviews.gem5.org/r/3762/
---

(Updated Dez. 10, 2016, 10:33 vorm.)


Review request for Default.


Summary (updated)
-

config: Fix missing include in fs.py


Repository: gem5


Description
---

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:

```bash
build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img
```

NameError: global name 'CpuConfig' is not defined


Diffs
-

  configs/example/fs.py 78ef8daecd81 

Diff: http://reviews.gem5.org/r/3762/diff/


Testing
---


Thanks,

Matthias Jung

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Re: [gem5-dev] Review Request 3762: Bugfix for Elastic Traces

2016-12-10 Thread Matthias Jung 

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3762/
---

(Updated Dec. 10, 2016, 10:31 a.m.)


Review request for Default.


Repository: gem5


Description
---

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:

```bash
build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img
```

NameError: global name 'CpuConfig' is not defined


Diffs (updated)
-

  configs/example/fs.py 78ef8daecd81 

Diff: http://reviews.gem5.org/r/3762/diff/


Testing
---


Thanks,

Matthias Jung

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-12-10 Thread Cron Daemon 
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