date:20170518

Re: [gem5-dev] Issue With X86 O3 CPU

2017-05-18 Thread Gabe Black

I don't think the problem is a buffer overflow perse, or that it has
anything to do with an undefined instruction. I think you may have a wild
pointer to the instruction memory or the local nugget of instruction memory
the x86 predecoder is processing which ends up pointed to some part of the
data segment, and it just happens to be near some string constants which
belong to the fault objects including the one you're referring to. Note
that below that it talks about the 'Abort exception!' string literal being
near where you're accessing too.

Gabe

On Thu, May 18, 2017 at 2:28 PM, Gross, Joe  wrote:

> Hello,
>
> When running an application internally, with the address sanitizer
> enabled, I'm seeing a global buffer overflow in the x86 decoder during
> processExtendedOpcode() and wondered if anybody, possibly Gabe, would know
> a quick solution for this. If anybody would like a trace then I could
> generate this, but unfortunately the binaries that cause the problem are
> internal. The problem seems contained to decoding an unexpected opcode.
> Also the location changes slightly from application to application, so
> there may be several unsupported opcodes.
>
> Joe
>
> ERROR: AddressSanitizer: global-buffer-overflow on address 0x0454bcdf
> at pc 0x00adb323 bp 0x7fff873f1870 sp 0x7fff873f1868
> READ of size 1 at 0x0454bcdf thread T0
> #0 0xadb322 in X86ISA::Decoder::processExtendedOpcode(unsigned char
> const (&) [256]) X86/arch/x86/decoder.cc:460:23
> #1 0xadb322 in X86ISA::Decoder::doOneByteOpcodeState(unsigned char)
> X86/arch/x86/decoder.cc:299
> #2 0xad890d in X86ISA::Decoder::process()
> X86/arch/x86/decoder.cc:113:21
> #3 0x1f40de7 in X86ISA::Decoder::moreBytes(X86ISA::PCState const&,
> unsigned long, unsigned long) X86/arch/x86/decoder.hh:312:9
> #4 0x1f40de7 in DefaultFetch::fetch(bool&)
> X86/cpu/o3/fetch_impl.hh:1313
> #5 0x1f398fc in DefaultFetch::tick()
> X86/cpu/o3/fetch_impl.hh:947:9
> #6 0x1ec2ba6 in FullO3CPU::tick() X86/cpu/o3/cpu.cc:565:11
> #7 0x2eaa586 in EventQueue::serviceOne() X86/sim/eventq.cc:228:16
> #8 0x2efd8d4 in doSimLoop(EventQueue*)  X86/sim/simulate.cc:219:37
> #9 0x2efcd7d in simulate(unsigned long)  X86/sim/simulate.cc:132:26
>
> 0x0454bcdf is located 33 bytes to the left of global variable ' literal>' defined in 'X86/arch/x86/faults.cc:131:13' (0x454bd00) of size
> 47
>   '' is ascii string 'Unrecognized/invalid instruction
> executed:
>  %s'
> 0x0454bcdf is located 14 bytes to the right of global variable
> '' defined in 'X86/arch/x86/faults.cc:122:9' (0x454bcc0) of
> size 17
>   '' is ascii string 'Abort exception!'
> SUMMARY: AddressSanitizer: global-buffer-overflow
> X86/arch/x86/decoder.cc:460:23 in 
> X86ISA::Decoder::processExtendedOpcode(unsigned
> char const (&) [256])
> Shadow bytes around the buggy address:
>   0x808a1740: 00 00 00 00 00 00 00 00 00 00 00 f9 f9 f9 f9 f9
>   0x808a1750: 07 f9 f9 f9 f9 f9 f9 f9 00 00 00 00 02 f9 f9 f9
>   0x808a1760: f9 f9 f9 f9 00 00 00 00 00 00 00 05 f9 f9 f9 f9
>   0x808a1770: 00 02 f9 f9 f9 f9 f9 f9 00 00 00 00 00 00 00 00
>   0x808a1780: 00 00 02 f9 f9 f9 f9 f9 03 f9 f9 f9 f9 f9 f9 f9
> =>0x808a1790: 06 f9 f9 f9 f9 f9 f9 f9 00 00 01[f9]f9 f9 f9 f9
>   0x808a17a0: 00 00 00 00 00 07 f9 f9 f9 f9 f9 f9 01 f9 f9 f9
>   0x808a17b0: f9 f9 f9 f9 00 f9 f9 f9 f9 f9 f9 f9 06 f9 f9 f9
>   0x808a17c0: f9 f9 f9 f9 05 f9 f9 f9 f9 f9 f9 f9 00 00 00 00
>   0x808a17d0: 03 f9 f9 f9 f9 f9 f9 f9 00 02 f9 f9 f9 f9 f9 f9
>   0x808a17e0: 00 00 01 f9 f9 f9 f9 f9 00 00 00 00 04 f9 f9 f9
> Shadow byte legend (one shadow byte represents 8 application bytes):
>   Addressable:   00
>   Partially addressable: 01 02 03 04 05 06 07
>   Heap left redzone:   fa
>   Freed heap region:   fd
>   Stack left redzone:  f1
>   Stack mid redzone:   f2
>   Stack right redzone: f3
>   Stack after return:  f5
>   Stack use after scope:   f8
>   Global redzone:  f9
>   Global init order:   f6
>   Poisoned by user:f7
>   Container overflow:  fc
>   Array cookie:ac
>   Intra object redzone:bb
>   ASan internal:   fe
>   Left alloca redzone: ca
>   Right alloca redzone:cb
> ___
> gem5-dev mailing list
> gem5-dev@gem5.org
> http://m5sim.org/mailman/listinfo/gem5-dev
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Issue With X86 O3 CPU

2017-05-18 Thread Gross, Joe

Hello,

When running an application internally, with the address sanitizer enabled, I'm 
seeing a global buffer overflow in the x86 decoder during 
processExtendedOpcode() and wondered if anybody, possibly Gabe, would know a 
quick solution for this. If anybody would like a trace then I could generate 
this, but unfortunately the binaries that cause the problem are internal. The 
problem seems contained to decoding an unexpected opcode. Also the location 
changes slightly from application to application, so there may be several 
unsupported opcodes.

Joe

ERROR: AddressSanitizer: global-buffer-overflow on address 0x0454bcdf at pc 
0x00adb323 bp 0x7fff873f1870 sp 0x7fff873f1868
READ of size 1 at 0x0454bcdf thread T0
#0 0xadb322 in X86ISA::Decoder::processExtendedOpcode(unsigned char const 
(&) [256]) X86/arch/x86/decoder.cc:460:23
#1 0xadb322 in X86ISA::Decoder::doOneByteOpcodeState(unsigned char) 
X86/arch/x86/decoder.cc:299
#2 0xad890d in X86ISA::Decoder::process() X86/arch/x86/decoder.cc:113:21
#3 0x1f40de7 in X86ISA::Decoder::moreBytes(X86ISA::PCState const&, unsigned 
long, unsigned long) X86/arch/x86/decoder.hh:312:9
#4 0x1f40de7 in DefaultFetch::fetch(bool&) 
X86/cpu/o3/fetch_impl.hh:1313
#5 0x1f398fc in DefaultFetch::tick() 
X86/cpu/o3/fetch_impl.hh:947:9
#6 0x1ec2ba6 in FullO3CPU::tick() X86/cpu/o3/cpu.cc:565:11
#7 0x2eaa586 in EventQueue::serviceOne() X86/sim/eventq.cc:228:16
#8 0x2efd8d4 in doSimLoop(EventQueue*)  X86/sim/simulate.cc:219:37
#9 0x2efcd7d in simulate(unsigned long)  X86/sim/simulate.cc:132:26

0x0454bcdf is located 33 bytes to the left of global variable '' defined in 'X86/arch/x86/faults.cc:131:13' (0x454bd00) of size 47
  '' is ascii string 'Unrecognized/invalid instruction executed:
 %s'
0x0454bcdf is located 14 bytes to the right of global variable '' defined in 'X86/arch/x86/faults.cc:122:9' (0x454bcc0) of size 17
  '' is ascii string 'Abort exception!'
SUMMARY: AddressSanitizer: global-buffer-overflow 
X86/arch/x86/decoder.cc:460:23 in 
X86ISA::Decoder::processExtendedOpcode(unsigned char const (&) [256])
Shadow bytes around the buggy address:
  0x808a1740: 00 00 00 00 00 00 00 00 00 00 00 f9 f9 f9 f9 f9
  0x808a1750: 07 f9 f9 f9 f9 f9 f9 f9 00 00 00 00 02 f9 f9 f9
  0x808a1760: f9 f9 f9 f9 00 00 00 00 00 00 00 05 f9 f9 f9 f9
  0x808a1770: 00 02 f9 f9 f9 f9 f9 f9 00 00 00 00 00 00 00 00
  0x808a1780: 00 00 02 f9 f9 f9 f9 f9 03 f9 f9 f9 f9 f9 f9 f9
=>0x808a1790: 06 f9 f9 f9 f9 f9 f9 f9 00 00 01[f9]f9 f9 f9 f9
  0x808a17a0: 00 00 00 00 00 07 f9 f9 f9 f9 f9 f9 01 f9 f9 f9
  0x808a17b0: f9 f9 f9 f9 00 f9 f9 f9 f9 f9 f9 f9 06 f9 f9 f9
  0x808a17c0: f9 f9 f9 f9 05 f9 f9 f9 f9 f9 f9 f9 00 00 00 00
  0x808a17d0: 03 f9 f9 f9 f9 f9 f9 f9 00 02 f9 f9 f9 f9 f9 f9
  0x808a17e0: 00 00 01 f9 f9 f9 f9 f9 00 00 00 00 04 f9 f9 f9
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:   00
  Partially addressable: 01 02 03 04 05 06 07
  Heap left redzone:   fa
  Freed heap region:   fd
  Stack left redzone:  f1
  Stack mid redzone:   f2
  Stack right redzone: f3
  Stack after return:  f5
  Stack use after scope:   f8
  Global redzone:  f9
  Global init order:   f6
  Poisoned by user:f7
  Container overflow:  fc
  Array cookie:ac
  Intra object redzone:bb
  ASan internal:   fe
  Left alloca redzone: ca
  Right alloca redzone:cb
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: base, sim, arch: Fix clang 5.0 warnings

2017-05-18 Thread Andreas Sandberg (Gerrit)


Hello Curtis Dunham,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/3420

to review the following change.


Change subject: base, sim, arch: Fix clang 5.0 warnings
..

base, sim, arch: Fix clang 5.0 warnings

Compiling gem5 with recent version of clang (4 and 5) triggers
warnings that are treated as errors:

  * Global templatized static functions result in a warning if they
are not used. These should either be declared as static inline or
without the static identifier to avoid the warning.

  * Some templatized classes contain static variables. The
instantiated versions of these variables / templates need to be
explicitly declared to avoid a compiler warning.

Change-Id: Ie8261144836e94ebab7ea04b90927672c257
Signed-off-by: Andreas Sandberg 
Reviewed-by: Curtis Dunham 
---
M src/arch/arm/faults.hh
M src/arch/arm/insts/vfp.hh
M src/arch/arm/isa/insts/fp.isa
M src/arch/hsail/insts/decl.hh
M src/arch/mips/faults.hh
M src/arch/sparc/faults.hh
M src/base/circlebuf.hh
M src/sim/syscall_emul.hh
8 files changed, 125 insertions(+), 15 deletions(-)



diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index ab4c675..6e7c92c 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -567,7 +567,8 @@
 };

 /*
- * Explicitly declare template static member variables avoid warnings in  
some clang versions

+ * Explicitly declare template static member variables to avoid warnings
+ * in some clang versions
  */
 template<> ArmFault::FaultVals ArmFaultVals::vals;
 template<> ArmFault::FaultVals ArmFaultVals::vals;
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index de0c621..caa2237 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -201,7 +201,7 @@
 }

 template 
-static bool
+static inline bool
 isSnan(fpType val)
 {
 const bool single = (sizeof(fpType) == sizeof(float));
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 0f10a05..dc2f307 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -65,7 +65,7 @@
 };

 template 
-static StaticInstPtr
+StaticInstPtr
 decodeVfpRegRegOp(ExtMachInst machInst,
 IntRegIndex dest, IntRegIndex op1, bool wide)
 {
@@ -101,7 +101,7 @@
 };

 template 
-static StaticInstPtr
+StaticInstPtr
 decodeVfpRegImmOp(ExtMachInst machInst,
 IntRegIndex dest, uint64_t imm, bool wide)
 {
@@ -137,7 +137,7 @@
 };

 template 
-static StaticInstPtr
+StaticInstPtr
 decodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest,
  IntRegIndex op1, uint64_t imm, bool wide)
 {
@@ -173,7 +173,7 @@
 };

 template 
-static StaticInstPtr
+StaticInstPtr
 decodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest,
  IntRegIndex op1, IntRegIndex op2, bool wide)
 {
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index f84cb61..3132a42 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -1272,6 +1272,27 @@

 template T heynot(T arg) { return ~arg; }
 template<> inline bool heynot(bool arg) { return !arg; }
+
+
+/* Explicitly declare template static member variables to avoid
+ * warnings in some clang versions
+ */
+template<> const char *B1::label;
+template<> const char *B8::label;
+template<> const char *B16::label;
+template<> const char *B32::label;
+template<> const char *B64::label;
+template<> const char *S8::label;
+template<> const char *S16::label;
+template<> const char *S32::label;
+template<> const char *S64::label;
+template<> const char *U8::label;
+template<> const char *U16::label;
+template<> const char *U32::label;
+template<> const char *U64::label;
+template<> const char *F32::label;
+template<> const char *F64::label;
+
 } // namespace HsailISA

 #endif // __ARCH_HSAIL_INSTS_DECL_HH__
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 1ec726d..dcce764 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -303,6 +303,30 @@
 ExcCode code() const { return MipsFault::code(); }
 };

+/*
+ * Explicitly declare template static member variables to avoid warnings
+ * in some clang versions
+ */
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals  
MipsFault::vals;

+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;
+template<> MipsFaultBase::FaultVals MipsFault::vals;

[gem5-dev] Change in public/gem5[master]: python: Remove unused readline import

2017-05-18 Thread Andreas Sandberg (Gerrit)

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/3421



Change subject: python: Remove unused readline import
..

python: Remove unused readline import

The readline module is imported by main.py but doesn't seem to be
used.

Change-Id: I7888e3b6ad0a0fedc14b0feec2adf0a39883bbf8
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/main.py
1 file changed, 0 insertions(+), 4 deletions(-)



diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 4931430..ad45288 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -410,10 +410,6 @@
 scope = { '__file__' : filename,
   '__name__' : '__m5_main__' }

-# we want readline if we're doing anything interactive
-if options.interactive or options.pdb:
-exec "import readline" in scope
-
 # if pdb was requested, execfile the thing under pdb, otherwise,
 # just do the execfile normally
 if options.pdb:

--
To view, visit https://gem5-review.googlesource.com/3421
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7888e3b6ad0a0fedc14b0feec2adf0a39883bbf8
Gerrit-Change-Number: 3421
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: base: Refactor the GDB code.

2017-05-18 Thread Gabe Black (Gerrit)

Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3280 )


Change subject: base: Refactor the GDB code.
..

base: Refactor the GDB code.

The new version modularizes the implementation of the various commands,
gets rid of dynamic allocation of the register cache, fixes some small
style problems, and uses exceptions to simplify error handling internal to
the GDB stub.

Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2
Reviewed-on: https://gem5-review.googlesource.com/3280
Reviewed-by: Andreas Sandberg 
Reviewed-by: Boris Shingarov 
Maintainer: Andreas Sandberg 
---
M src/arch/alpha/remote_gdb.cc
M src/arch/alpha/remote_gdb.hh
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/remote_gdb.hh
M src/arch/x86/remote_gdb.cc
M src/arch/x86/remote_gdb.hh
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
16 files changed, 543 insertions(+), 505 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Boris Shingarov: Looks good to me, approved



diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index 8c01005..a9ec4cf 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -262,12 +262,12 @@
 }


-bool
+void
 RemoteGDB::insertHardBreak(Addr addr, size_t len)
 {
 warn_once("Breakpoints do not work in Alpha PAL mode.\n"
   "  See PCEventQueue::doService() in cpu/pc_event.cc.\n");
-return BaseRemoteGDB::insertHardBreak(addr, len);
+BaseRemoteGDB::insertHardBreak(addr, len);
 }

 RemoteGDB::BaseGdbRegCache*
diff --git a/src/arch/alpha/remote_gdb.hh b/src/arch/alpha/remote_gdb.hh
index 4b71fd2..38ff919 100644
--- a/src/arch/alpha/remote_gdb.hh
+++ b/src/arch/alpha/remote_gdb.hh
@@ -53,7 +53,7 @@
 bool acc(Addr addr, size_t len);
 bool write(Addr addr, size_t size, const char *data);

-bool insertHardBreak(Addr addr, size_t len);
+void insertHardBreak(Addr addr, size_t len) override;

 class AlphaGdbRegCache : public BaseGdbRegCache
 {
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index b0f6d8e..eefe62b 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -165,7 +165,7 @@
 using namespace ArmISA;

 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
-: BaseRemoteGDB(_system, tc)
+: BaseRemoteGDB(_system, tc), regCache32(this), regCache64(this)
 {
 }

@@ -297,7 +297,7 @@
 RemoteGDB::gdbRegs()
 {
 if (inAArch64(context))
-return new AArch64GdbRegCache(this);
+return 
 else
-return new AArch32GdbRegCache(this);
+return 
 }
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 13ceac1..acd6f32 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -79,7 +79,11 @@
 size_t size() const { return sizeof(r); }
 void getRegs(ThreadContext*);
 void setRegs(ThreadContext*) const;
-const std::string name() const { return gdb->name()  
+ ".AArch32GdbRegCache"; }

+const std::string
+name() const
+{
+return gdb->name() + ".AArch32GdbRegCache";
+}
 };

 class AArch64GdbRegCache : public BaseGdbRegCache
@@ -98,9 +102,16 @@
 size_t size() const { return sizeof(r); }
 void getRegs(ThreadContext*);
 void setRegs(ThreadContext*) const;
-const std::string name() const { return gdb->name()  
+ ".AArch64GdbRegCache"; }

+const std::string
+name() const
+{
+return gdb->name() + ".AArch64GdbRegCache";
+}
 };

+AArch32GdbRegCache regCache32;
+AArch64GdbRegCache regCache64;
+
   public:
 RemoteGDB(System *_system, ThreadContext *tc);
 BaseGdbRegCache *gdbRegs();
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 4fa7cac..2cc2d77 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -152,7 +152,7 @@
 using namespace MipsISA;

 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
-: BaseRemoteGDB(_system, tc)
+: BaseRemoteGDB(_system, tc), regCache(this)
 {
 }

@@ -207,5 +207,5 @@

 RemoteGDB::BaseGdbRegCache*
 RemoteGDB::gdbRegs() {
-return new MipsGdbRegCache(this);
+return 
 }
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index fd006e0..fba55d8 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -70,9 +70,14 @@
 size_t size() const { return sizeof(r); }
 void getRegs(ThreadContext*);
 void setRegs(ThreadContext*) const;
-

[gem5-dev] Change in public/gem5[master]: syscall_emul, riscv: add override keyword to RISCV Process c...

2017-05-18 Thread Brandon Potter (Gerrit)

Brandon Potter has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3360 )


Change subject: syscall_emul, riscv: add override keyword to RISCV Process  
class

..

syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Alec Roelke 
---
M src/arch/riscv/process.hh
1 file changed, 6 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index f732a44..2a27f35 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -48,17 +48,19 @@
   protected:
 RiscvProcess(ProcessParams * params, ObjectFile *objFile);

-void initState();
+void initState() override;

 template
 void argsInit(int pageSize);

   public:
-RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int );
+RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int ) override;
 /// Explicitly import the otherwise hidden getSyscallArg
 using Process::getSyscallArg;
-void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
-void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+void setSyscallArg(ThreadContext *tc, int i,
+   RiscvISA::IntReg val) override;
+void setSyscallReturn(ThreadContext *tc,
+  SyscallReturn return_value) override;

 virtual bool mmapGrowsDown() const override { return false; }
 };

--
To view, visit https://gem5-review.googlesource.com/3360
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Gerrit-Change-Number: 3360
Gerrit-PatchSet: 2
Gerrit-Owner: Brandon Potter 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: configs: fix cpu names in big.LITTLE example

2017-05-18 Thread Pierre-Yves Péneau (Gerrit)

Pierre-Yves Péneau has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3300 )


Change subject: configs: fix cpu names in big.LITTLE example
..

configs: fix cpu names in big.LITTLE example

CPU aliases have been dropped, this change fixes the big.LITTLE example.

Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Signed-off-by: Pierre-Yves Péneau 
Reviewed-on: https://gem5-review.googlesource.com/3300
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 3e7ac2f..4f548b1 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -84,7 +84,7 @@
 class BigCluster(devices.CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock,
  cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("arm_detailed"), devices.L1I,  
devices.L1D,
+cpu_config = [ CpuConfig.get("O3_ARM_v7a_3"), devices.L1I,  
devices.L1D,

 devices.WalkCache, devices.L2 ]
 super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
  cpu_voltage, *cpu_config)
@@ -92,7 +92,7 @@
 class LittleCluster(devices.CpuCluster):
 def __init__(self, system, num_cpus, cpu_clock,
  cpu_voltage="1.0V"):
-cpu_config = [ CpuConfig.get("minor"), devices.L1I, devices.L1D,
+cpu_config = [ CpuConfig.get("MinorCPU"), devices.L1I, devices.L1D,
devices.WalkCache, devices.L2 ]
 super(LittleCluster, self).__init__(system, num_cpus, cpu_clock,
  cpu_voltage, *cpu_config)

--
To view, visit https://gem5-review.googlesource.com/3300
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Gerrit-Change-Number: 3300
Gerrit-PatchSet: 3
Gerrit-Owner: Pierre-Yves Péneau 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Pierre-Yves Péneau 
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE

2017-05-18 Thread Pierre-Yves Péneau (Gerrit)

Pierre-Yves Péneau has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2464 )


Change subject: arm, config: added support for ex5 model of big.LITTLE
..

arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE cores, ex5_big and
ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5
model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory
hierarchy latencies have been calibrated using the lmbench micro-benchmark
suite. The preliminary validation results have been published  
as: 'Full-System

Simulation of big.LITTLE Multicore Architecture for Performance and Energy
Exploration', in International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016).

From http://reviews.gem5.org/r/3666

Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Signed-off-by: Anastasiia Butko 
Signed-off-by: Pierre-Yves Péneau 
Reviewed-on: https://gem5-review.googlesource.com/2464
Reviewed-by: Gabor Dozsa 
Maintainer: Jason Lowe-Power 
---
M configs/common/CpuConfig.py
A configs/common/ex5_LITTLE.py
A configs/common/ex5_big.py
M configs/example/arm/fs_bigLITTLE.py
4 files changed, 392 insertions(+), 0 deletions(-)

Approvals:
  Gabor Dozsa: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 8810622..28267c7 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -117,6 +117,20 @@
 except:
 pass

+# The calibrated ex5-model cores
+try:
+from ex5_LITTLE import ex5_LITTLE
+_cpu_classes["ex5_LITTLE"] = ex5_LITTLE
+except:
+ pass
+
+try:
+from ex5_big import ex5_big
+_cpu_classes["ex5_big"] = ex5_big
+except:
+ pass
+
+
 # Add all CPUs in the object hierarchy.
 for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
 _cpu_classes[name] = cls
diff --git a/configs/common/ex5_LITTLE.py b/configs/common/ex5_LITTLE.py
new file mode 100644
index 000..c9c419f
--- /dev/null
+++ b/configs/common/ex5_LITTLE.py
@@ -0,0 +1,154 @@
+# Copyright (c) 2012 The Regents of The University of Michigan
+# Copyright (c) 2016 Centre National de la Recherche Scientifique
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+#  Anastasiia Butko
+#  Louisa Bessad
+
+from m5.objects import *
+from O3_ARM_v7a import *
+from Caches import *
+
+#---
+#ex5 LITTLE core (based on the ARM Cortex-A7)
+#---
+
+# Simple ALU Instructions have a latency of 3
+class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
+opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
+
+# Complex ALU instructions have a variable latencies
+class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
+opList = [ OpDesc(opClass='IntMult', opLat=7) ]
+
+class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
+opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
+
+# Floating point and SIMD instructions
+class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
+opList = [ OpDesc(opClass='SimdAdd', opLat=6),
+   OpDesc(opClass='SimdAddAcc', opLat=4),
+   OpDesc(opClass='SimdAlu',

[gem5-dev] Change in public/gem5[master]: configs, arm: add option to enable security extensions

2017-05-18 Thread Gedare Bloom (Gerrit)


Hello Jason Lowe-Power, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/3264

to look at the new patch set (#4).

Change subject: configs, arm: add option to enable security extensions
..

configs, arm: add option to enable security extensions

Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c
Signed-off-by: Gedare Bloom 
---
M configs/common/FSConfig.py
M configs/common/Options.py
M configs/example/fs.py
3 files changed, 7 insertions(+), 2 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/3264
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c
Gerrit-Change-Number: 3264
Gerrit-PatchSet: 4
Gerrit-Owner: Gedare Bloom 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gedare Bloom 
Gerrit-Reviewer: Jason Lowe-Power 
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE

2017-05-18 Thread Pierre-Yves Péneau (Gerrit)


Hello Jason Lowe-Power, Gabor Dozsa, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2464

to look at the new patch set (#3).

Change subject: arm, config: added support for ex5 model of big.LITTLE
..

arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE cores, ex5_big and
ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5
model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory
hierarchy latencies have been calibrated using the lmbench micro-benchmark
suite. The preliminary validation results have been published  
as: 'Full-System

Simulation of big.LITTLE Multicore Architecture for Performance and Energy
Exploration', in International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016).

From http://reviews.gem5.org/r/3666

Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Signed-off-by: Anastasiia Butko 
Signed-off-by: Pierre-Yves Péneau 
---
M configs/common/CpuConfig.py
A configs/common/ex5_LITTLE.py
A configs/common/ex5_big.py
M configs/example/arm/fs_bigLITTLE.py
4 files changed, 392 insertions(+), 0 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/2464
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Gerrit-Change-Number: 2464
Gerrit-PatchSet: 3
Gerrit-Owner: Pierre-Yves Péneau 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Pierre-Yves Péneau 
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

2017-05-18 Thread Matthias Jung (Gerrit)

Matthias Jung has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2240 )


Change subject: ext: Include SystemC 2.3.1 into gem5
..

ext: Include SystemC 2.3.1 into gem5

In the past it happened several times that some changes in gem5 broke the
SystemC coupling. Recently Accelera has changed the licence for SystemC
from their own licence to Apache2.0, which is compatible with gem5.
However, SystemC usually relies on the Boost library, but I was able to
exchange the boost calls by c++11 alternatives. The recent SystemC version
is placed into /ext and is integrated into gem5's build system. The goal is
to integrate some SystemC tests for the CI in some following patches.

Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0
Reviewed-on: https://gem5-review.googlesource.com/2240
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
A ext/systemc/AUTHORS
A ext/systemc/ChangeLog
A ext/systemc/INSTALL
A ext/systemc/LICENSE
A ext/systemc/NEWS
A ext/systemc/NOTICE
A ext/systemc/README.gem5.md
A ext/systemc/README.md
A ext/systemc/README.sysc
A ext/systemc/RELEASENOTES
A ext/systemc/SConscript
A ext/systemc/src/README_TLM.txt
A ext/systemc/src/sysc/communication/sc_buffer.h
A ext/systemc/src/sysc/communication/sc_clock.cpp
A ext/systemc/src/sysc/communication/sc_clock.h
A ext/systemc/src/sysc/communication/sc_clock_ports.h
A ext/systemc/src/sysc/communication/sc_communication_ids.h
A ext/systemc/src/sysc/communication/sc_event_finder.cpp
A ext/systemc/src/sysc/communication/sc_event_finder.h
A ext/systemc/src/sysc/communication/sc_event_queue.cpp
A ext/systemc/src/sysc/communication/sc_event_queue.h
A ext/systemc/src/sysc/communication/sc_export.cpp
A ext/systemc/src/sysc/communication/sc_export.h
A ext/systemc/src/sysc/communication/sc_fifo.h
A ext/systemc/src/sysc/communication/sc_fifo_ifs.h
A ext/systemc/src/sysc/communication/sc_fifo_ports.h
A ext/systemc/src/sysc/communication/sc_host_mutex.h
A ext/systemc/src/sysc/communication/sc_interface.cpp
A ext/systemc/src/sysc/communication/sc_interface.h
A ext/systemc/src/sysc/communication/sc_mutex.cpp
A ext/systemc/src/sysc/communication/sc_mutex.h
A ext/systemc/src/sysc/communication/sc_mutex_if.h
A ext/systemc/src/sysc/communication/sc_port.cpp
A ext/systemc/src/sysc/communication/sc_port.h
A ext/systemc/src/sysc/communication/sc_prim_channel.cpp
A ext/systemc/src/sysc/communication/sc_prim_channel.h
A ext/systemc/src/sysc/communication/sc_semaphore.cpp
A ext/systemc/src/sysc/communication/sc_semaphore.h
A ext/systemc/src/sysc/communication/sc_semaphore_if.h
A ext/systemc/src/sysc/communication/sc_signal.cpp
A ext/systemc/src/sysc/communication/sc_signal.h
A ext/systemc/src/sysc/communication/sc_signal_ifs.h
A ext/systemc/src/sysc/communication/sc_signal_ports.cpp
A ext/systemc/src/sysc/communication/sc_signal_ports.h
A ext/systemc/src/sysc/communication/sc_signal_resolved.cpp
A ext/systemc/src/sysc/communication/sc_signal_resolved.h
A ext/systemc/src/sysc/communication/sc_signal_resolved_ports.cpp
A ext/systemc/src/sysc/communication/sc_signal_resolved_ports.h
A ext/systemc/src/sysc/communication/sc_signal_rv.h
A ext/systemc/src/sysc/communication/sc_signal_rv_ports.h
A ext/systemc/src/sysc/communication/sc_writer_policy.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_bit.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit_ids.h
A ext/systemc/src/sysc/datatypes/bit/sc_bit_proxies.h
A ext/systemc/src/sysc/datatypes/bit/sc_bv.h
A ext/systemc/src/sysc/datatypes/bit/sc_bv_base.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_bv_base.h
A ext/systemc/src/sysc/datatypes/bit/sc_logic.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_logic.h
A ext/systemc/src/sysc/datatypes/bit/sc_lv.h
A ext/systemc/src/sysc/datatypes/bit/sc_lv_base.cpp
A ext/systemc/src/sysc/datatypes/bit/sc_lv_base.h
A ext/systemc/src/sysc/datatypes/bit/sc_proxy.h
A ext/systemc/src/sysc/datatypes/fx/fx.h
A ext/systemc/src/sysc/datatypes/fx/sc_context.h
A ext/systemc/src/sysc/datatypes/fx/sc_fix.h
A ext/systemc/src/sysc/datatypes/fx/sc_fixed.h
A ext/systemc/src/sysc/datatypes/fx/sc_fx_ids.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxcast_switch.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxcast_switch.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxdefs.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxdefs.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum_observer.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxnum_observer.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxtype_params.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxtype_params.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxval.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxval.h
A ext/systemc/src/sysc/datatypes/fx/sc_fxval_observer.cpp
A ext/systemc/src/sysc/datatypes/fx/sc_fxval_observer.h

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2017-05-18 Thread Cron Daemon

* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: CHANGED!
*** diff[config.ini]: SKIPPED* 
build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic: CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: 
CHANGED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: 
CHANGED!
 --- quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby ---* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby:
 CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby:
 CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: 
passed.* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby:
 CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: 
CHANGED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: 
CHANGED!
 *** diff[config.ini]: SKIPPED* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic: 
CHANGED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby:
 CHANGED!*** diff[simout]: SKIPPED
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing: 
CHANGED!
scons: *** [build/ALPHA/encumbered/eio/libexo.do] Error 1
scons: *** [build/ALPHA/encumbered/eio/eio.do] Error 1
scons: *** [build/ALPHA/encumbered/eio/libexo.fo] Error 1
scons: *** [build/ALPHA/encumbered/eio/eio.fo] Error 1
scons: *** [build/ALPHA/encumbered/eio/libexo.o] Error 1
scons: *** [build/ALPHA/encumbered/eio/eio.o] Error 1
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: passed.
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 passed.
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 passed.
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 passed.
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: passed.
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: passed.
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 passed.
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 passed.
*

Re: [gem5-dev] Issue With X86 O3 CPU

[gem5-dev] Issue With X86 O3 CPU

[gem5-dev] Change in public/gem5[master]: base, sim, arch: Fix clang 5.0 warnings

[gem5-dev] Change in public/gem5[master]: python: Remove unused readline import

[gem5-dev] Change in public/gem5[master]: base: Refactor the GDB code.

[gem5-dev] Change in public/gem5[master]: syscall_emul, riscv: add override keyword to RISCV Process c...

[gem5-dev] Change in public/gem5[master]: configs: fix cpu names in big.LITTLE example

[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE

[gem5-dev] Change in public/gem5[master]: configs, arm: add option to enable security extensions

[gem5-dev] Change in public/gem5[master]: arm, config: added support for ex5 model of big.LITTLE

[gem5-dev] Change in public/gem5[master]: ext: Include SystemC 2.3.1 into gem5

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

12 matches

Site Navigation

Mail list logo

Footer information