[gem5-dev] Change in public/gem5[master]: config, arm: FS configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4202 )


Change subject: config, arm: FS configuration for the ARM starter kit
..

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4202
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
A configs/example/arm/starter_fs.py
1 file changed, 242 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

new file mode 100644
index 000..9b6f68f
--- /dev/null
+++ b/configs/example/arm/starter_fs.py
@@ -0,0 +1,242 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  Authors:  Andreas Sandberg
+#Chuan Zhu
+#Gabor Dozsa
+#
+
+"""This script is the full system example script from the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+"""
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+
+m5.util.addToPath('../..')
+
+from common import SysPaths
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+default_dist_version = '20170616'
+default_kernel = 'vmlinux.vexpress_gem5_v1_64.' + default_dist_version
+default_disk = 'linaro-minimal-aarch64.img'
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+
+"atomic" : ( AtomicSimpleCPU, None, None, None, None),
+"minor" : (MinorCPU,
+   devices.L1I, devices.L1D,
+   devices.WalkCache,
+   devices.L2),
+"hpi" : ( HPI.HPI,
+  HPI.HPI_ICache, HPI.HPI_DCache,
+  HPI.HPI_WalkCache,
+  HPI.HPI_L2)
+}
+
+def create_cow_image(name):
+"""Helper function to create a Copy-on-Write disk image"""
+image = CowDiskImage()
+image.child.image_file = SysPaths.disk(name)
+
+return image;
+
+
+def create(args):
+''' Create and configure the system object. '''
+
+if not args.dtb:
+dtb_file = SysPaths.binary("armv8_gem5_v1_%icpu.%s.dtb" %
+

[gem5-dev] Change in public/gem5[master]: config, arm: SE configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4203 )


Change subject: config, arm: SE configuration for the ARM starter kit
..

config, arm: SE configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4203
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
A configs/example/arm/starter_se.py
1 file changed, 233 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

new file mode 100644
index 000..902e6e4
--- /dev/null
+++ b/configs/example/arm/starter_se.py
@@ -0,0 +1,233 @@
+# Copyright (c) 2016-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#  Authors:  Andreas Sandberg
+#Chuan Zhu
+#Gabor Dozsa
+#
+
+"""This script is the syscall emulation example script from the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+"""
+
+import os
+import m5
+from m5.util import addToPath
+from m5.objects import *
+import argparse
+import shlex
+
+m5.util.addToPath('../..')
+
+from common import MemConfig
+from common.cores.arm import HPI
+
+import devices
+
+
+
+# Pre-defined CPU configurations. Each tuple must be ordered as :  
(cpu_class,
+# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any  
of

+# the cache class may be 'None' if the particular cache is not present.
+cpu_types = {
+"atomic" : ( AtomicSimpleCPU, None, None, None, None),
+"minor" : (MinorCPU,
+   devices.L1I, devices.L1D,
+   devices.WalkCache,
+   devices.L2),
+"hpi" : ( HPI.HPI,
+  HPI.HPI_ICache, HPI.HPI_DCache,
+  HPI.HPI_WalkCache,
+  HPI.HPI_L2)
+}
+
+
+class SimpleSeSystem(System):
+'''
+Example system class for syscall emulation mode
+'''
+
+# Use a fixed cache line size of 64 bytes
+cache_line_size = 64
+
+def __init__(self, args, **kwargs):
+super(SimpleSeSystem, self).__init__(**kwargs)
+
+# Setup book keeping to be able to use CpuClusters from the
+# devices module.
+self._clusters = []
+self._num_cpus = 0
+
+# Create a voltage and clock domain for system components
+self.voltage_domain = 

[gem5-dev] Change in public/gem5[master]: config, arm: Add a high-performance in order timing model

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4201 )


Change subject: config, arm: Add a high-performance in order timing model
..

config, arm: Add a high-performance in order timing model

The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi 
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4201
Reviewed-by: Jason Lowe-Power 
---
A configs/common/cores/arm/HPI.py
1 file changed, 1,454 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/common/cores/arm/HPI.py  
b/configs/common/cores/arm/HPI.py

new file mode 100644
index 000..03bad24
--- /dev/null
+++ b/configs/common/cores/arm/HPI.py
@@ -0,0 +1,1454 @@
+# Copyright (c) 2014-2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andrew Bardsley
+#
+
+"""The High-Performance In-order (HPI) CPU timing model is tuned to be
+representative of a modern in-order ARMv8-A implementation. The HPI
+core and its supporting simulation scripts, namely starter_se.py and
+starter_fs.py (under /configs/example/arm/) are part of the ARM
+Research Starter Kit on System Modeling. More information can be found
+at: http://www.arm.com/ResearchEnablement/SystemModeling
+
+"""
+
+from m5.objects import *
+
+# Simple function to allow a string of [01x_] to be converted into a
+# mask and value for use with MinorFUTiming
+def make_implicant(implicant_string):
+ret_mask = 0
+ret_match = 0
+
+shift = False
+for char in implicant_string:
+char = char.lower()
+if shift:
+ret_mask <<= 1
+ret_match <<= 1
+
+shift = True
+if char == '_':
+shift = False
+elif char == '0':
+ret_mask |= 1
+elif char == '1':
+ret_mask |= 1
+ret_match |= 1
+elif char == 'x':
+pass
+else:
+print "Can't parse implicant character", char
+
+return (ret_mask, ret_match)
+
+#  ,- 36 thumb
+#  | ,--- 35 bigThumb
+#  | |,-- 34 aarch64
+a64_inst =  
make_implicant('0_01xx__________')
+a32_inst =  

[gem5-dev] Change in public/gem5[master]: config: Change mem_range attribute naming in ARM SimpleSystem

[Andreas Sandberg (Gerrit)]

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4200 )


Change subject: config: Change mem_range attribute naming in ARM  
SimpleSystem

..

config: Change mem_range attribute naming in ARM SimpleSystem

MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.

Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa 
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/4200
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M configs/example/arm/devices.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index f7375cd..467d2b9 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -209,13 +209,13 @@
 mem_range = self.realview._mem_regions[0]
 mem_range_size = long(mem_range[1]) - long(mem_range[0])
 assert mem_range_size >= long(Addr(mem_size))
-self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
+self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ]
 self._caches = caches
 if self._caches:
-self.iocache = IOCache(addr_ranges=[self._mem_range])
+self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 else:
 self.dmabridge = Bridge(delay='50ns',
-ranges=[self._mem_range])
+ranges=[self.mem_ranges[0]])

 self._pci_devices = 0
 self._clusters = []

--
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To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Gerrit-Change-Number: 4200
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: config, mem, hmc: fix HMC test script

[Éder F. Zulian (Gerrit)]

Éder F. Zulian has uploaded a new patch set (#5). (  
https://gem5-review.googlesource.com/4120 )


Change subject: config, mem, hmc: fix HMC test script
..

config, mem, hmc: fix HMC test script

This patch keeps the logic behind the HMC model implementation untouched.

Additional changes:
- simple hello world script using HMC (SE simulation)

Usage examples:

./build/ARM/gem5.opt configs/example/hmctest.py
./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor  
--enable-link-monitor --arch=same
./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor  
--enable-link-monitor --arch=mixed

./build/ARM/gem5.opt configs/example/hmc_hello.py
./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor  
--enable-link-monitor


Change-Id: Ibcac21e717a93473265f7710b23d3d5512e2bad1
---
M configs/common/HMC.py
A configs/example/hmc_hello.py
A configs/example/hmc_tgen.cfg
M configs/example/hmctest.py
4 files changed, 422 insertions(+), 251 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ibcac21e717a93473265f7710b23d3d5512e2bad1
Gerrit-Change-Number: 4120
Gerrit-PatchSet: 5
Gerrit-Owner: Éder F. Zulian 
Gerrit-Reviewer: Éder F. Zulian 
Gerrit-CC: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: config, arm: FS configuration for the ARM starter kit

[Andreas Sandberg (Gerrit)]

Hello Jason Lowe-Power, Gabor Dozsa,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4202

to look at the new patch set (#3).

Change subject: config, arm: FS configuration for the ARM starter kit
..

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa 
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg 
---
A configs/example/arm/starter_fs.py
1 file changed, 242 insertions(+), 0 deletions(-)


--
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To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Gerrit-Change-Number: 4202
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabor Dozsa 
Gerrit-Reviewer: Jason Lowe-Power 
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Re: [gem5-dev] running system C models as gem5 SimObjects

[Gabe Black]

I worked on a project with gem5 a while ago where I added context switching
to create something pretty similar to what I understand SC_THREADs to be
using a standard library call (I think) that I forget the name of, so that
part isn't that scary and hopefully wouldn't be too heavy weight. The book
I'm reading makes it sound like the system C scheduler is single threaded
and just switches contexts in and out on the same thread, but the code I
poked at in the gem5 tree seemed to be using pthreads, etc., which would
suggest multiple simultaneous threads. But gem5 can run multithreaded now
too, right? I think I saw some support for that in the code.

If there really is a significant performance penalty using TLM, I wonder if
their simulation kernel has similar issues? I'd be more inclined to adapt
the system C APIs to be a client of the gem5 event queue, but I'm probably
biased since I'm much more familiar with the gem5 one. I'd think either
absorbing an external system C implementation into gem5 or vice versa would
be pretty hairy from a code management perspective.

In any case, I'm glad to hear that there would be some interest if we were
to push in that direction.

Gabe

On Thu, Jul 27, 2017 at 12:14 AM, Andreas Hansson 
wrote:

> Hi Gabe,
>
> The similarity between TLM2 and gem5 is not accidental. We did a lot of
> work in 2011 and 2012 to make it that way. In fact, we even created a
> version of the gem5 ports that use the 4-phase TLM2 non-blocking protocol,
> but ended up never pushing it as it has a fairly sizeable negative
> performance impact (15% or so if I remember correctly). We also separated
> the actual protocol from the physical port, as in TLM2
> (http://reviews.gem5.org/r/1301/), but ended up never pushing it, again
> for performance reasons. I still think it would make sense to try and
> align the two, but there are undoubtedly challenges.
>
> When it comes to the simulation kernel, the problem you will run into is
> that SystemC supports both blocking and non-blocking modelling semantics.
> gem5 should be able to wrap SC_METHODS without problems, but will not be
> able to deal with SC_THREAD and SC_CTHREAD without the addition of some
> form of threading/fibres/contexts. There has been work done in the bast to
> add boost fibres to gem5 (we never posted this), and it is definitely
> doable, but the devil is in the details.
>
> Overall I strongly support aligning gem5 and SystemC further. The best
> outcome, in my view, would be if gem5 was transitioned to work on the
> SystemC kernel, allowing interoperability and more elaborate event
> semantics, and then also transitioned to use the TLM ports. That would be
> quite a work package though.
>
> Andreas
>
> On 26/07/2017, 01:53, "gem5-dev on behalf of Gabe Black"
>  wrote:
>
> >Hi folks. As a part of some work I'm doing, I've been considering what it
> >would take to run system C models inside gem5 as SimObjects. I'm working
> >through some reading material I have about system C, but I haven't
> >actually
> >tried writing any of it yet. This seems similar to the work that was done
> >to allow running gem5 as a system C model, but sort of in reverse and at a
> >finer granularity, ie each object as its own thing and not system C as a
> >large black box.
> >
> >One thing I was wondering is what sort of complications might make that
> >not
> >work out. So far, I can imagine how to adapt the system C model into gem5
> >without too much fuss, but there's still a lot of pages left in the book
> >I'm reading and I haven't touched the actual spec yet. What was the
> >thinking behind putting gem5 into system C and not doing something like
> >what I'm thinking of?
> >
> >Another thing I'm wondering about is whether it would make sense to try to
> >replace gem5's port protocol with the one in system C. Obviously that
> >would
> >involve touching a lot of code, but I was surprised at how similar the
> >system C port setup and the gem5 one are. It might be nice generally to
> >use
> >a standardized mechanism that people might already be familiar with and
> >have an implementation against. That might also obviate the
> >bridging/adapter ports that are in the current system C/gem5 integration
> >mechanism. Thoughts?
> >
> >Gabe
> >___
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Re: [gem5-dev] running system C models as gem5 SimObjects

[Andreas Hansson]

Hi Gabe,

The similarity between TLM2 and gem5 is not accidental. We did a lot of
work in 2011 and 2012 to make it that way. In fact, we even created a
version of the gem5 ports that use the 4-phase TLM2 non-blocking protocol,
but ended up never pushing it as it has a fairly sizeable negative
performance impact (15% or so if I remember correctly). We also separated
the actual protocol from the physical port, as in TLM2
(http://reviews.gem5.org/r/1301/), but ended up never pushing it, again
for performance reasons. I still think it would make sense to try and
align the two, but there are undoubtedly challenges.

When it comes to the simulation kernel, the problem you will run into is
that SystemC supports both blocking and non-blocking modelling semantics.
gem5 should be able to wrap SC_METHODS without problems, but will not be
able to deal with SC_THREAD and SC_CTHREAD without the addition of some
form of threading/fibres/contexts. There has been work done in the bast to
add boost fibres to gem5 (we never posted this), and it is definitely
doable, but the devil is in the details.

Overall I strongly support aligning gem5 and SystemC further. The best
outcome, in my view, would be if gem5 was transitioned to work on the
SystemC kernel, allowing interoperability and more elaborate event
semantics, and then also transitioned to use the TLM ports. That would be
quite a work package though.

Andreas

On 26/07/2017, 01:53, "gem5-dev on behalf of Gabe Black"
 wrote:

>Hi folks. As a part of some work I'm doing, I've been considering what it
>would take to run system C models inside gem5 as SimObjects. I'm working
>through some reading material I have about system C, but I haven't
>actually
>tried writing any of it yet. This seems similar to the work that was done
>to allow running gem5 as a system C model, but sort of in reverse and at a
>finer granularity, ie each object as its own thing and not system C as a
>large black box.
>
>One thing I was wondering is what sort of complications might make that
>not
>work out. So far, I can imagine how to adapt the system C model into gem5
>without too much fuss, but there's still a lot of pages left in the book
>I'm reading and I haven't touched the actual spec yet. What was the
>thinking behind putting gem5 into system C and not doing something like
>what I'm thinking of?
>
>Another thing I'm wondering about is whether it would make sense to try to
>replace gem5's port protocol with the one in system C. Obviously that
>would
>involve touching a lot of code, but I was surprised at how similar the
>system C port setup and the gem5 one are. It might be nice generally to
>use
>a standardized mechanism that people might already be familiar with and
>have an implementation against. That might also obviate the
>bridging/adapter ports that are in the current system C/gem5 integration
>mechanism. Thoughts?
>
>Gabe
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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

[Cron Daemon]

* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: FAILED!
 * build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: 
FAILED!gem5 exited with non-zero status: 1
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic: FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby: 
FAILED!*** diff[config.ini]: SKIPPED
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: 
FAILED!
 * 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!*** gem5 stderr ***
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
*** stat_diff: SKIPPED* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic: 
FAILED!
*** diff[config.json]: SKIPPED* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing: 
FAILED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing: 
CHANGED!*** gem5: OK
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 passed.
 * 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
*