date:20180508

[gem5-dev] Change in gem5/gem5[master]: arch-x86, arch-power: fix calls to bits and insertBits

2018-05-08 Thread Matt Sinclair (Gerrit)

Matt Sinclair has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10241 )


Change subject: arch-x86, arch-power: fix calls to bits and insertBits
..

arch-x86, arch-power: fix calls to bits and insertBits

The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit.  This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.

Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M src/arch/power/isa/decoder.isa
M src/arch/x86/isa.cc
2 files changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 71ef95b..6bc19ad 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -158,8 +158,8 @@
 508: cmpb({{
 uint32_t val = 0;
 for (int n = 0; n < 32; n += 8) {
-if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) {
-val = insertBits(val, n, n+7, 0xff);
+if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
+val = insertBits(val, n+7, n, 0xff);
 }
 }
 Ra = val;
@@ -580,8 +580,8 @@
 for (int i = 0; i < 8; ++i) {
 if (bits(FLM, i) == 1) {
 int k = 4 * (i + (8 * (1 - W_FIELD)));
-FPSCR = insertBits(FPSCR, k, k + 3,
-   bits(Fb_uq, k, k + 3));
+FPSCR = insertBits(FPSCR, k + 3, k,
+   bits(Fb_uq, k + 3, k));
 }
 }
 }
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 28c50f3..a866b95 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -145,7 +145,7 @@
 if (miscReg == MISCREG_FSW) {
 MiscReg fsw = regVal[MISCREG_FSW];
 MiscReg top = regVal[MISCREG_X87_TOP];
-return insertBits(fsw, 11, 13, top);
+return insertBits(fsw, 13, 11, top);
 }

 return readMiscRegNoEffect(miscReg);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Gerrit-Change-Number: 10241
Gerrit-PatchSet: 4
Gerrit-Owner: Matt Sinclair 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Create block insertion function

2018-05-08 Thread Daniel Carvalho (Gerrit)

Daniel Carvalho has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9824 )


Change subject: mem-cache: Create block insertion function
..

mem-cache: Create block insertion function

Create a block insertion function to be used when inserting
blocks. This resets the number of references to 1 (the
insertion is taken into account), sets the insertion tick,
and set secure state.

Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e
Reviewed-on: https://gem5-review.googlesource.com/9824
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/blk.cc
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/tags/base.cc
4 files changed, 49 insertions(+), 19 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/blk.cc b/src/mem/cache/blk.cc
index 9475bda..233f380 100644
--- a/src/mem/cache/blk.cc
+++ b/src/mem/cache/blk.cc
@@ -43,6 +43,36 @@
 #include "base/cprintf.hh"

 void
+CacheBlk::insert(const Addr tag, const State is_secure,
+ const int src_master_ID, const uint32_t task_ID)
+{
+// Touch block
+isTouched = true;
+
+// Set block tag
+this->tag = tag;
+
+// Set source requestor ID
+srcMasterId = src_master_ID;
+
+// Set task ID
+task_id = task_ID;
+
+// Set insertion tick as current tick
+tickInserted = curTick();
+
+// Insertion counts as a reference to the block
+refCount = 1;
+
+// Set secure state
+if (is_secure) {
+status = BlkSecure;
+} else {
+status = 0;
+}
+}
+
+void
 CacheBlkPrintWrapper::print(std::ostream , int verbosity,
 const std::string ) const
 {
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index b57c61b..b634d21 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -253,6 +253,20 @@
 }

 /**
+ * Set member variables when a block insertion occurs. Resets reference
+ * count to 1 (the insertion counts as a reference), and touch block if
+ * it hadn't been touched previously. Sets the insertion tick to the
+ * current tick. Does not make block valid.
+ *
+ * @param tag Block address tag.
+ * @param is_secure Whether the block is in secure space or not.
+ * @param src_master_ID The source requestor ID.
+ * @param task_ID The new task ID.
+ */
+void insert(const Addr tag, const State is_secure, const int  
src_master_ID,

+const uint32_t task_ID);
+
+/**
  * Track the fact that a local locked was issued to the
  * block. Invalidate any previous LL to the same address.
  */
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 28c4343..2d3ab83 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -397,10 +397,7 @@
 }
 tags->insertBlock(pkt, blk);

-blk->status = (BlkValid | BlkReadable);
-if (pkt->isSecure()) {
-blk->status |= BlkSecure;
-}
+blk->status |= (BlkValid | BlkReadable);
 }
 // only mark the block dirty if we got a writeback command,
 // and leave it as is for a clean writeback
@@ -460,10 +457,7 @@
 }
 tags->insertBlock(pkt, blk);

-blk->status = (BlkValid | BlkReadable);
-if (pkt->isSecure()) {
-blk->status |= BlkSecure;
-}
+blk->status |= (BlkValid | BlkReadable);
 }
 }

diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 2f8d428..1d6ed46 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -100,26 +100,18 @@
 blk->invalidate();
 }

-// Touch block
-blk->isTouched = true;
-blk->refCount = 1;
-blk->tickInserted = curTick();
-
 // Previous block, if existed, has been removed, and now we have
 // to insert the new one
 tagsInUse++;

-// Set tag for new block.  Caller is responsible for setting status.
-blk->tag = extractTag(addr);
-
 // Deal with what we are bringing in
 MasterID master_id = pkt->req->masterId();
 assert(master_id < cache->system->maxMasters());
 occupancies[master_id]++;
-blk->srcMasterId = master_id;

-// Set task id
-blk->task_id = pkt->req->taskId();
+// Insert block with tag, src master id and task id
+blk->insert(extractTag(addr), pkt->isSecure(), master_id,
+pkt->req->taskId());

 // We only need to write into one tag and one data block.
 tagAccesses += 1;

--
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Gerrit-Branch:

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

2018-05-08 Thread Giacomo Travaglini (Gerrit)

Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10361 )


Change subject: arch-arm: Map ID_x_EL1 registers to AArch32 version
..

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 38 insertions(+), 25 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42d1b92..296f8eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -118,6 +118,18 @@
 miscRegs[MISCREG_MIDR_EL1] = p->midr;
 miscRegs[MISCREG_VPIDR] = p->midr;

+miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
 if (FullSystem && system->highestELIs64()) {
 // Initialize AArch64 state
 clear64(p);
@@ -208,18 +220,6 @@

 miscRegs[MISCREG_CPACR] = 0;

-miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
-miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
 miscRegs[MISCREG_FPSID] = p->fpsid;

 if (haveLPAE) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..08eb255 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3392,34 +3392,47 @@
 InitReg(MISCREG_REVIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_ISAR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR5);

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add E2H bit to HCR_EL2 System register

2018-05-08 Thread Giacomo Travaglini (Gerrit)


Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10381

to review the following change.


Change subject: arch-arm: Add E2H bit to HCR_EL2 System register
..

arch-arm: Add E2H bit to HCR_EL2 System register

This patch adds the EL2 Host bit to the HCR_EL2 register.  Enables a
configuration where a Host Operating System is running in EL2, and the
Host Operating System's applications are running in EL0.

Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.hh
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 06d1a0d..b43b04f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1478,6 +1478,7 @@
 EndBitUnion(HSTR)

 BitUnion64(HCR)
+Bitfield<34> e2h;   // AArch64
 Bitfield<33> id;// AArch64
 Bitfield<32> cd;// AArch64
 Bitfield<31> rw;// AArch64

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Gerrit-Change-Number: 10381
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.1 TTBR1_EL2 register

2018-05-08 Thread Giacomo Travaglini (Gerrit)


Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10382

to review the following change.


Change subject: arch-arm: Implement ARMv8.1 TTBR1_EL2 register
..

arch-arm: Implement ARMv8.1 TTBR1_EL2 register

This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for
getting the translation table base address when a Host Operating System
is running at EL2. (HCR_EL2.E2H = 1)

Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/miscregs.cc
M src/arch/arm/table_walker.cc
2 files changed, 33 insertions(+), 12 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..f3f7476 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3522,7 +3522,7 @@
   .hyp().mon()
   .mapsTo(MISCREG_HTTBR);
 InitReg(MISCREG_TTBR1_EL2)
-  .unimplemented();
+  .hyp().mon();
 InitReg(MISCREG_TCR_EL2)
   .hyp().mon()
   .mapsTo(MISCREG_HTCR);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 3c79e43..26a07d7 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -739,9 +739,9 @@
 DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
 currState->vaddr_tainted, currState->tcr);

-static const GrainSize GrainMapDefault[] =
+static const GrainSize GrainMap_tg0[] =
   { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
-static const GrainSize GrainMap_EL1_tg1[] =
+static const GrainSize GrainMap_tg1[] =
   { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };

 statWalkWaitTime.sample(curTick() - currState->startTime);
@@ -761,7 +761,7 @@
 DPRINTF(TLB, " - Selecting VTTBR0 (AArch64 stage 2)\n");
 ttbr = currState->tc->readMiscReg(MISCREG_VTTBR_EL2);
 tsz = 64 - currState->vtcr.t0sz64;
-tg = GrainMapDefault[currState->vtcr.tg0];
+tg = GrainMap_tg0[currState->vtcr.tg0];
 // ARM DDI 0487A.f D7-2148
 // The starting level of stage 2 translation depends on
 // VTCR_EL2.SL0 and VTCR_EL2.TG0
@@ -781,7 +781,7 @@
 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
 ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
 tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
-tg = GrainMapDefault[currState->tcr.tg0];
+tg = GrainMap_tg0[currState->tcr.tg0];
 if (bits(currState->vaddr, 63, tsz) != 0x0 ||
 currState->tcr.epd0)
   fault = true;
@@ -790,7 +790,7 @@
 DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
 ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
 tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
-tg = GrainMap_EL1_tg1[currState->tcr.tg1];
+tg = GrainMap_tg1[currState->tcr.tg1];
 if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
 currState->tcr.epd1)
   fault = true;
@@ -802,16 +802,37 @@
 ps = currState->tcr.ips;
 break;
   case EL2:
+switch(bits(currState->vaddr, 63,48)) {
+  case 0:
+DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
+tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
+tg = GrainMap_tg0[currState->tcr.tg0];
+break;
+
+  case 0x:
+DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
+tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
+tg = GrainMap_tg1[currState->tcr.tg1];
+if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
+currState->tcr.epd1 || !currState->hcr.e2h)
+  fault = true;
+break;
+
+   default:
+  // invalid addr if top two bytes are not all 0s
+  fault = true;
+}
+ps = currState->tcr.ips;
+break;
   case EL3:
 switch(bits(currState->vaddr, 63,48)) {
 case 0:
 DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
-if (currState->el == EL2)
-ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
-else
-ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
+ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL3);
 tsz =

[gem5-dev] Change in gem5/gem5[master]: dev: Add support for a simple debug UART

2018-05-08 Thread Andreas Sandberg (Gerrit)

Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10025 )


Change subject: dev: Add support for a simple debug UART
..

dev: Add support for a simple debug UART

Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.

This is useful to implement various debug devices that exist in many
systems.

Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg 
Reviewed-by: Jack Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/10025
Reviewed-by: Giacomo Travaglini 
---
M src/dev/serial/SConscript
M src/dev/serial/Uart.py
A src/dev/serial/simple.cc
A src/dev/serial/simple.hh
4 files changed, 180 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/dev/serial/SConscript b/src/dev/serial/SConscript
index b9f13f5..9fe5ece 100644
--- a/src/dev/serial/SConscript
+++ b/src/dev/serial/SConscript
@@ -50,6 +50,7 @@
 SimObject('Uart.py')

 Source('serial.cc')
+Source('simple.cc')
 Source('terminal.cc')
 Source('uart.cc')
 Source('uart8250.cc')
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 5333705..029d46c 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2005-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -38,6 +50,14 @@
 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 device = Param.SerialDevice(Parent.any, "The terminal")

+class SimpleUart(Uart):
+type = 'SimpleUart'
+cxx_header = "dev/serial/simple.hh"
+big_endian = Param.Bool(False, "Is the device Big Endian?")
+pio_size = Param.Addr(0x4, "Size of address range")
+end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
+"received on the UART")
+
 class Uart8250(Uart):
 type = 'Uart8250'
 cxx_header = "dev/serial/uart8250.hh"
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
new file mode 100644
index 000..aea94f9
--- /dev/null
+++ b/src/dev/serial/simple.cc
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

2018-05-08 Thread Giacomo Travaglini (Gerrit)


Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/10361

to review the following change.


Change subject: arch-arm: Map ID_x_EL1 registers to AArch32 version
..

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
2 files changed, 38 insertions(+), 25 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42d1b92..296f8eb 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -118,6 +118,18 @@
 miscRegs[MISCREG_MIDR_EL1] = p->midr;
 miscRegs[MISCREG_VPIDR] = p->midr;

+miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+
 if (FullSystem && system->highestELIs64()) {
 // Initialize AArch64 state
 clear64(p);
@@ -208,18 +220,6 @@

 miscRegs[MISCREG_CPACR] = 0;

-miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
-
-miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
 miscRegs[MISCREG_FPSID] = p->fpsid;

 if (haveLPAE) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 6615913..08eb255 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3392,34 +3392,47 @@
 InitReg(MISCREG_REVIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_ISAR0_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_ID_ISAR5);
 InitReg(MISCREG_MVFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_MVFR1_EL1)

--
To view, visit https://gem5-review.googlesource.com/10361
To

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-05-08 Thread Cron Daemon

* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!*** diff[config.json]: SKIPPED
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!*** gem5: ERROR: gem5 exited with non-zero status: 1
*** diff[simerr]: SKIPPED* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
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build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!Statistics mismatch
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: 
CHANGED!Maximum error magnitude: +10150.00%
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
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CHANGED!
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 CHANGED!*** diff[drivesys.terminal]: SKIPPED
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 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
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CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
CHANGED!scons: `build/NULL/tests/opt/quick/fs' is up to date.
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
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* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: 
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build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED!
* 
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* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
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* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED!
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* build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic:

[gem5-dev] Change in gem5/gem5[master]: arch-x86, arch-power: fix calls to bits and insertBits

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Create block insertion function

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add E2H bit to HCR_EL2 System register

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.1 TTBR1_EL2 register

[gem5-dev] Change in gem5/gem5[master]: dev: Add support for a simple debug UART

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Map ID_x_EL1 registers to AArch32 version

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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