date:20180511

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Remove isTouched field from the CacheBlk

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10427



Change subject: mem-cache: Remove isTouched field from the CacheBlk
..

mem-cache: Remove isTouched field from the CacheBlk

At the moment isTouched is used in the warm-up detection mechanism but
it keeps track of the same information as isValid(). This change
removes it and substitutes its use by isValid().

Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62
---
M src/mem/cache/blk.cc
M src/mem/cache/blk.hh
M src/mem/cache/tags/base.cc
3 files changed, 6 insertions(+), 19 deletions(-)



diff --git a/src/mem/cache/blk.cc b/src/mem/cache/blk.cc
index 233f380..ad0c20a 100644
--- a/src/mem/cache/blk.cc
+++ b/src/mem/cache/blk.cc
@@ -46,9 +46,6 @@
 CacheBlk::insert(const Addr tag, const State is_secure,
  const int src_master_ID, const uint32_t task_ID)
 {
-// Touch block
-isTouched = true;
-
 // Set block tag
 this->tag = tag;

diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index b634d21..561d502 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -109,12 +109,6 @@
  */
 int set, way;

-/**
- * Whether this block has been touched since simulation started.
- * Used to calculate number of used tags.
- */
-bool isTouched;
-
 /** Number of references to this block since it was brought in. */
 unsigned refCount;

@@ -217,7 +211,6 @@
 task_id = ContextSwitchTaskId::Unknown;
 status = 0;
 whenReady = MaxTick;
-isTouched = false;
 refCount = 0;
 srcMasterId = Request::invldMasterId;
 tickInserted = MaxTick;
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 75d117e..0087de8 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -78,14 +78,6 @@
 // Get address
 Addr addr = pkt->getAddr();

-// Update warmup data
-if (!blk->isTouched) {
-if (!warmedUp && tagsInUse.value() >= warmupBound) {
-warmedUp = true;
-warmupCycle = curTick();
-}
-}
-
 // If we're replacing a block that was previously valid update
 // stats for it. This can't be done in findBlock() because a
 // found block might not actually be replaced there if the
@@ -100,7 +92,6 @@

 // Previous block, if existed, has been removed, and now we have
 // to insert the new one
-tagsInUse++;

 // Deal with what we are bringing in
 MasterID master_id = pkt->req->masterId();
@@ -111,6 +102,12 @@
 blk->insert(extractTag(addr), pkt->isSecure(), master_id,
 pkt->req->taskId());

+tagsInUse++;
+if (!warmedUp && tagsInUse.value() >= warmupBound) {
+warmedUp = true;
+warmupCycle = curTick();
+}
+
 // We only need to write into one tag and one data block.
 tagAccesses += 1;
 dataAccesses += 1;

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62
Gerrit-Change-Number: 10427
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Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move cache bypass mechanism to the ports

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10432



Change subject: mem-cache: Move cache bypass mechanism to the ports
..

mem-cache: Move cache bypass mechanism to the ports

Cache bypass is necessary for cpu models like the KvmCPU. Previously
the bypass would happen at the cache classes. With this change the
bypassing happens directly at the ports.

Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62
---
M src/mem/cache/base.cc
M src/mem/cache/cache.cc
2 files changed, 37 insertions(+), 37 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 8929dee..a2588e2 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -637,17 +637,6 @@
 void
 BaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side)
 {
-if (system->bypassCaches()) {
-// Packets from the memory side are snoop request and
-// shouldn't happen in bypass mode.
-assert(from_cpu_side);
-
-// The cache should be flushed if we are in cache bypass mode,
-// so we don't need to check if we need to update anything.
-memSidePort->sendFunctional(pkt);
-return;
-}
-
 Addr blk_addr = pkt->getBlockAddr(blkSize);
 bool is_secure = pkt->isSecure();
 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
@@ -2153,6 +2142,11 @@
 bool
 BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
 {
+// Snoops shouldn't happen when bypassing caches
+assert(!cache->system->bypassCaches());
+
+assert(pkt->isResponse());
+
 // Express snoop responses from master to slave, e.g., from L1 to L2
 cache->recvTimingSnoopResp(pkt);
 return true;
@@ -2162,7 +2156,7 @@
 bool
 BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
 {
-if (pkt->isExpressSnoop()) {
+if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
 // always let express snoop packets through even if blocked
 return true;
 } else if (blocked || mustSendRetry) {
@@ -2177,7 +2171,15 @@
 bool
 BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
 {
-if (tryTiming(pkt)) {
+assert(pkt->isRequest());
+
+if (cache->system->bypassCaches()) {
+// Just forward the packet if caches are disabled.
+// @todo This should really enqueue the packet rather
+bool M5_VAR_USED success = cache->memSidePort->sendTimingReq(pkt);
+assert(success);
+return true;
+} else if (tryTiming(pkt)) {
 cache->recvTimingReq(pkt);
 return true;
 }
@@ -2187,12 +2189,24 @@
 Tick
 BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
 {
-return cache->recvAtomic(pkt);
+if (cache->system->bypassCaches()) {
+// Forward the request if the system is in cache bypass mode.
+return cache->memSidePort->sendAtomic(pkt);
+} else {
+return cache->recvAtomic(pkt);
+}
 }

 void
 BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
 {
+if (cache->system->bypassCaches()) {
+// The cache should be flushed if we are in cache bypass mode,
+// so we don't need to check if we need to update anything.
+cache->memSidePort->sendFunctional(pkt);
+return;
+}
+
 // functional request
 cache->functionalAccess(pkt, true);
 }
@@ -2227,6 +2241,9 @@
 void
 BaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
 {
+// Snoops shouldn't happen when bypassing caches
+assert(!cache->system->bypassCaches());
+
 // handle snooping requests
 cache->recvTimingSnoopReq(pkt);
 }
@@ -2234,12 +2251,18 @@
 Tick
 BaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
 {
+// Snoops shouldn't happen when bypassing caches
+assert(!cache->system->bypassCaches());
+
 return cache->recvAtomicSnoop(pkt);
 }

 void
 BaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
 {
+// Snoops shouldn't happen when bypassing caches
+assert(!cache->system->bypassCaches());
+
 // functional snoop (note that in contrast to atomic we don't have
 // a specific functionalSnoop method, as they have the same
 // behaviour regardless)
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 7e69bcf..7868da3 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -265,9 +265,6 @@
 {
 DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());

-assert(pkt->isResponse());
-assert(!system->bypassCaches());
-
 // determine if the response is from a snoop request we created
 // (in which case it should be in the outstandingSnoop), or if we
 // merely forwarded someone else's snoop request
@@ -403,16 +400,6 @@
 {
 DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());

-assert(pkt->isRequest());
-
-// Just forward the packet if caches are disabled.
-if (system->bypassCaches()) {
-// @todo This should really enqueue the packet rather
-bool

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add helper function to perform evictions

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10430



Change subject: mem-cache: Add helper function to perform evictions
..

mem-cache: Add helper function to perform evictions

Change-Id: I2df24eb1a8516220bec9b685c8c09bf55be18681
---
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
2 files changed, 41 insertions(+), 21 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 16846ee..3419d1e 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -303,11 +303,7 @@
 // flush and invalidate any existing block
 CacheBlk *old_blk(tags->findBlock(pkt->getAddr(),  
pkt->isSecure()));

 if (old_blk && old_blk->isValid()) {
-if (old_blk->isDirty() || writebackClean)
-writebacks.push_back(writebackBlk(old_blk));
-else
-writebacks.push_back(cleanEvictBlk(old_blk));
-invalidateBlock(old_blk);
+evictBlock(old_blk, writebacks);
 }

 blk = nullptr;
@@ -1246,9 +1242,7 @@
 schedule(writebackTempBlockAtomicEvent, curTick());
 }

-tempBlockWriteback = (blk->isDirty() || writebackClean) ?
-writebackBlk(blk) : cleanEvictBlk(blk);
-invalidateBlock(blk);
+tempBlockWriteback = evictBlock(blk);
 }

 if (pkt->needsResponse()) {
@@ -1641,10 +1635,7 @@

 // if we used temp block, check to see if its valid and then clear it  
out

 if (blk == tempBlock && tempBlock->isValid()) {
-PacketPtr wb_pkt = tempBlock->isDirty() || writebackClean ?
-writebackBlk(blk) : cleanEvictBlk(blk);
-writebacks.push_back(wb_pkt);
-invalidateBlock(tempBlock);
+evictBlock(blk, writebacks);
 }

 const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
@@ -1656,6 +1647,23 @@
 }

 PacketPtr
+Cache::evictBlock(CacheBlk *blk)
+{
+PacketPtr pkt = (blk->isDirty() || writebackClean) ?
+writebackBlk(blk) : cleanEvictBlk(blk);
+
+invalidateBlock(blk);
+
+return pkt;
+}
+
+void
+Cache::evictBlock(CacheBlk *blk, PacketList )
+{
+writebacks.push_back(evictBlock(blk));
+}
+
+PacketPtr
 Cache::writebackBlk(CacheBlk *blk)
 {
 chatty_assert(!isReadOnly || writebackClean,
@@ -1848,15 +1856,7 @@
 if (blk->wasPrefetched()) {
 unusedPrefetches++;
 }
-// Will send up Writeback/CleanEvict snoops via isCachedAbove
-// when pushing this writeback list into the write buffer.
-if (blk->isDirty() || writebackClean) {
-// Save writeback packet for handling by caller
-writebacks.push_back(writebackBlk(blk));
-} else {
-writebacks.push_back(cleanEvictBlk(blk));
-}
-invalidateBlock(blk);
+evictBlock(blk, writebacks);
 replacements++;
 }
 }
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index a90ffd5..ad67cde 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -496,6 +496,26 @@
  bool is_timing, bool is_deferred, bool  
pending_inval);


 /**
+ * Evict a cache block.
+ *
+ * Performs a writeback if necesssary and invalidates the block
+ *
+ * @param blk Block to invalidate
+ * @return A packet with the writeback, can be nullptr
+ */
+virtual PacketPtr evictBlock(CacheBlk *blk);
+
+/**
+ * Evict a cache block.
+ *
+ * Performs a writeback if necesssary and invalidates the block
+ *
+ * @param blk Block to invalidate
+ * @param writebacks Return a list of packets with writebacks
+ */
+virtual void evictBlock(CacheBlk *blk, PacketList );
+
+/**
  * Create a writeback request for the given block.
  * @param blk The block to writeback.
  * @return The writeback request for the block.

--
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Gerrit-Branch: master
Gerrit-Change-Id: I2df24eb1a8516220bec9b685c8c09bf55be18681
Gerrit-Change-Number: 10430
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Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move replacements stat to the base cache class

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10426



Change subject: mem-cache: Move replacements stat to the base cache class
..

mem-cache: Move replacements stat to the base cache class

Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
5 files changed, 9 insertions(+), 11 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 2c7d9fb..606708c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -758,4 +758,9 @@
 overallAvgMshrUncacheableLatency.subname(i,  
system->getMasterName(i));

 }

+replacements
+.name(name() + ".replacements")
+.desc("number of replacements")
+.flags(total)
+;
 }
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index b006d4b..69c4818 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -453,6 +453,9 @@
 /** The average overall latency of an MSHR miss. */
 Stats::Formula overallAvgMshrUncacheableLatency;

+/** Number of replacements of valid blocks. */
+Stats::Scalar replacements;
+
 /**
  * @}
  */
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 9ef5bfd..4426d2d 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1856,6 +1856,7 @@
 } else {
 writebacks.push_back(cleanEvictBlk(blk));
 }
+replacements++;
 }
 }

diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 1d6ed46..75d117e 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -48,7 +48,6 @@

 #include "mem/cache/tags/base.hh"

-#include "cpu/smt.hh" //maxThreadsPerCPU
 #include "mem/cache/base.hh"
 #include "sim/sim_exit.hh"

@@ -92,7 +91,6 @@
 // found block might not actually be replaced there if the
 // coherence protocol says it can't be.
 if (blk->isValid()) {
-replacements[0]++;
 totalRefs += blk->refCount;
 ++sampledRefs;

@@ -125,13 +123,6 @@

 using namespace Stats;

-replacements
-.init(maxThreadsPerCPU)
-.name(name() + ".replacements")
-.desc("number of replacements")
-.flags(total)
-;
-
 tagsInUse
 .name(name() + ".tagsinuse")
 .desc("Cycle average of tags in use")
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 4cf6774..c04329f 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -104,8 +104,6 @@
  * @{
  */

-/** Number of replacements of valid blocks per thread. */
-Stats::Vector replacements;
 /** Per cycle average of the number of tags that hold valid data. */
 Stats::Average tagsInUse;


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Gerrit-Change-Number: 10426
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix include directives in the cache related classes

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10433



Change subject: mem-cache: Fix include directives in the cache related  
classes

..

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/mshr_queue.cc
M src/mem/cache/mshr_queue.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/cache/prefetch/queued.cc
M src/mem/cache/prefetch/queued.hh
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/prefetch/tagged.cc
M src/mem/cache/prefetch/tagged.hh
M src/mem/cache/queue.hh
M src/mem/cache/queue_entry.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/cacheset.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/write_queue.cc
M src/mem/cache/write_queue.hh
M src/mem/cache/write_queue_entry.cc
M src/mem/cache/write_queue_entry.hh
42 files changed, 171 insertions(+), 42 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index a2588e2..8c33bf4 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -48,12 +48,19 @@

 #include "mem/cache/base.hh"

+#include "base/compiler.hh"
+#include "base/logging.hh"
 #include "debug/Cache.hh"
 #include "debug/CachePort.hh"
 #include "debug/CacheVerbose.hh"
-#include "debug/Drain.hh"
 #include "mem/cache/mshr.hh"
 #include "mem/cache/prefetch/base.hh"
+#include "mem/cache/queue_entry.hh"
+#include "params/BaseCache.hh"
+#include "sim/core.hh"
+
+class BaseMasterPort;
+class BaseSlavePort;

 using namespace std;

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 758f726..f6fe132 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -52,12 +52,11 @@
 #ifndef __MEM_CACHE_BASE_HH__
 #define __MEM_CACHE_BASE_HH__

-#include 
-#include 
+#include 
+#include 
 #include 
-#include 

-#include "base/logging.hh"
+#include "base/addr_range.hh"
 #include "base/statistics.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
@@ -68,16 +67,25 @@
 #include "mem/cache/mshr_queue.hh"
 #include "mem/cache/tags/base.hh"
 #include "mem/cache/write_queue.hh"
+#include "mem/cache/write_queue_entry.hh"
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
+#include "mem/packet_queue.hh"
 #include "mem/qport.hh"
 #include "mem/request.hh"
-#include "params/BaseCache.hh"
 #include "sim/eventq.hh"
-#include "sim/full_system.hh"
+#include "sim/serialize.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"

+class BaseMasterPort;
+class BasePrefetcher;
+class BaseSlavePort;
+class MSHR;
+class MasterPort;
+class QueueEntry;
+struct BaseCacheParams;
+
 /**
  * A basic cache interface. Implements some common functions for speed.
  */
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 561d502..951abd5 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -48,9 +48,14 @@
 #ifndef __MEM_CACHE_BLK_HH__
 #define __MEM_CACHE_BLK_HH__

+#include 
+#include 
+#include 
 #include 
+#include 

 #include "base/printable.hh"
+#include "base/types.hh"
 #include "mem/cache/replacement_policies/base.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 0f9f781..38c7a65 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -54,16 +54,22 @@

 #include "mem/cache/cache.hh"

+#include 
+
+#include "base/compiler.hh"
 #include "base/logging.hh"
+#include "base/trace.hh"
 #include "base/types.hh"
 #include "debug/Cache.hh"
-#include "debug/CachePort.hh"
 #include "debug/CacheTags.hh"
 #include "debug/CacheVerbose.hh"
+#include "enums/Clusivity.hh"
 #include "mem/cache/blk.hh"
 #include "mem/cache/mshr.hh"
-#include "mem/cache/prefetch/base.hh"
-#include "sim/sim_exit.hh"
+#include "mem/cache/tags/base.hh"
+#include "mem/cache/write_queue_entry.hh"
+#include "mem/request.hh"
+#include "params/Cache.hh"

 Cache::Cache(const CacheParams *p)
 : BaseCache(p, p->system->cacheLineSize()),
diff --git a/src/mem/cache/cache.hh

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the recvAtomic function

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10425



Change subject: mem-cache: Refactor the recvAtomic function
..

mem-cache: Refactor the recvAtomic function

The recvAtomic function in the cache handles atomic requests. Over
time, recvAtomic has grown in complexity and code size. This change
factors out some of its functionality in a separate functiona. The new
functions handles atomic requests that miss.

Change-Id: If77d2de1e3e802e1da37f889f68910e700c59209
---
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
2 files changed, 100 insertions(+), 76 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 79e7613..9ef5bfd 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1073,6 +1073,88 @@
 }


+Cycles
+Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+   PacketList )
+{
+// deal with the packets that go through the write path of
+// the cache, i.e. any evictions and writes
+if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean ||
+(pkt->req->isUncacheable() && pkt->isWrite())) {
+return ticksToCycles(memSidePort->sendAtomic(pkt));
+}
+
+// only misses left
+
+PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
+
+bool is_forward = (bus_pkt == nullptr);
+
+if (is_forward) {
+// just forwarding the same request to the next level
+// no local cache operation involved
+bus_pkt = pkt;
+}
+
+DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__,
+bus_pkt->print());
+
+#if TRACING_ON
+CacheBlk::State old_state = blk ? blk->status : 0;
+#endif
+
+Cycles latency = ticksToCycles(memSidePort->sendAtomic(bus_pkt));
+
+bool is_invalidate = bus_pkt->isInvalidate();
+
+// We are now dealing with the response handling
+DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__,
+bus_pkt->print(), old_state);
+
+// If packet was a forward, the response (if any) is already
+// in place in the bus_pkt == pkt structure, so we don't need
+// to do anything.  Otherwise, use the separate bus_pkt to
+// generate response to pkt and then delete it.
+if (!is_forward) {
+if (pkt->needsResponse()) {
+assert(bus_pkt->isResponse());
+if (bus_pkt->isError()) {
+pkt->makeAtomicResponse();
+pkt->copyError(bus_pkt);
+} else if (pkt->cmd == MemCmd::WriteLineReq) {
+// note the use of pkt, not bus_pkt here.
+
+// write-line request to the cache that promoted
+// the write to a whole line
+blk = handleFill(pkt, blk, writebacks,
+ allocOnFill(pkt->cmd));
+assert(blk != NULL);
+is_invalidate = false;
+satisfyRequest(pkt, blk);
+} else if (bus_pkt->isRead() ||
+   bus_pkt->cmd == MemCmd::UpgradeResp) {
+// we're updating cache state to allow us to
+// satisfy the upstream request from the cache
+blk = handleFill(bus_pkt, blk, writebacks,
+ allocOnFill(pkt->cmd));
+satisfyRequest(pkt, blk);
+maintainClusivity(pkt->fromCache(), blk);
+} else {
+// we're satisfying the upstream request without
+// modifying cache state, e.g., a write-through
+pkt->makeAtomicResponse();
+}
+}
+delete bus_pkt;
+}
+
+if (is_invalidate && blk && blk->isValid()) {
+invalidateBlock(blk);
+}
+
+return latency;
+}
+
 Tick
 Cache::recvAtomic(PacketPtr pkt)
 {
@@ -1124,84 +1206,10 @@
 // handle writebacks resulting from the access here to ensure they
 // logically proceed anything happening below
 doWritebacksAtomic(writebacks);
+assert(writebacks.empty());

 if (!satisfied) {
-// MISS
-
-// deal with the packets that go through the write path of
-// the cache, i.e. any evictions and writes
-if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean ||
-(pkt->req->isUncacheable() && pkt->isWrite())) {
-lat += ticksToCycles(memSidePort->sendAtomic(pkt));
-return lat * clockPeriod();
-}
-// only misses left
-
-PacketPtr bus_pkt = createMissPacket(pkt, blk,  
pkt->needsWritable());

-
-bool is_forward = (bus_pkt == nullptr);
-
-if (is_forward) {
-// just forwarding the same request to the next level
-// no local cache operation involved
-bus_pkt = pkt;
-}
-
-DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__,
-bus_pkt->print());
-
-#if TRACING_ON
-

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Delegate block invalidation to block allocation

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10429



Change subject: mem-cache: Delegate block invalidation to block allocation
..

mem-cache: Delegate block invalidation to block allocation

For a block replacement we first select a victim block, we invalidate
it and then populate it with the new information. Prior to this change
BaseTags::insertBlock() did the invalidation and filled in the block
with the new information. Now that the replacements stat is moved to
the BaseCache, insertBlock does not need to perform the invalidation
and as a result we can unify the block eviction code in BaseCache.

Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3
---
M src/mem/cache/cache.cc
M src/mem/cache/tags/base.cc
2 files changed, 3 insertions(+), 8 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 4426d2d..16846ee 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1856,6 +1856,7 @@
 } else {
 writebacks.push_back(cleanEvictBlk(blk));
 }
+invalidateBlock(blk);
 replacements++;
 }
 }
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 2685c08..7d0a939 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -75,17 +75,11 @@
 void
 BaseTags::insertBlock(PacketPtr pkt, CacheBlk *blk)
 {
+assert(!blk->isValid());
+
 // Get address
 Addr addr = pkt->getAddr();

-// If we're replacing a block that was previously valid update
-// stats for it. This can't be done in findBlock() because a
-// found block might not actually be replaced there if the
-// coherence protocol says it can't be.
-if (blk->isValid()) {
-invalidate(blk);
-}
-
 // Previous block, if existed, has been removed, and now we have
 // to insert the new one


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Gerrit-Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3
Gerrit-Change-Number: 10429
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingReq function

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10424



Change subject: mem-cache: Refactor the cache recvTimingReq function
..

mem-cache: Refactor the cache recvTimingReq function

The recvTimingReq function in the cache handles timing requests. Over
time, recvTimingReq has grown in complexity and code size. This change
factors out some of its functionality in two separate functions. The
new functions handle timing requests that hit and timing requests that
miss separately.

Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418
---
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
2 files changed, 247 insertions(+), 210 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index c0d4401..79e7613 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -643,6 +643,231 @@
 }

 void
+Cache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
+{
+// should never be satisfying an uncacheable access as we
+// flush and invalidate any existing block as part of the
+// lookup
+assert(!pkt->req->isUncacheable());
+
+// track time of availability of next prefetch, if any
+Tick next_pf_time = MaxTick;
+
+// hit (for all other request types)
+
+if (prefetcher && (prefetchOnAccess ||
+   (blk && blk->wasPrefetched( {
+if (blk)
+blk->status &= ~BlkHWPrefetched;
+
+// Don't notify on SWPrefetch
+if (!pkt->cmd.isSWPrefetch()) {
+assert(!pkt->req->isCacheMaintenance());
+next_pf_time = prefetcher->notify(pkt);
+}
+}
+
+if (pkt->needsResponse()) {
+pkt->makeTimingResponse();
+// @todo: Make someone pay for this
+pkt->headerDelay = pkt->payloadDelay = 0;
+
+// In this case we are considering request_time that takes
+// into account the delay of the xbar, if any, and just
+// lat, neglecting responseLatency, modelling hit latency
+// just as lookupLatency or or the value of lat overriden
+// by access(), that calls accessBlock() function.
+cpuSidePort->schedTimingResp(pkt, request_time, true);
+} else {
+DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
+pkt->print());
+
+// queue the packet for deletion, as the sending cache is
+// still relying on it; if the block is found in access(),
+// CleanEvict and Writeback messages will be deleted
+// here as well
+pendingDelete.reset(pkt);
+}
+
+if (next_pf_time != MaxTick)
+schedMemSideSendEvent(next_pf_time);
+}
+
+void
+Cache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time,
+   Tick request_time)
+{
+Addr blk_addr = pkt->getBlockAddr(blkSize);
+
+// ignore any existing MSHR if we are dealing with an
+// uncacheable request
+MSHR *mshr = pkt->req->isUncacheable() ? nullptr :
+mshrQueue.findMatch(blk_addr, pkt->isSecure());
+
+// Software prefetch handling:
+// To keep the core from waiting on data it won't look at
+// anyway, send back a response with dummy data. Miss handling
+// will continue asynchronously. Unfortunately, the core will
+// insist upon freeing original Packet/Request, so we have to
+// create a new pair with a different lifecycle. Note that this
+// processing happens before any MSHR munging on the behalf of
+// this request because this new Request will be the one stored
+// into the MSHRs, not the original.
+if (pkt->cmd.isSWPrefetch()) {
+assert(pkt->needsResponse());
+assert(pkt->req->hasPaddr());
+assert(!pkt->req->isUncacheable());
+
+// There's no reason to add a prefetch as an additional target
+// to an existing MSHR. If an outstanding request is already
+// in progress, there is nothing for the prefetch to do.
+// If this is the case, we don't even create a request at all.
+PacketPtr pf = nullptr;
+
+if (!mshr) {
+// copy the request and create a new SoftPFReq packet
+RequestPtr req = new Request(pkt->req->getPaddr(),
+ pkt->req->getSize(),
+ pkt->req->getFlags(),
+ pkt->req->masterId());
+pf = new Packet(req, pkt->cmd);
+pf->allocate();
+assert(pf->getAddr() == pkt->getAddr());
+assert(pf->getSize() == pkt->getSize());
+}
+
+pkt->makeTimingResponse();
+
+// request_time is used here, taking into account lat and the delay
+// charged if the packet comes from the xbar.
+cpuSidePort->schedTimingResp(pkt, request_time, true);
+
+// If an outstanding request is in progress (we

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Determine if an MSHR has requests from another cache

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10422



Change subject: mem-cache: Determine if an MSHR has requests from another  
cache

..

mem-cache: Determine if an MSHR has requests from another cache

To decide whether we allocate upon receiving a response we need to
determine if any of the currently serviced requests (non-deferred
targets) is comming from another cache. This change adds support for
tracking this information in the MSHR.

Change-Id: If1db93c12b6af5813b91b9d6b6e5e196d327f038
---
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
2 files changed, 29 insertions(+), 5 deletions(-)



diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index cc26b56..14ac342 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -68,7 +68,8 @@
 }

 MSHR::TargetList::TargetList()
-: needsWritable(false), hasUpgrade(false), allocOnFill(false)
+: needsWritable(false), hasUpgrade(false), allocOnFill(false),
+  hasFromCache(false)
 {}


@@ -91,6 +92,8 @@
 // potentially re-evaluate whether we should allocate on a fill or
 // not
 allocOnFill = allocOnFill || alloc_on_fill;
+
+hasFromCache = hasFromCache || pkt->fromCache();
 }
 }

@@ -590,7 +593,7 @@
 void
 MSHR::print(std::ostream , int verbosity, const std::string )  
const

 {
-ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
+ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
  prefix, blkAddr, blkAddr + blkSize - 1,
  isSecure ? "s" : "ns",
  isForward ? "Forward" : "",
@@ -600,7 +603,8 @@
  inService ? "InSvc" : "",
  downstreamPending ? "DwnPend" : "",
  postInvalidate ? "PostInv" : "",
- postDowngrade ? "PostDowngr" : "");
+ postDowngrade ? "PostDowngr" : "",
+ hasFromCache() ? "HasFromCache" : "");

 if (!targets.empty()) {
 ccprintf(os, "%s  Targets:\n", prefix);
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 5fe0fb9..2894482 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -162,6 +162,11 @@
 bool hasUpgrade;
 /** Set when the response should allocate on fill */
 bool allocOnFill;
+/**
+ * Determine whether there was at least one non-snooping
+ * target coming from another cache.
+ */
+bool hasFromCache;

 TargetList();

@@ -176,7 +181,12 @@
 void updateFlags(PacketPtr pkt, Target::Source source,
  bool alloc_on_fill);

-void resetFlags() { needsWritable = hasUpgrade = allocOnFill =  
false; }

+void resetFlags() {
+needsWritable = false;
+hasUpgrade = false;
+allocOnFill = false;
+hasFromCache = false;
+}

 /**
  * Goes through the list of targets and uses them to populate
@@ -191,7 +201,8 @@
  * values.
  */
 bool isReset() const {
-return !needsWritable && !hasUpgrade && !allocOnFill;
+return !needsWritable && !hasUpgrade && !allocOnFill &&
+!hasFromCache;
 }

 /**
@@ -257,6 +268,15 @@
 bool allocOnFill() const {
 return targets.allocOnFill;
 }
+
+/**
+ * Determine if there are non-deferred requests from other caches
+ *
+ * @return true if any of the targets is from another cache
+ */
+bool hasFromCache() const {
+return targets.hasFromCache;
+}
   private:

 /**

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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingResp function

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10423



Change subject: mem-cache: Refactor the cache recvTimingResp function
..

mem-cache: Refactor the cache recvTimingResp function

The recvTimingResp function in the cache handles timing
responses. Over time, recvTimingResp has grown in complexity and code
size. This change factors out some of its functionality to a separate
function. The new function iterates through the in-service targets and
handles them accordingly.

Change-Id: I0ef28288640f6be1b30452b0664d32432e692ea6
---
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
2 files changed, 115 insertions(+), 96 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index b9625be..c0d4401 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1322,100 +1322,20 @@
 }

 void
-Cache::recvTimingResp(PacketPtr pkt)
+Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
+  PacketList )
 {
-assert(pkt->isResponse());
-
-// all header delay should be paid for by the crossbar, unless
-// this is a prefetch response from above
-panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
- "%s saw a non-zero packet delay\n", name());
-
-bool is_error = pkt->isError();
-
-if (is_error) {
-DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
-pkt->print());
-}
-
-DPRINTF(Cache, "%s: Handling response %s\n", __func__,
-pkt->print());
-
-// if this is a write, we should be looking at an uncacheable
-// write
-if (pkt->isWrite()) {
-assert(pkt->req->isUncacheable());
-handleUncacheableWriteResp(pkt);
-return;
-}
-
-// we have dealt with any (uncacheable) writes above, from here on
-// we know we are dealing with an MSHR due to a miss or a prefetch
-MSHR *mshr = dynamic_cast(pkt->popSenderState());
-assert(mshr);
-
-if (mshr == noTargetMSHR) {
-// we always clear at least one target
-clearBlocked(Blocked_NoTargets);
-noTargetMSHR = nullptr;
-}
-
-// Initial target is used just for stats
 MSHR::Target *initial_tgt = mshr->getTarget();
-int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
-Tick miss_latency = curTick() - initial_tgt->recvTime;
+// First offset for critical word first calculations
+int initial_offset = initial_tgt->pkt->getOffset(blkSize);

-if (pkt->req->isUncacheable()) {
-assert(pkt->req->masterId() < system->maxMasters());
-mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
-miss_latency;
-} else {
-assert(pkt->req->masterId() < system->maxMasters());
-mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
-miss_latency;
-}
-
-bool wasFull = mshrQueue.isFull();
-
-PacketList writebacks;
-
-Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
-
+const bool is_error = pkt->isError();
 bool is_fill = !mshr->isForward &&
 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
-
-CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
-const bool valid_blk = blk && blk->isValid();
-// If the response indicates that there are no sharers and we
-// either had the block already or the response is filling we can
-// promote our copy to writable
-if (!pkt->hasSharers() &&
-(is_fill || (valid_blk && !pkt->req->isCacheInvalidate( {
-mshr->promoteWritable();
-}
-
-if (is_fill && !is_error) {
-DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
-pkt->getAddr());
-
-blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill());
-assert(blk != nullptr);
-}
-
 // allow invalidation responses originating from write-line
 // requests to be discarded
 bool is_invalidate = pkt->isInvalidate();

-// The block was marked as not readable while there was a pending
-// cache maintenance operation, restore its flag.
-if (pkt->isClean() && !is_invalidate && valid_blk) {
-blk->status |= BlkReadable;
-}
-
-// First offset for critical word first calculations
-int initial_offset = initial_tgt->pkt->getOffset(blkSize);
-
-bool from_cache = false;
 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
 for (auto : targets) {
 Packet *tgt_pkt = target.pkt;
@@ -1437,10 +1357,6 @@
 break; // skip response
 }

-// keep track of whether we have responded to another
-// cache
-from_cache = from_cache || tgt_pkt->fromCache();
-
 // unlike the other packet flows, where data is found in other
 // caches or memory and brought back, write-line

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add a non-coherent cache

2018-05-11 Thread Nikos Nikoleris (Gerrit)


Hello Gabe Black, Daniel Carvalho, Jason Lowe-Power,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8291

to look at the new patch set (#6).

Change subject: mem-cache: Add a non-coherent cache
..

mem-cache: Add a non-coherent cache

The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.

This is a modified version of a changeset put together by Andreas
Hansson 

Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
---
M configs/example/memtest.py
M src/mem/cache/Cache.py
M src/mem/cache/SConscript
M src/mem/cache/cache.cc
A src/mem/cache/noncoherent_cache.cc
A src/mem/cache/noncoherent_cache.hh
M src/mem/cache/queue.hh
M tests/configs/base_config.py
8 files changed, 514 insertions(+), 13 deletions(-)


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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Gerrit-Change-Number: 8291
Gerrit-PatchSet: 6
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move reference count stats update to blk invalidation

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10428



Change subject: mem-cache: Move reference count stats update to blk  
invalidation

..

mem-cache: Move reference count stats update to blk invalidation

The tags in the cache keep track of the number of references to the
blocks as well as the average number of references between an
inssertion and the next invalidation. Previously the stats where
updated only on block insertion and invalidations were ignored. This
changes moves the update of the counters to the block invalidation
function.

Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612
---
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
2 files changed, 5 insertions(+), 4 deletions(-)



diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 0087de8..2685c08 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -83,11 +83,7 @@
 // found block might not actually be replaced there if the
 // coherence protocol says it can't be.
 if (blk->isValid()) {
-totalRefs += blk->refCount;
-++sampledRefs;
-
 invalidate(blk);
-blk->invalidate();
 }

 // Previous block, if existed, has been removed, and now we have
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index c04329f..31fbfc0 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -247,8 +247,13 @@
 {
 assert(blk);
 assert(blk->isValid());
+
 tagsInUse--;
 occupancies[blk->srcMasterId]--;
+totalRefs += blk->refCount;
+sampledRefs++;
+
+blk->invalidate();
 }

 /**

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612
Gerrit-Change-Number: 10428
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Simplify writeback for the tempBlock in recvTimingResp

2018-05-11 Thread Nikos Nikoleris (Gerrit)

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/10421



Change subject: mem-cache: Simplify writeback for the tempBlock in  
recvTimingResp

..

mem-cache: Simplify writeback for the tempBlock in recvTimingResp

When we use the tempBlock to fill-in, we have to write it back and
invalidate it at the end of current transaction. This patch simplifies
the writeback flow by treating it as a regular writeback.

Change-Id: I257be7bbff211e2832ad001a4e991daf67704485
---
M src/mem/cache/cache.cc
1 file changed, 7 insertions(+), 23 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 2d3ab83..b9625be 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1611,33 +1611,17 @@
 // reset the xbar additional timinig  as it is now accounted for
 pkt->headerDelay = pkt->payloadDelay = 0;

-// copy writebacks to write buffer
-doWritebacks(writebacks, forward_time);
-
 // if we used temp block, check to see if its valid and then clear it  
out

 if (blk == tempBlock && tempBlock->isValid()) {
-// We use forwardLatency here because we are copying
-// Writebacks/CleanEvicts to write buffer. It specifies the  
latency to

-// allocate an internal buffer and to schedule an event to the
-// queued port.
-if (blk->isDirty() || writebackClean) {
-PacketPtr wbPkt = writebackBlk(blk);
-allocateWriteBuffer(wbPkt, forward_time);
-// Set BLOCK_CACHED flag if cached above.
-if (isCachedAbove(wbPkt))
-wbPkt->setBlockCached();
-} else {
-PacketPtr wcPkt = cleanEvictBlk(blk);
-// Check to see if block is cached above. If not allocate
-// write buffer
-if (isCachedAbove(wcPkt))
-delete wcPkt;
-else
-allocateWriteBuffer(wcPkt, forward_time);
-}
-invalidateBlock(blk);
+PacketPtr wb_pkt = tempBlock->isDirty() || writebackClean ?
+writebackBlk(blk) : cleanEvictBlk(blk);
+writebacks.push_back(wb_pkt);
+invalidateBlock(tempBlock);
 }

+// copy writebacks to write buffer
+doWritebacks(writebacks, forward_time);
+
 DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
 delete pkt;
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I257be7bbff211e2832ad001a4e991daf67704485
Gerrit-Change-Number: 10421
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2018-05-11 Thread Cron Daemon

* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!*** diff[config.ini]: SKIPPED
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: 
CHANGED!*** diff[config.ini]: SKIPPED* 
build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.* 
build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
*** diff[simout]: SKIPPED* 
build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!*** diff[config.ini]: SKIPPED
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 CHANGED!
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 CHANGED!
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 CHANGED!
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!*** stat_diff: FAILURE: Statistics mismatch
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: 
CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: 
CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple:
 CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: CHANGED!
* build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: CHANGED!
* build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic: CHANGED!
*** stat_diff: FAILURE: Statistics mismatch* 
build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing: CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing: CHANGED!
* 
build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker: 
CHANGED!*** diff[simout]: SKIPPED
* 
build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: 
CHANGED!
*

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Remove isTouched field from the CacheBlk

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move cache bypass mechanism to the ports

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add helper function to perform evictions

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move replacements stat to the base cache class

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix include directives in the cache related classes

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the recvAtomic function

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Delegate block invalidation to block allocation

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingReq function

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Determine if an MSHR has requests from another cache

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingResp function

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add a non-coherent cache

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move reference count stats update to blk invalidation

[gem5-dev] Change in gem5/gem5[master]: mem-cache: Simplify writeback for the tempBlock in recvTimingResp

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

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