[gem5-dev] Change in gem5/gem5[master]: gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry
Anthony Gutierrez has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10481 )
Change subject: gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry
..
gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry
GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It
wrapped the class and included an extra member "valid". This member was
intended to report on the validity of the entry, however it introduced
bugs when folks forgot to set field properly in the code. So, instead of
keeping the extra field which we might forget to set, we track validity by
using nullptr for invalid tlb entries (as the tlb entries are dynamically
allocated). This saves on the extra class definition and prevents bugs
creeping into the code since the checks are intrinsically tied into
accessing any of the X86ISA::TlbEntry members.
This changeset fixes the issues introduced by a8d030522, a4e722725, and
2a15bfd79.
Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2
Reviewed-on: https://gem5-review.googlesource.com/10481
Reviewed-by: Brandon Potter
Maintainer: Anthony Gutierrez
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/tlb_coalescer.cc
4 files changed, 55 insertions(+), 59 deletions(-)
Approvals:
Brandon Potter: Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index a46e965..aa4f0a3 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1083,7 +1083,7 @@
safe_cast(pkt->senderState);
// no PageFaults are permitted for data accesses
-if (!translation_state->tlbEntry->valid) {
+if (!translation_state->tlbEntry) {
DTLBPort::SenderState *sender_state =
safe_cast(translation_state->saved);
@@ -1095,8 +1095,6 @@
pkt->req->getVaddr());
}
-assert(translation_state->tlbEntry->valid);
-
// update the hitLevel distribution
int hit_level = translation_state->hitLevel;
computeUnit->hitsPerTLBLevel[hit_level]++;
@@ -1329,7 +1327,7 @@
TheISA::GpuTLB::TranslationState *translation_state =
safe_cast(pkt->senderState);
-bool success = translation_state->tlbEntry->valid;
+bool success = translation_state->tlbEntry != nullptr;
delete translation_state->tlbEntry;
assert(!translation_state->ports.size());
pkt->senderState = translation_state->saved;
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index 5691f35..8b9bd43 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -73,7 +73,7 @@
accessDistance = p->accessDistance;
clock = p->clk_domain->clockPeriod();
-tlb.assign(size, GpuTlbEntry());
+tlb.assign(size, TlbEntry());
freeList.resize(numSets);
entryList.resize(numSets);
@@ -166,10 +166,10 @@
}
}
-GpuTlbEntry*
-GpuTLB::insert(Addr vpn, GpuTlbEntry )
+TlbEntry*
+GpuTLB::insert(Addr vpn, TlbEntry )
{
-GpuTlbEntry *newEntry = nullptr;
+TlbEntry *newEntry = nullptr;
/**
* vpn holds the virtual page address
@@ -222,7 +222,7 @@
return entry;
}
-GpuTlbEntry*
+TlbEntry*
GpuTLB::lookup(Addr va, bool update_lru)
{
int set = (va >> TheISA::PageShift) & setMask;
@@ -242,7 +242,7 @@
for (int i = 0; i < numSets; ++i) {
while (!entryList[i].empty()) {
-GpuTlbEntry *entry = entryList[i].front();
+TlbEntry *entry = entryList[i].front();
entryList[i].pop_front();
freeList[i].push_back(entry);
}
@@ -684,7 +684,7 @@
if (m5Reg.paging) {
DPRINTF(GPUTLB, "Paging enabled.\n");
//update LRU stack on a hit
-GpuTlbEntry *entry = lookup(vaddr, true);
+TlbEntry *entry = lookup(vaddr, true);
if (entry)
tlb_hit = true;
@@ -792,7 +792,7 @@
if (m5Reg.paging) {
DPRINTF(GPUTLB, "Paging enabled.\n");
// The vaddr already has the segment base applied.
-GpuTlbEntry *entry = lookup(vaddr);
+TlbEntry *entry = lookup(vaddr);
localNumTLBAccesses++;
if (!entry) {
@@ -830,9 +830,8 @@
DPRINTF(GPUTLB, "Mapping %#x to %#x\n",
alignedVaddr, pte->paddr);
-GpuTlbEntry gpuEntry(
-p->pTable->pid(), alignedVaddr,
-pte->paddr, true);
+TlbEntry gpuEntry(p->pid(), alignedVaddr,
+
[gem5-dev] Change in gem5/gem5[master]: dev: Exit correctly in dist-gem5 for SE mode
Anthony Gutierrez has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10461 )
Change subject: dev: Exit correctly in dist-gem5 for SE mode
..
dev: Exit correctly in dist-gem5 for SE mode
Do not allow the exit() syscall to terminate gem5 when running in dist-gem5
mode. The exit must be coordinated by the distributed interface instead.
Change-Id: I57f47610b59fe9e18ba3a1667fb5e45cecac1a81
Reviewed-on: https://gem5-review.googlesource.com/10461
Maintainer: Jason Lowe-Power
Reviewed-by: Mohammad Alian
Reviewed-by: Jason Lowe-Power
---
M src/sim/syscall_emul.cc
1 file changed, 15 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Mohammad Alian: Looks good to me, but someone else must approve
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 8736176..7f4d766 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -43,6 +43,7 @@
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
+#include "dev/net/dist_iface.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/sim_exit.hh"
@@ -102,6 +103,20 @@
for (auto : sys->systemList)
activeContexts += system->numRunningContexts();
if (activeContexts == 1) {
+/**
+ * Even though we are terminating the final thread context,
dist-gem5
+ * requires the simulation to remain active and provide
+ * synchronization messages to the switch process. So we just halt
+ * the last thread context and return. The simulation will be
+ * terminated by dist-gem5 in a coordinated manner once all nodes
+ * have signaled their readiness to exit. For non dist-gem5
+ * simulations, readyToExit() always returns true.
+ */
+if (!DistIface::readyToExit(0)) {
+tc->halt();
+return status;
+}
+
exitSimLoop("exiting with last active thread context", status &
0xff);
return status;
}
--
To view, visit https://gem5-review.googlesource.com/10461
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I57f47610b59fe9e18ba3a1667fb5e45cecac1a81
Gerrit-Change-Number: 10461
Gerrit-PatchSet: 4
Gerrit-Owner: Anthony Gutierrez
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabor Dozsa
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Mohammad Alian
Gerrit-CC: Michael LeBeane
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Use block visitor to update tags stats and print tags
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/10621
to review the following change.
Change subject: mem-cache: Use block visitor to update tags stats and print
tags
..
mem-cache: Use block visitor to update tags stats and print tags
This change uses the block visitor to perform stat updates and print
tags as uneccesary and moves the corresponding functions to the
BaseTags class. This also implements the print, computeStats and
cleanupRefs for the FALRU class.
Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03
Reviewed-by: Andreas Sandberg
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/blk.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.hh
8 files changed, 148 insertions(+), 111 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index c50fcdb..2254303 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1326,14 +1326,16 @@
void
BaseCache::memWriteback()
{
-CacheBlkVisitorWrapper visitor(*this, ::writebackVisitor);
+CacheBlkVisitorWrapper visitor(
+*this, ::writebackVisitor);
tags->forEachBlk(visitor);
}
void
BaseCache::memInvalidate()
{
-CacheBlkVisitorWrapper visitor(*this, ::invalidateVisitor);
+CacheBlkVisitorWrapper visitor(
+*this, ::invalidateVisitor);
tags->forEachBlk(visitor);
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index aacf09a..3c318d9 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1153,31 +1153,6 @@
};
/**
- * Wrap a method and present it as a cache block visitor.
- *
- * For example the forEachBlk method in the tag arrays expects a
- * callable object/function as their parameter. This class wraps a
- * method in an object and presents callable object that adheres to
- * the cache block visitor protocol.
- */
-class CacheBlkVisitorWrapper : public CacheBlkVisitor
-{
- public:
-typedef bool (BaseCache::*VisitorPtr)(CacheBlk );
-
-CacheBlkVisitorWrapper(BaseCache &_cache, VisitorPtr _visitor)
-: cache(_cache), visitor(_visitor) {}
-
-bool operator()(CacheBlk ) override {
-return (cache.*visitor)(blk);
-}
-
- private:
-BaseCache
-VisitorPtr visitor;
-};
-
-/**
* Cache block visitor that determines if there are dirty blocks in a
* cache.
*
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 951abd5..efb70d4 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2017 ARM Limited
+ * Copyright (c) 2012-2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -425,4 +425,52 @@
virtual bool operator()(CacheBlk ) = 0;
};
+/**
+ * Wrap a method and present it as a cache block visitor.
+ *
+ * For example the forEachBlk method in the tag arrays expects a
+ * callable object/function as their parameter. This class wraps a
+ * method in an object and presents callable object that adheres to
+ * the cache block visitor protocol.
+ */
+template
+class CacheBlkVisitorWrapper : public CacheBlkVisitor
+{
+ public:
+typedef bool (Object::*VisitorPtr)(CacheBlk );
+
+CacheBlkVisitorWrapper(Object &_object, VisitorPtr _visitor)
+: object(_object), visitor(_visitor) {}
+
+bool operator()(CacheBlk ) override {
+return (object.*visitor)(blk);
+}
+
+ private:
+Object
+VisitorPtr visitor;
+};
+
+/**
+ * Wrap a tags print method and present it as a cache block visitor.
+ *
+ * For example the forEachBlk method in the tag arrays expects a
+ * callable object/function as their parameter. This class wraps a
+ * method in an object and presents a callable object that adheres to
+ * the cache block visitor protocol.
+ */
+class CacheBlkPrintVisitor : public CacheBlkVisitor
+{
+ public:
+bool operator()(CacheBlk ) override {
+if (blk.isValid())
+str += csprintf("\tset: %d way: %d %s\n", blk.set, blk.way,
+blk.print());
+return true;
+}
+
+std::string str;
+};
+
+
#endif //__MEM_CACHE_BLK_HH__
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index c7ea17b..8ed4278 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013,2016 ARM Limited
+ * Copyright (c) 2013,2016,2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -110,6 +110,79 @@
dataAccesses += 1;
}
+bool
+BaseTags::cleanupRefsVisitor(CacheBlk )
+{
+if (blk.isValid()) {
+totalRefs += blk.refCount;
+++sampledRefs;
+}
+
+return true;
+}
+
+void
+BaseTags::cleanupRefs()
+{
+
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/10602
to review the following change.
Change subject: arch-arm: Read APSR in User Mode
..
arch-arm: Read APSR in User Mode
This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.
Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini
Reviewed-by: Andreas Sandberg
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/miscregs.hh
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index f1c6acf..ef579bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -226,7 +226,7 @@
cpsr.c = CondCodesC;
cpsr.v = CondCodesV;
cpsr.ge = CondCodesGE;
-Dest = cpsr & 0xF8FF03DF
+Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
'''
mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b00e5ff..f9386b4 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1423,6 +1423,17 @@
static const uint32_t CondCodesMask = 0xF00F;
static const uint32_t CpsrMaskQ = 0x0800;
+// APSR (Application Program Status Register Mask). It is the user
level
+// alias for the CPSR. The APSR is a subset of the CPSR. Although
+// bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
+// APSR:
+// Bit[9] returns the value of CPSR.E.
+// Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
+static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask |
0x01D0;
+
+// CPSR (Current Program Status Register Mask).
+static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
+
BitUnion32(HDCR)
Bitfield<11> tdra;
Bitfield<10> tdosa;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Gerrit-Change-Number: 10602
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: python: Include hasattr helper for SimObjects
Hello Andreas Sandberg, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/10601 to review the following change. Change subject: python: Include hasattr helper for SimObjects .. python: Include hasattr helper for SimObjects With this patch it will be possibile to query a SimObject from configuration file to check if it has a parameter. Change-Id: Ie5eb6efe5595f9a8a44df49e6e149428c6c3464d Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg --- M src/python/m5/SimObject.py 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 6e61961..0bcc900 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -1,4 +1,4 @@ -# Copyright (c) 2017 ARM Limited +# Copyright (c) 2017-2018 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -660,6 +660,16 @@ raise AttributeError, \ "object '%s' has no attribute '%s'" % (cls.__name__, attr) +# Check for attribute (called to see if foo has attribute attr when +# foo is an instance of class cls) +def hasattr(cls, attr): +try: +__getattr__(cls, attr) +except AttributeError: +return False +else: +return True + def __str__(cls): return cls.__name__ -- To view, visit https://gem5-review.googlesource.com/10601 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie5eb6efe5595f9a8a44df49e6e149428c6c3464d Gerrit-Change-Number: 10601 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add a non-coherent cache
Hello Gabe Black, Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/8291 to look at the new patch set (#10). Change subject: mem-cache: Add a non-coherent cache .. mem-cache: Add a non-coherent cache The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a --- M configs/example/memtest.py M src/mem/cache/Cache.py M src/mem/cache/SConscript M src/mem/cache/mshr.cc A src/mem/cache/noncoherent_cache.cc A src/mem/cache/noncoherent_cache.hh M src/mem/cache/queue.hh M tests/configs/base_config.py 8 files changed, 556 insertions(+), 17 deletions(-) -- To view, visit https://gem5-review.googlesource.com/8291 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Gerrit-Change-Number: 8291 Gerrit-PatchSet: 10 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Adopt a more sensible cache class hierarchy
Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10431 to look at the new patch set (#5). Change subject: mem-cache: Adopt a more sensible cache class hierarchy .. mem-cache: Adopt a more sensible cache class hierarchy This patch changes what goes into the BaseCache and what goes into the Cache, to make it easier to add a NoncoherentCache with as much re-use as possible. A number of redundant members and definitions are also removed in the process. This is a modified version of a changeset put together by Andreas Hansson Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b --- M src/mem/cache/Cache.py M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/cache.cc M src/mem/cache/cache.hh M src/mem/cache/mshr.cc M src/mem/cache/mshr.hh M src/mem/cache/queue_entry.hh M src/mem/cache/write_queue_entry.cc M src/mem/cache/write_queue_entry.hh 10 files changed, 2,292 insertions(+), 2,157 deletions(-) -- To view, visit https://gem5-review.googlesource.com/10431 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b Gerrit-Change-Number: 10431 Gerrit-PatchSet: 5 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingReq function
Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10424 to look at the new patch set (#4). Change subject: mem-cache: Refactor the cache recvTimingReq function .. mem-cache: Refactor the cache recvTimingReq function The recvTimingReq function in the cache handles timing requests. Over time, recvTimingReq has grown in complexity and code size. This change factors out some of its functionality in two separate functions. The new functions handle timing requests that hit and timing requests that miss separately. Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418 --- M src/mem/cache/cache.cc M src/mem/cache/cache.hh 2 files changed, 223 insertions(+), 192 deletions(-) -- To view, visit https://gem5-review.googlesource.com/10424 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418 Gerrit-Change-Number: 10424 Gerrit-PatchSet: 4 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Refactor the cache recvTimingResp function
Hello Daniel Carvalho, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/10423 to look at the new patch set (#4). Change subject: mem-cache: Refactor the cache recvTimingResp function .. mem-cache: Refactor the cache recvTimingResp function The recvTimingResp function in the cache handles timing responses. Over time, recvTimingResp has grown in complexity and code size. This change factors out some of its functionality to a separate function. The new function iterates through the in-service targets and handles them accordingly. Change-Id: I0ef28288640f6be1b30452b0664d32432e692ea6 --- M src/mem/cache/cache.cc M src/mem/cache/cache.hh 2 files changed, 113 insertions(+), 89 deletions(-) -- To view, visit https://gem5-review.googlesource.com/10423 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0ef28288640f6be1b30452b0664d32432e692ea6 Gerrit-Change-Number: 10423 Gerrit-PatchSet: 4 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Determine if an MSHR has requests from another cache
Nikos Nikoleris has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10422 )
Change subject: mem-cache: Determine if an MSHR has requests from another
cache
..
mem-cache: Determine if an MSHR has requests from another cache
To decide whether we allocate upon receiving a response we need to
determine if any of the currently serviced requests (non-deferred
targets) is comming from another cache. This change adds support for
tracking this information in the MSHR.
Change-Id: If1db93c12b6af5813b91b9d6b6e5e196d327f038
Reviewed-on: https://gem5-review.googlesource.com/10422
Reviewed-by: Jason Lowe-Power
Maintainer: Nikos Nikoleris
---
M src/mem/cache/cache.cc
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
3 files changed, 33 insertions(+), 11 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 73c7e19..e9aec49 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1415,7 +1415,6 @@
// First offset for critical word first calculations
int initial_offset = initial_tgt->pkt->getOffset(blkSize);
-bool from_cache = false;
MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
for (auto : targets) {
Packet *tgt_pkt = target.pkt;
@@ -1437,10 +1436,6 @@
break; // skip response
}
-// keep track of whether we have responded to another
-// cache
-from_cache = from_cache || tgt_pkt->fromCache();
-
// unlike the other packet flows, where data is found in other
// caches or memory and brought back, write-line requests
always
// have the data right away, so the above check for "is fill?"
@@ -1572,7 +1567,7 @@
}
}
-maintainClusivity(from_cache, blk);
+maintainClusivity(targets.hasFromCache, blk);
if (blk && blk->isValid()) {
// an invalidate response stemming from a write line request
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index cc26b56..4f170e6 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -68,7 +68,8 @@
}
MSHR::TargetList::TargetList()
-: needsWritable(false), hasUpgrade(false), allocOnFill(false)
+: needsWritable(false), hasUpgrade(false), allocOnFill(false),
+ hasFromCache(false)
{}
@@ -91,6 +92,10 @@
// potentially re-evaluate whether we should allocate on a fill or
// not
allocOnFill = allocOnFill || alloc_on_fill;
+
+if (source != Target::FromPrefetcher) {
+hasFromCache = hasFromCache || pkt->fromCache();
+}
}
}
@@ -590,7 +595,7 @@
void
MSHR::print(std::ostream , int verbosity, const std::string )
const
{
-ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
+ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s %s\n",
prefix, blkAddr, blkAddr + blkSize - 1,
isSecure ? "s" : "ns",
isForward ? "Forward" : "",
@@ -600,7 +605,8 @@
inService ? "InSvc" : "",
downstreamPending ? "DwnPend" : "",
postInvalidate ? "PostInv" : "",
- postDowngrade ? "PostDowngr" : "");
+ postDowngrade ? "PostDowngr" : "",
+ hasFromCache() ? "HasFromCache" : "");
if (!targets.empty()) {
ccprintf(os, "%s Targets:\n", prefix);
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 5fe0fb9..b4bf33a 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -162,6 +162,11 @@
bool hasUpgrade;
/** Set when the response should allocate on fill */
bool allocOnFill;
+/**
+ * Determine whether there was at least one non-snooping
+ * target coming from another cache.
+ */
+bool hasFromCache;
TargetList();
@@ -176,7 +181,12 @@
void updateFlags(PacketPtr pkt, Target::Source source,
bool alloc_on_fill);
-void resetFlags() { needsWritable = hasUpgrade = allocOnFill =
false; }
+void resetFlags() {
+needsWritable = false;
+hasUpgrade = false;
+allocOnFill = false;
+hasFromCache = false;
+}
/**
* Goes through the list of targets and uses them to populate
@@ -191,7 +201,8 @@
* values.
*/
bool isReset() const {
-return !needsWritable && !hasUpgrade && !allocOnFill;
+return !needsWritable && !hasUpgrade && !allocOnFill &&
+!hasFromCache;
}
/**
@@ -257,6 +268,16 @@
bool allocOnFill() const {
return targets.allocOnFill;
}
+
+/**
+ * Determine if there are non-deferred requests from other caches
+
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! *** diff[config.ini]: SKIPPED* build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: CHANGED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: CHANGED! * build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: CHANGED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: CHANGED! *
