[gem5-dev] Change in gem5/gem5[master]: tests: add cpu tests to the new testing infrastructure
Ayaz Akram has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15857 ) Change subject: tests: add cpu tests to the new testing infrastructure .. tests: add cpu tests to the new testing infrastructure Change-Id: I42996ddc802ef279ab4970afc37cb0df25c04b08 Signed-off-by: Ayaz Akram Reviewed-on: https://gem5-review.googlesource.com/c/15857 Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg --- A tests/gem5/cpu_tests/ref/Bubblesort A tests/gem5/cpu_tests/ref/FloatMM A tests/gem5/cpu_tests/run.py A tests/gem5/cpu_tests/test.py 4 files changed, 249 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Andreas Sandberg: Looks good to me, approved; Looks good to me, approved diff --git a/tests/gem5/cpu_tests/ref/Bubblesort b/tests/gem5/cpu_tests/ref/Bubblesort new file mode 100644 index 000..79d2ae3 --- /dev/null +++ b/tests/gem5/cpu_tests/ref/Bubblesort @@ -0,0 +1,6 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1 ticks per second +-5 diff --git a/tests/gem5/cpu_tests/ref/FloatMM b/tests/gem5/cpu_tests/ref/FloatMM new file mode 100644 index 000..6539627 --- /dev/null +++ b/tests/gem5/cpu_tests/ref/FloatMM @@ -0,0 +1,6 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + + +Global frequency set at 1 ticks per second +-776.61 diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py new file mode 100644 index 000..c1cdd3f --- /dev/null +++ b/tests/gem5/cpu_tests/run.py @@ -0,0 +1,174 @@ +# -*- coding: utf-8 -*- +# Copyright (c) 2018 The Regents of the University of California +# All Rights Reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Lowe-Power + +import os +import argparse + +import m5 +from m5.objects import * + +class L1Cache(Cache): +"""Simple L1 Cache with default values""" + +assoc = 8 +tag_latency = 1 +data_latency = 1 +response_latency = 1 +mshrs = 16 +tgts_per_mshr = 20 + +def connectBus(self, bus): +"""Connect this cache to a memory-side bus""" +self.mem_side = bus.slave + +def connectCPU(self, cpu): +"""Connect this cache's port to a CPU-side port + This must be defined in a subclass""" +raise NotImplementedError + +class L1ICache(L1Cache): +"""Simple L1 instruction cache with default values""" + +# Set the default size +size = '32kB' + +def connectCPU(self, cpu): +"""Connect this cache's port to a CPU icache port""" +self.cpu_side = cpu.icache_port + +class L1DCache(L1Cache): +"""Simple L1 data cache with default values""" + +# Set the default size +size = '32kB' + +def connectCPU(self, cpu): +"""Connect this cache's port to a CPU dcache port""" +self.cpu_side = cpu.dcache_port + +class L2Cache(Cache): +"""Simple L2 Cache with default values""" + +# Default parameters +size = '512kB' +assoc = 16 +tag_latency = 10 +data_latency = 10 +response_latency = 1 +mshrs = 20 +tgts_per_mshr = 12 + +def connectCPUSideBus(self, bus): +self.cpu_side = bus.master + +def connectMemSideBus(self, bus): +self.mem_side = bus.slave + + +class
[gem5-dev] Change in gem5/gem5[master]: sim-se: update the arm kernel version
Ayaz Akram has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15855 ) Change subject: sim-se: update the arm kernel version .. sim-se: update the arm kernel version This change is needed to run cpu tests with ARM binaries compiled with newer linux kernel headers Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625 Signed-off-by: Ayaz Akram Reviewed-on: https://gem5-review.googlesource.com/c/15855 Reviewed-by: Brandon Potter Reviewed-by: Andreas Sandberg Maintainer: Brandon Potter Maintainer: Andreas Sandberg --- M src/arch/arm/linux/process.cc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Brandon Potter: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index a7ec70e..99f4b2c 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -89,7 +89,7 @@ strcpy(name->sysname, "Linux"); strcpy(name->nodename, "gem5"); -strcpy(name->release, "3.7.0+"); +strcpy(name->release, "4.10.8+"); strcpy(name->version, "#1 SMP Sat Dec 1 00:00:00 GMT 2012"); strcpy(name->machine, "armv8l"); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15855 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625 Gerrit-Change-Number: 15855 Gerrit-PatchSet: 6 Gerrit-Owner: Ayaz Akram Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ayaz Akram Gerrit-Reviewer: Brandon Potter Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Move test programs paths to related test scripts
Ayaz Akram has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15856 )
Change subject: tests: Move test programs paths to related test scripts
..
tests: Move test programs paths to related test scripts
This change is needed to make sure that the DownloadedProgram fixture
does not fail, in case the test binaries are not stored in test-progs/
(e.g. in the case of cpu tests)
Change-Id: Icf96f2537b038502e78da560c7ccebc44984b509
Signed-off-by: Ayaz Akram
Reviewed-on: https://gem5-review.googlesource.com/c/15856
Reviewed-by: Andreas Sandberg
Reviewed-by: Rutuja Govind Oza
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M tests/gem5/fixture.py
M tests/gem5/hello_se/test_hello_se.py
M tests/gem5/m5_util/test_exit.py
3 files changed, 4 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
Rutuja Govind Oza: Looks good to me, approved
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index a50d73c..df834ef 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -220,11 +220,9 @@
super(DownloadedProgram, self).__init__("download-" + program,
build_once=True, **kwargs)
-self.program_dir = joinpath('test-progs', path)
+self.program_dir = path
self.path = joinpath(self.program_dir, program)
-
self.url = self.urlbase + self.path
-
def _download(self):
import urllib
log.test_log.debug("Downloading " + self.url + " to " + self.path)
diff --git a/tests/gem5/hello_se/test_hello_se.py
b/tests/gem5/hello_se/test_hello_se.py
index 0310064..5017962 100644
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -39,7 +39,7 @@
for isa in test_progs:
for binary in test_progs[isa]:
import os
-path = os.path.join('hello', 'bin', isa, 'linux')
+path = os.path.join('test-progs', 'hello', 'bin', isa, 'linux')
hello_program = DownloadedProgram(path, binary)
ref_path = joinpath(getcwd(), 'ref')
diff --git a/tests/gem5/m5_util/test_exit.py
b/tests/gem5/m5_util/test_exit.py
index f5292b1..a766db4 100644
--- a/tests/gem5/m5_util/test_exit.py
+++ b/tests/gem5/m5_util/test_exit.py
@@ -37,7 +37,8 @@
r'Exiting @ tick \d* because m5_exit instruction encountered'
)
-test_program = DownloadedProgram('m5-exit/bin/x86/linux/', 'm5_exit')
+test_program = DownloadedProgram('test-progs/m5-exit/bin/x86/linux/',\
+'m5_exit')
a = verifier.MatchRegex(m5_exit_regex)
gem5_verify_config(
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15856
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icf96f2537b038502e78da560c7ccebc44984b509
Gerrit-Change-Number: 15856
Gerrit-PatchSet: 4
Gerrit-Owner: Ayaz Akram
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Rutuja Govind Oza
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: tests: Convert memtest to new framework
Ayaz Akram has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15836 )
Change subject: tests: Convert memtest to new framework
..
tests: Convert memtest to new framework
The original memtest is located at:
https://gem5.googlesource.com/public/gem5/+/master/tests/configs/memtest.py
Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/15836
Reviewed-by: Nikos Nikoleris
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
A tests/gem5/memory/memtest-run.py
M tests/gem5/memory/simple-run.py
M tests/gem5/memory/test.py
3 files changed, 100 insertions(+), 11 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/tests/gem5/memory/memtest-run.py
b/tests/gem5/memory/memtest-run.py
new file mode 100644
index 000..c454160
--- /dev/null
+++ b/tests/gem5/memory/memtest-run.py
@@ -0,0 +1,85 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../../../configs/')
+from common.Caches import *
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [MemTest(max_loads = 1e5, progress_interval = 1e4)
+for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus,
+physmem = SimpleMemory(),
+membus = SystemXBar())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
system.voltage_domain)
+
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+# All cpus are associated with cpu_clk_domain
+cpu.clk_domain = system.cpu_clk_domain
+cpu.l1c = L1Cache(size = '32kB', assoc = 4)
+cpu.l1c.cpu_side = cpu.port
+cpu.l1c.mem_side = system.toL2Bus.slave
+
+system.system_port = system.membus.slave
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# ---
+# run simulation
+# ---
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+
+m5.instantiate()
+exit_event = m5.simulate()
+if exit_event.getCause() != "maximum number of loads reached":
+exit(1)
+
diff --git a/tests/gem5/memory/simple-run.py
b/tests/gem5/memory/simple-run.py
index b77c23c..28ddce6 100644
--- a/tests/gem5/memory/simple-run.py
+++ b/tests/gem5/memory/simple-run.py
@@ -47,17 +47,14 @@
args = parser.parse_args()
-# both traffic generator and communication monitor are only available
-# if we have protobuf support, so potentially skip this test
-# require_sim_object("TrafficGen")
-# require_sim_object("CommMonitor")
-# This needs to be fixed in the new
[gem5-dev] Change in gem5/gem5[master]: tests: Convert tgen-simple-memory to new framework
Ayaz Akram has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15835 )
Change subject: tests: Convert tgen-simple-memory to new framework
..
tests: Convert tgen-simple-memory to new framework
The original test is located at:
https://gem5.googlesource.com/public/gem5/+/master/tests/configs/tgen-simple-mem.py
Change-Id: I13a58cfb3d01d08ef7c818fc00fb56ba126eb4b6
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/15835
Reviewed-by: Rutuja Govind Oza
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
A tests/gem5/memory/simple-run.py
A tests/gem5/memory/test.py
A tests/gem5/memory/tgen-simple-mem.cfg
A tests/gem5/memory/tgen-simple-mem.trc
4 files changed, 200 insertions(+), 0 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Rutuja Govind Oza: Looks good to me, approved
diff --git a/tests/gem5/memory/simple-run.py
b/tests/gem5/memory/simple-run.py
new file mode 100644
index 000..b77c23c
--- /dev/null
+++ b/tests/gem5/memory/simple-run.py
@@ -0,0 +1,103 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+import m5
+from m5.objects import *
+
+import argparse
+
+parser = argparse.ArgumentParser(description='Simple memory tester')
+parser.add_argument('--bandwidth', default=None)
+parser.add_argument('--latency', default=None)
+parser.add_argument('--latency_var', default=None)
+
+args = parser.parse_args()
+
+# both traffic generator and communication monitor are only available
+# if we have protobuf support, so potentially skip this test
+# require_sim_object("TrafficGen")
+# require_sim_object("CommMonitor")
+# This needs to be fixed in the new infrastructure
+
+# even if this is only a traffic generator, call it cpu to make sure
+# the scripts are happy
+cpu = TrafficGen(
+config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
+ "tgen-simple-mem.cfg"))
+
+class MyMem(SimpleMemory):
+if args.bandwidth:
+bandwidth = args.bandwidth
+if args.latency:
+latency = args.latency
+if args.latency_var:
+latency_var = args.latency_var
+
+# system simulated
+system = System(cpu = cpu, physmem = MyMem(),
+membus = IOXBar(width = 16),
+clk_domain = SrcClockDomain(clock = '1GHz',
+voltage_domain =
+VoltageDomain()))
+
+# add a communication monitor, and also trace all the packets and
+# calculate and verify stack distance
+system.monitor = CommMonitor()
+system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
+system.monitor.stackdist = StackDistProbe(verify = True)
+
+# connect the traffic generator to the bus via a communication
[gem5-dev] Change in gem5/gem5[master]: cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
Hello Javier Bueno Hedo, Sudhanshu Jha, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14855 to look at the new patch set (#16). Change subject: cpu: Added 8KB and 64KB TAGE-SC-L branch predictor .. cpu: Added 8KB and 64KB TAGE-SC-L branch predictor The original paper of the branch predictor can be found here: http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf Change-Id: I684863752407685adaacedebb699205c3559c528 --- M src/cpu/pred/BranchPredictor.py M src/cpu/pred/SConscript M src/cpu/pred/loop_predictor.cc M src/cpu/pred/loop_predictor.hh M src/cpu/pred/ltage.cc M src/cpu/pred/ltage.hh A src/cpu/pred/statistical_corrector.cc A src/cpu/pred/statistical_corrector.hh M src/cpu/pred/tage.cc M src/cpu/pred/tage.hh M src/cpu/pred/tage_base.cc M src/cpu/pred/tage_base.hh A src/cpu/pred/tage_sc_l.cc A src/cpu/pred/tage_sc_l.hh A src/cpu/pred/tage_sc_l_64KB.cc A src/cpu/pred/tage_sc_l_64KB.hh A src/cpu/pred/tage_sc_l_8KB.cc A src/cpu/pred/tage_sc_l_8KB.hh 18 files changed, 2,541 insertions(+), 56 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14855 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I684863752407685adaacedebb699205c3559c528 Gerrit-Change-Number: 14855 Gerrit-PatchSet: 16 Gerrit-Owner: Pau Cabre Gerrit-Assignee: Ilias Vougioukas Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Pau Cabre Gerrit-Reviewer: Sudhanshu Jha Gerrit-CC: Ilias Vougioukas Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Sandbox Based Optimal Offset Implementation
Hello Nikos Nikoleris, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15095 to look at the new patch set (#4). Change subject: mem-cache: Sandbox Based Optimal Offset Implementation .. mem-cache: Sandbox Based Optimal Offset Implementation Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation. Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/sbooe.cc A src/mem/cache/prefetch/sbooe.hh 4 files changed, 281 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15095 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862 Gerrit-Change-Number: 15095 Gerrit-PatchSet: 4 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: move members of Process to MemState
Brandon Potter has uploaded a new patch set (#6). ( https://gem5-review.googlesource.com/c/public/gem5/+/12306 ) Change subject: sim-se: move members of Process to MemState .. sim-se: move members of Process to MemState This changeset moves memory-related functionality from the Process class to the MemState class. The goal is to create an object to manage the memory for Syscall Emulation Mode; ideally, that object has as much cohesion as possible. Change-Id: I5e6afecbd47e9c46998c4d6a1091d1f4fb698a71 --- M src/arch/alpha/faults.cc M src/arch/alpha/process.cc M src/arch/alpha/process.hh M src/arch/arm/linux/process.cc M src/arch/arm/process.cc M src/arch/arm/remote_gdb.cc M src/arch/arm/tlb.cc M src/arch/generic/tlb.cc M src/arch/mips/process.cc M src/arch/mips/remote_gdb.cc M src/arch/mips/tlb.cc M src/arch/power/process.cc M src/arch/power/remote_gdb.cc M src/arch/power/tlb.cc M src/arch/riscv/process.cc M src/arch/riscv/process.hh M src/arch/riscv/remote_gdb.cc M src/arch/riscv/tlb.cc M src/arch/sparc/faults.cc M src/arch/sparc/process.cc M src/arch/sparc/process.hh M src/arch/sparc/remote_gdb.cc M src/arch/x86/process.cc M src/arch/x86/process.hh M src/arch/x86/remote_gdb.cc M src/arch/x86/tlb.cc M src/cpu/thread_context.hh M src/gpu-compute/compute_unit.cc M src/gpu-compute/gpu_tlb.cc M src/gpu-compute/shader.cc M src/mem/se_translating_port_proxy.cc M src/mem/se_translating_port_proxy.hh M src/sim/SConscript M src/sim/faults.cc A src/sim/mem_state.cc M src/sim/mem_state.hh R src/sim/mem_state_impl.hh M src/sim/process.cc M src/sim/process.hh M src/sim/syscall_emul.hh 40 files changed, 893 insertions(+), 385 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12306 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5e6afecbd47e9c46998c4d6a1091d1f4fb698a71 Gerrit-Change-Number: 12306 Gerrit-PatchSet: 6 Gerrit-Owner: Brandon Potter Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: change syscall function signature
Hello Jason Lowe-Power, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12299 to look at the new patch set (#6). Change subject: sim-se: change syscall function signature .. sim-se: change syscall function signature The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c --- M src/arch/alpha/linux/process.cc M src/arch/arm/freebsd/process.cc M src/arch/arm/linux/process.cc M src/arch/mips/linux/process.cc M src/arch/power/linux/process.cc M src/arch/riscv/linux/process.cc M src/arch/sparc/linux/syscalls.cc M src/arch/sparc/solaris/process.cc M src/arch/x86/linux/process.cc M src/gpu-compute/cl_driver.cc M src/gpu-compute/cl_driver.hh M src/sim/emul_driver.hh M src/sim/process.cc M src/sim/syscall_desc.cc M src/sim/syscall_desc.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh 17 files changed, 372 insertions(+), 383 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12299 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Gerrit-Change-Number: 12299 Gerrit-PatchSet: 6 Gerrit-Owner: Brandon Potter Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: generate /proc/self/maps file
Hello Alexandru Duțu, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12311 to look at the new patch set (#6). Change subject: sim-se: generate /proc/self/maps file .. sim-se: generate /proc/self/maps file This change generates /proc/self/maps for the currently running process. It assummes a system with one process and one thread per process. This is needed by the OpenCL runtime, as it calls pthread_getattr_np. Change-Id: Iee0f35842ef5571f6b0717194bc746a585a945e6 --- M configs/common/FileSystemConfig.py M src/arch/alpha/process.cc M src/arch/x86/linux/process.cc M src/arch/x86/process.cc M src/kern/linux/linux.cc M src/kern/linux/linux.hh M src/mem/vma.hh M src/sim/mem_state.cc M src/sim/mem_state.hh M src/sim/syscall_emul.hh 10 files changed, 90 insertions(+), 22 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12311 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iee0f35842ef5571f6b0717194bc746a585a945e6 Gerrit-Change-Number: 12311 Gerrit-PatchSet: 6 Gerrit-Owner: Brandon Potter Gerrit-Reviewer: Alexandru Duțu Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: remove mem proxy in ThreadContext
Brandon Potter has uploaded a new patch set (#6). ( https://gem5-review.googlesource.com/c/public/gem5/+/12305 ) Change subject: sim-se: remove mem proxy in ThreadContext .. sim-se: remove mem proxy in ThreadContext Many parts of the source code use a memory proxy reference to access the simulated memory space in Syscall Emulation Mode. However, it would be nice if all memory responsibilities were delegated to a single object rather than spread across many objects. This patch helps to consolidate the memory responsibilities inside the MemState class by removing the ThreadContext's memory proxy. Change-Id: Ic1a6c3017c412a24db91770396d0a9bde790421d --- M src/arch/alpha/linux/process.cc M src/arch/arm/freebsd/process.cc M src/arch/arm/linux/process.cc M src/arch/mips/linux/process.cc M src/arch/power/linux/process.cc M src/arch/riscv/linux/process.cc M src/arch/sparc/linux/syscalls.cc M src/arch/sparc/process.cc M src/arch/sparc/solaris/process.cc M src/arch/x86/linux/process.cc M src/arch/x86/pseudo_inst.cc M src/base/remote_gdb.cc M src/cpu/checker/thread_context.hh M src/cpu/o3/thread_context.hh M src/cpu/thread_context.hh M src/cpu/thread_state.cc M src/cpu/thread_state.hh M src/gpu-compute/cl_driver.cc M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh 20 files changed, 399 insertions(+), 259 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12305 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic1a6c3017c412a24db91770396d0a9bde790421d Gerrit-Change-Number: 12305 Gerrit-PatchSet: 6 Gerrit-Owner: Brandon Potter Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: support lazy physical page allocs
Brandon Potter has uploaded a new patch set (#6). ( https://gem5-review.googlesource.com/c/public/gem5/+/12307 ) Change subject: sim-se: support lazy physical page allocs .. sim-se: support lazy physical page allocs This patch introduces Virtual Memory Areas (VMAs) to the Process class. Instead of binding virtual pages to physical pages during mmap/remap, we instead create a VMA that covers the region. Physical pages are allocated only if the virtual page is actually touched by the program. The binding occurs in fixupStackFault, renamed to fixupFault. Delaying the binding allows SE mode to support sparse usages of mmap. Change-Id: I2caa0f3c9622d810474ea1b1ad717820b2de9437 --- M src/base/addr_range.hh A src/base/mapped_buf.hh M src/mem/SConscript A src/mem/vma.cc A src/mem/vma.hh M src/sim/mem_state.cc M src/sim/mem_state.hh M src/sim/process.cc M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh 10 files changed, 494 insertions(+), 167 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12307 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I2caa0f3c9622d810474ea1b1ad717820b2de9437 Gerrit-Change-Number: 12307 Gerrit-PatchSet: 6 Gerrit-Owner: Brandon Potter Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: add a pseudo-filesystem
Brandon Potter has uploaded a new patch set (#7). ( https://gem5-review.googlesource.com/c/public/gem5/+/12119 ) Change subject: sim-se: add a pseudo-filesystem .. sim-se: add a pseudo-filesystem This change introduce the concept of a pseudo-filesystem in gem5. The pseudo-filesystm works by creating a directory structure in m5out (or whichever output dir the user specifies) that system calls may be redirected to. This is useful for cases where SE mode would introduce some non-determinism due to reading files with varying path names (e.g., variation from run to run if your gem5 job is scheduled on a cluster where paths may change). It is also useful for opening files that have information specific to the host CPU, such as cache hierarchy or CPU information. This is useful when running runtimes in SE mode in the absence of a real OS kernel since many runtime layers provide system-level services to user space applications. Change-Id: I90821b3b403168b904a662fa98b85def1628621c --- A configs/common/FileSystemConfig.py M configs/common/Options.py M configs/example/se.py M src/kern/linux/linux.cc A src/sim/RedirectPath.py M src/sim/SConscript M src/sim/System.py M src/sim/process.cc M src/sim/process.hh A src/sim/redirect_path.cc A src/sim/redirect_path.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh M src/sim/system.cc M src/sim/system.hh 15 files changed, 593 insertions(+), 96 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12119 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I90821b3b403168b904a662fa98b85def1628621c Gerrit-Change-Number: 12119 Gerrit-PatchSet: 7 Gerrit-Owner: Brandon Potter Gerrit-CC: Andreas Sandberg Gerrit-CC: Giacomo Travaglini Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Replace deprecated repr syntax
Hello Gabe Black, Jason Lowe-Power, Juha Jäykkä, Giacomo Travaglini, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15989 to look at the new patch set (#6). Change subject: python: Replace deprecated repr syntax .. python: Replace deprecated repr syntax Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54 Signed-off-by: Andreas Sandberg --- M src/python/m5/util/grammar.py M src/python/m5/util/multidict.py M src/python/m5/util/sorteddict.py 3 files changed, 4 insertions(+), 4 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15989 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54 Gerrit-Change-Number: 15989 Gerrit-PatchSet: 6 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Juha Jäykkä Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Replace dict.has_key with 'key in dict'
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15987 )
Change subject: python: Replace dict.has_key with 'key in dict'
..
python: Replace dict.has_key with 'key in dict'
Python 3 has removed dict.has_key in favour of 'key in dict'.
Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/15987
Reviewed-by: Giacomo Travaglini
---
M src/SConscript
M src/arch/isa_parser.py
M src/arch/x86/isa/macroop.isa
M src/mem/slicc/ast/PeekStatementAST.py
M src/mem/slicc/symbols/StateMachine.py
M src/python/m5/SimObject.py
M src/python/m5/params.py
M src/python/m5/util/multidict.py
M src/unittest/genini.py
9 files changed, 26 insertions(+), 26 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/SConscript b/src/SConscript
index dcb08a3..81b6cd3 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1338,7 +1338,7 @@
ext = t.split('.')[-1]
if ext in target_types:
return ext
-if obj2target.has_key(ext):
+if ext in obj2target:
return obj2target[ext]
match = re.search(r'/tests/([^/]+)/', t)
if match and match.group(1) in target_types:
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 16004c0..48bc23f 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -142,7 +142,7 @@
del myDict['snippets']
snippetLabels = [l for l in labelRE.findall(template)
- if d.snippets.has_key(l)]
+ if l in d.snippets]
snippets = dict([(s, self.parser.mungeSnippet(d.snippets[s]))
for s in snippetLabels])
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 33e559c..7d72961 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -333,7 +333,7 @@
noModRMString = "env.setSeg(machInst);\n"
def genMacroop(Name, env):
blocks = OutputBlocks()
-if not macroopDict.has_key(Name):
+if not Name in macroopDict:
raise Exception, "Unrecognized instruction: %s" % Name
macroop = macroopDict[Name]
if not macroop.declared:
diff --git a/src/mem/slicc/ast/PeekStatementAST.py
b/src/mem/slicc/ast/PeekStatementAST.py
index 00d26e9..6cadb31 100644
--- a/src/mem/slicc/ast/PeekStatementAST.py
+++ b/src/mem/slicc/ast/PeekStatementAST.py
@@ -71,7 +71,7 @@
}
''')
-if self.pairs.has_key("block_on"):
+if "block_on" in self.pairs:
address_field = self.pairs['block_on']
code('''
if (m_is_blocking &&
@@ -82,7 +82,7 @@
}
''')
-if self.pairs.has_key("wake_up"):
+if "wake_up" in self.pairs:
address_field = self.pairs['wake_up']
code('''
if (m_waiting_buffers.count(in_msg_ptr->m_$address_field) > 0) {
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 330cc03..03e624b 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -239,7 +239,7 @@
if param.rvalue is not None:
dflt_str = str(param.rvalue.inline()) + ', '
-if python_class_map.has_key(param.type_ast.type.c_ident):
+if param.type_ast.type.c_ident in python_class_map:
python_type = python_class_map[param.type_ast.type.c_ident]
code('${{param.ident}} =
Param.${{python_type}}(${dflt_str}"")')
@@ -1109,7 +1109,7 @@
for port in self.in_ports:
code.indent()
code('// ${ident}InPort $port')
-if port.pairs.has_key("rank"):
+if "rank" in port.pairs:
code('m_cur_in_port = ${{port.pairs["rank"]}};')
else:
code('m_cur_in_port = 0;')
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 97cf6d0..f553fd6 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -534,7 +534,7 @@
cls._new_port(key, val)
# init-time-only keywords
-elif cls.init_keywords.has_key(key):
+elif key in cls.init_keywords:
cls._set_keyword(key, val, cls.init_keywords[key])
# default: use normal path (ends up in __setattr__)
@@ -613,11 +613,11 @@
type.__setattr__(cls, attr, value)
return
-if cls.keywords.has_key(attr):
+if attr in cls.keywords:
cls._set_keyword(attr, value, cls.keywords[attr])
return
-if cls._ports.has_key(attr):
+if attr in cls._ports:
cls._cls_get_port_ref(attr).connect(value)
return
@@ -652,10
[gem5-dev] Change in gem5/gem5[master]: python: Add missing defines import
Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16402 ) Change subject: python: Add missing defines import .. python: Add missing defines import The _check_tracing helper function in main.py depends on defines to check if tracing has been enabled at compile time. This module is imported in main() but not at the module level, which breaks this function. Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/16402 Reviewed-by: Giacomo Travaglini --- M src/python/m5/main.py 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved Andreas Sandberg: Looks good to me, approved diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 8a259f3..08b1464 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -193,6 +193,8 @@ def _check_tracing(): +import defines + if defines.TRACING_ON: return -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16402 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Gerrit-Change-Number: 16402 Gerrit-PatchSet: 2 Gerrit-Owner: Andreas Sandberg Gerrit-Assignee: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Replace dict.has_key with 'key in dict'
Hello Jason Lowe-Power, Juha Jäykkä, Giacomo Travaglini, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15987 to look at the new patch set (#6). Change subject: python: Replace dict.has_key with 'key in dict' .. python: Replace dict.has_key with 'key in dict' Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg --- M src/SConscript M src/arch/isa_parser.py M src/arch/x86/isa/macroop.isa M src/mem/slicc/ast/PeekStatementAST.py M src/mem/slicc/symbols/StateMachine.py M src/python/m5/SimObject.py M src/python/m5/params.py M src/python/m5/util/multidict.py M src/unittest/genini.py 9 files changed, 26 insertions(+), 26 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15987 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Gerrit-Change-Number: 15987 Gerrit-PatchSet: 6 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Juha Jäykkä Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Add missing defines import
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16402 Change subject: python: Add missing defines import .. python: Add missing defines import The _check_tracing helper function in main.py depends on defines to check if tracing has been enabled at compile time. This module is imported in main() but not at the module level, which breaks this function. Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Signed-off-by: Andreas Sandberg --- M src/python/m5/main.py 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 8a259f3..08b1464 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -193,6 +193,8 @@ def _check_tracing(): +import defines + if defines.TRACING_ON: return -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16402 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Gerrit-Change-Number: 16402 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Replace DictMixin with Mapping / MutableMapping
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15984 )
Change subject: python: Replace DictMixin with Mapping / MutableMapping
..
python: Replace DictMixin with Mapping / MutableMapping
Python 3 has removed support for DictMixin, so switch to Mapping /
MutableMapping in collections which provides the same functionality.
Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/15984
Reviewed-by: Jason Lowe-Power
---
M src/python/m5/debug.py
1 file changed, 10 insertions(+), 14 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index f7e34a7..d2892f7 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -28,7 +28,7 @@
from __future__ import print_function
-from UserDict import DictMixin
+from collections import Mapping
import _m5.debug
from _m5.debug import SimpleFlag, CompoundFlag
@@ -56,7 +56,7 @@
printList([ c.name() for c in children ], indent=8)
print()
-class AllFlags(DictMixin):
+class AllFlags(Mapping):
def __init__(self):
self._version = -1
self._dict = {}
@@ -79,6 +79,14 @@
self._update()
return self._dict[item]
+def __iter__(self):
+self._update()
+return iter(self._dict)
+
+def __len__(self):
+self._update()
+return len(self._dict)
+
def keys(self):
self._update()
return self._dict.keys()
@@ -91,16 +99,4 @@
self._update()
return self._dict.items()
-def iterkeys(self):
-self._update()
-return self._dict.iterkeys()
-
-def itervalues(self):
-self._update()
-return self._dict.itervalues()
-
-def iteritems(self):
-self._update()
-return self._dict.iteritems()
-
flags = AllFlags()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32
Gerrit-Change-Number: 15984
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sandberg
Gerrit-Assignee: Jason Lowe-Power
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: python: Replace orderdict with collections.OrderedDict
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16362 )
Change subject: python: Replace orderdict with collections.OrderedDict
..
python: Replace orderdict with collections.OrderedDict
Python 2.7 and newer has support for ordered dictionaries in the
standard library. Remove this custom class.
Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/16362
Reviewed-by: Giacomo Travaglini
Reviewed-by: Jason Lowe-Power
---
M src/mem/slicc/symbols/StateMachine.py
M src/mem/slicc/symbols/Type.py
M src/python/SConscript
M src/python/m5/util/__init__.py
D src/python/m5/util/orderdict.py
M util/stats/profile.py
6 files changed, 9 insertions(+), 85 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index cbcc792..330cc03 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -26,7 +26,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from m5.util import orderdict
+from collections import OrderedDict
from slicc.symbols.Symbol import Symbol
from slicc.symbols.Var import Var
@@ -78,10 +78,10 @@
if str(param.type_ast.type) == "Prefetcher":
self.prefetchers.append(var)
-self.states = orderdict()
-self.events = orderdict()
-self.actions = orderdict()
-self.request_types = orderdict()
+self.states = OrderedDict()
+self.events = OrderedDict()
+self.actions = OrderedDict()
+self.request_types = OrderedDict()
self.transitions = []
self.in_ports = []
self.functions = []
@@ -1303,7 +1303,7 @@
''')
# This map will allow suppress generating duplicate code
-cases = orderdict()
+cases = OrderedDict()
for trans in self.transitions:
case_string = "%s_State_%s, %s_Event_%s" % \
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 37c0b16..162c1ab 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -25,7 +25,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from m5.util import orderdict
+from collections import OrderedDict
from slicc.util import PairContainer
from slicc.symbols.Symbol import Symbol
@@ -89,9 +89,9 @@
self.isStateDecl = ("state_decl" in self)
self.statePermPairs = []
-self.data_members = orderdict()
+self.data_members = OrderedDict()
self.methods = {}
-self.enums = orderdict()
+self.enums = OrderedDict()
@property
def isPrimitive(self):
diff --git a/src/python/SConscript b/src/python/SConscript
index 19fb386..36e0d5b 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -55,7 +55,6 @@
PySource('m5.util', 'm5/util/grammar.py')
PySource('m5.util', 'm5/util/jobfile.py')
PySource('m5.util', 'm5/util/multidict.py')
-PySource('m5.util', 'm5/util/orderdict.py')
PySource('m5.util', 'm5/util/smartdict.py')
PySource('m5.util', 'm5/util/sorteddict.py')
PySource('m5.util', 'm5/util/terminal.py')
diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index 02dece6..341e54f 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -51,7 +51,6 @@
from attrdict import attrdict, multiattrdict, optiondict
from code_formatter import code_formatter
from multidict import multidict
-from orderdict import orderdict
from smartdict import SmartDict
from sorteddict import SortedDict
diff --git a/src/python/m5/util/orderdict.py
b/src/python/m5/util/orderdict.py
deleted file mode 100644
index 1ffbca8..000
--- a/src/python/m5/util/orderdict.py
+++ /dev/null
@@ -1,73 +0,0 @@
-# Copyright (c) 2005 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this
[gem5-dev] Change in gem5/gem5[master]: python: Update use of exec to work with Python 3
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15986 )
Change subject: python: Update use of exec to work with Python 3
..
python: Update use of exec to work with Python 3
Python 3 uses 'exec(code, globals)' instead of 'exec code in
globals'. Switch to the newer syntax since it is supported by Python
2.7. Also, move check_tracing out of main to work around a bug in
Python 2.7.
Change-Id: I6d390160f58783e1b038a572b64cdf3ff09535fa
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/15986
Reviewed-by: Jason Lowe-Power
---
M src/python/importer.py
M src/python/m5/internal/params.py
M src/python/m5/main.py
M src/python/m5/objects/__init__.py
M src/python/m5/util/jobfile.py
5 files changed, 18 insertions(+), 17 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/python/importer.py b/src/python/importer.py
index c54fb49..224ab3b 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -77,7 +77,7 @@
mod.__package__ = fullname.rpartition('.')[0]
mod.__file__ = srcfile
-exec code in mod.__dict__
+exec(code, mod.__dict__)
except Exception:
del sys.modules[fullname]
raise
diff --git a/src/python/m5/internal/params.py
b/src/python/m5/internal/params.py
index ef94ad4..400e780 100644
--- a/src/python/m5/internal/params.py
+++ b/src/python/m5/internal/params.py
@@ -43,4 +43,4 @@
for name, module in inspect.getmembers(_m5):
if name.startswith('param_') or name.startswith('enum_'):
-exec "from _m5.%s import *" % name
+exec("from _m5.%s import *" % name)
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index e4619c0..8a259f3 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -148,7 +148,7 @@
options_file = config.get('options.py')
if options_file:
scope = { 'options' : options }
-execfile(options_file, scope)
+exec(compile(open(options_file).read(), options_file, 'exec'),
scope)
arguments = options.parse_args()
return options,arguments
@@ -191,6 +191,13 @@
# isn't available.
code.InteractiveConsole(scope).interact(banner)
+
+def _check_tracing():
+if defines.TRACING_ON:
+return
+
+fatal("Tracing is not enabled. Compile with TRACING_ON")
+
def main(*args):
import m5
@@ -213,12 +220,6 @@
m5.options = options
-def check_tracing():
-if defines.TRACING_ON:
-return
-
-fatal("Tracing is not enabled. Compile with TRACING_ON")
-
# Set the main event queue for the main thread.
event.mainq = event.getEventQueue(0)
event.setEventQueue(event.mainq)
@@ -279,7 +280,7 @@
if options.debug_help:
done = True
-check_tracing()
+_check_tracing()
debug.help()
if options.list_sim_objects:
@@ -366,7 +367,7 @@
debug.schedBreak(int(when))
if options.debug_flags:
-check_tracing()
+_check_tracing()
on_flags = []
off_flags = []
@@ -386,21 +387,21 @@
debug.flags[flag].enable()
if options.debug_start:
-check_tracing()
+_check_tracing()
e = event.create(trace.enable, event.Event.Debug_Enable_Pri)
event.mainq.schedule(e, options.debug_start)
else:
trace.enable()
if options.debug_end:
-check_tracing()
+_check_tracing()
e = event.create(trace.disable, event.Event.Debug_Enable_Pri)
event.mainq.schedule(e, options.debug_end)
trace.output(options.debug_file)
for ignore in options.debug_ignore:
-check_tracing()
+_check_tracing()
trace.ignore(ignore)
sys.argv = arguments
@@ -432,7 +433,7 @@
t = t.tb_next
pdb.interaction(t.tb_frame,t)
else:
-exec filecode in scope
+exec(filecode, scope)
# once the script is done
if options.interactive:
diff --git a/src/python/m5/objects/__init__.py
b/src/python/m5/objects/__init__.py
index 29402c5..8186c52 100644
--- a/src/python/m5/objects/__init__.py
+++ b/src/python/m5/objects/__init__.py
@@ -36,4 +36,4 @@
for module in modules.iterkeys():
if module.startswith('m5.objects.'):
-exec "from %s import *" % module
+exec("from %s import *" % module)
diff --git a/src/python/m5/util/jobfile.py b/src/python/m5/util/jobfile.py
index ad5b5ff..613289a 100644
--- a/src/python/m5/util/jobfile.py
+++ b/src/python/m5/util/jobfile.py
@@ -417,7 +417,7 @@
raise AttributeError("Could not find file '%s'" % jobfile)
data = {}
-execfile(filename, data)
+exec(compile(open(filename).read(), filename, 'exec'), data)
if 'conf' not in
[gem5-dev] Change in gem5/gem5[master]: python: Switch to using open instead of file
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15985 )
Change subject: python: Switch to using open instead of file
..
python: Switch to using open instead of file
Python 3 doesn't support the file(name, mode) syntax which has been
deprecated in favour of open.
Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/15985
Reviewed-by: Gabe Black
Reviewed-by: Giacomo Travaglini
---
M src/python/importer.py
M src/python/m5/main.py
M src/python/m5/simulate.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/grammar.py
5 files changed, 7 insertions(+), 6 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/python/importer.py b/src/python/importer.py
index 60b9b35..c54fb49 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -67,7 +67,7 @@
override =
os.environ.get('M5_OVERRIDE_PY_SOURCE', 'false').lower()
if override in ('true', 'yes') and os.path.exists(abspath):
-src = file(abspath, 'r').read()
+src = open(abspath, 'r').read()
code = compile(src, abspath, 'exec')
if os.path.basename(srcfile) == '__init__.py':
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index d8c0d92..e4619c0 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -407,7 +407,7 @@
sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path
filename = sys.argv[0]
-filedata = file(filename, 'r').read()
+filedata = open(filename, 'r').read()
filecode = compile(filedata, filename, 'exec')
scope = { '__file__' : filename,
'__name__' : '__m5_main__' }
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 03cc253..d72dee2 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -92,7 +92,7 @@
for obj in root.descendants(): obj.unproxyParams()
if options.dump_config:
-ini_file = file(os.path.join(options.outdir,
options.dump_config), 'w')
+ini_file = open(os.path.join(options.outdir,
options.dump_config), 'w')
# Print ini sections in sorted order for easier diffing
for obj in sorted(root.descendants(), key=lambda o: o.path()):
obj.print_ini(ini_file)
@@ -101,7 +101,8 @@
if options.json_config:
try:
import json
-json_file = file(os.path.join(options.outdir,
options.json_config), 'w')
+json_file = open(
+os.path.join(options.outdir, options.json_config), 'w')
d = root.get_config_as_dict()
json.dump(d, json_file, indent=4)
json_file.close()
diff --git a/src/python/m5/util/code_formatter.py
b/src/python/m5/util/code_formatter.py
index d48c59b..129fbd0 100644
--- a/src/python/m5/util/code_formatter.py
+++ b/src/python/m5/util/code_formatter.py
@@ -154,7 +154,7 @@
self._data = []
def write(self, *args):
-f = file(os.path.join(*args), "w")
+f = open(os.path.join(*args), "w")
for data in self._data:
f.write(data)
f.close()
diff --git a/src/python/m5/util/grammar.py b/src/python/m5/util/grammar.py
index bb34298..fcd8df2 100644
--- a/src/python/m5/util/grammar.py
+++ b/src/python/m5/util/grammar.py
@@ -115,7 +115,7 @@
def parse_file(self, f, **kwargs):
if isinstance(f, basestring):
source = f
-f = file(f, 'r')
+f = open(f, 'r')
elif isinstance(f, file):
source = f.name
else:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15985
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1
Gerrit-Change-Number: 15985
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Sandbox Based Optimal Offset Implementation
Hello Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15095 to look at the new patch set (#3). Change subject: mem-cache: Sandbox Based Optimal Offset Implementation .. mem-cache: Sandbox Based Optimal Offset Implementation Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation. Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/sbooe.cc A src/mem/cache/prefetch/sbooe.hh 4 files changed, 281 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15095 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862 Gerrit-Change-Number: 15095 Gerrit-PatchSet: 3 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ivan Pizarro Gerrit-CC: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: A Best-Offset Prefetcher
Hello krishnendra nathella, Dam Sunwoo, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/14820 to look at the new patch set (#4). Change subject: mem-cache: A Best-Offset Prefetcher .. mem-cache: A Best-Offset Prefetcher Michaud, P. (2015, June). A best-offset prefetcher. In 2nd Data Prefetching Championship. Change-Id: I61bb89ca5639356d54aeb04e856d5bf6e8805c22 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/bop.cc A src/mem/cache/prefetch/bop.hh 4 files changed, 440 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14820 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I61bb89ca5639356d54aeb04e856d5bf6e8805c22 Gerrit-Change-Number: 14820 Gerrit-PatchSet: 4 Gerrit-Owner: Ivan Pizarro Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Ivan Pizarro Gerrit-Reviewer: krishnendra nathella Gerrit-CC: Andreas Sandberg Gerrit-CC: Daniel Carvalho Gerrit-CC: Juha Jäykkä Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Convert memtest to new framework
Jason Lowe-Power has uploaded a new patch set (#5) to the change originally created by Ayaz Akram. ( https://gem5-review.googlesource.com/c/public/gem5/+/15836 ) Change subject: tests: Convert memtest to new framework .. tests: Convert memtest to new framework The original memtest is located at: https://gem5.googlesource.com/public/gem5/+/master/tests/configs/memtest.py Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a Signed-off-by: Jason Lowe-Power --- A tests/gem5/memory/memtest-run.py M tests/gem5/memory/simple-run.py M tests/gem5/memory/test.py 3 files changed, 100 insertions(+), 11 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15836 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a Gerrit-Change-Number: 15836 Gerrit-PatchSet: 5 Gerrit-Owner: Ayaz Akram Gerrit-Reviewer: Ayaz Akram Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher
Hello Nikos Nikoleris, Daniel Carvalho, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16383 to look at the new patch set (#2). Change subject: mem-cache: Added the Slim AMPM Prefetcher .. mem-cache: Added the Slim AMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript M src/mem/cache/prefetch/access_map_pattern_matching.cc M src/mem/cache/prefetch/access_map_pattern_matching.hh A src/mem/cache/prefetch/slim_ampm.cc A src/mem/cache/prefetch/slim_ampm.hh 6 files changed, 213 insertions(+), 24 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16383 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Gerrit-Change-Number: 16383 Gerrit-PatchSet: 2 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15215 )
Change subject: mem-cache: Irregular Stream Buffer Prefetcher
..
mem-cache: Irregular Stream Buffer Prefetcher
Based in the description of the following publication:
Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses
for improved correlated prefetching. In Proceedings of the 46th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM,
New York, NY, USA, 247-259.
Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165
Reviewed-on: https://gem5-review.googlesource.com/c/15215
Maintainer: Andreas Sandberg
Reviewed-by: Daniel Carvalho
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/SConscript
A src/mem/cache/prefetch/irregular_stream_buffer.cc
A src/mem/cache/prefetch/irregular_stream_buffer.hh
4 files changed, 385 insertions(+), 0 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 7077417..2c31de9 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -266,3 +266,46 @@
DeltaCorrelatingPredictionTables(),
"Delta Correlating Prediction Tables object")
+class IrregularStreamBufferPrefetcher(QueuedPrefetcher):
+type = "IrregularStreamBufferPrefetcher"
+cxx_class = "IrregularStreamBufferPrefetcher"
+cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
+
+max_counter_value = Param.Unsigned(3,
+"Maximum value of the confidence counter")
+chunk_size = Param.Unsigned(256,
+"Maximum number of addresses in a temporal stream")
+degree = Param.Unsigned(4, "Number of prefetches to generate")
+training_unit_assoc = Param.Unsigned(128,
+"Associativity of the training unit")
+training_unit_entries = Param.MemorySize("128",
+"Number of entries of the training unit")
+training_unit_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc,
+size = Parent.training_unit_entries),
+"Indexing policy of the training unit")
+training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
+"Replacement policy of the training unit")
+
+prefetch_candidates_per_entry = Param.Unsigned(16,
+"Number of prefetch candidates stored in a SP-AMC entry")
+address_map_cache_assoc = Param.Unsigned(128,
+"Associativity of the PS/SP AMCs")
+address_map_cache_entries = Param.MemorySize("128",
+"Number of entries of the PS/SP AMCs")
+ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1,
+assoc = Parent.address_map_cache_assoc,
+size = Parent.address_map_cache_entries),
+"Indexing policy of the Physical-to-Structural Address Map Cache")
+ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
+LRURP(),
+"Replacement policy of the Physical-to-Structural Address Map
Cache")
+sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1,
+assoc = Parent.address_map_cache_assoc,
+size = Parent.address_map_cache_entries),
+"Indexing policy of the Structural-to-Physical Address Mao Cache")
+sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
+LRURP(),
+"Replacement policy of the Structural-to-Physical Address Map
Cache")
diff --git a/src/mem/cache/prefetch/SConscript
b/src/mem/cache/prefetch/SConscript
index a5d84fd..0a209ff 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -35,6 +35,7 @@
Source('access_map_pattern_matching.cc')
Source('base.cc')
Source('delta_correlating_prediction_tables.cc')
+Source('irregular_stream_buffer.cc')
Source('queued.cc')
Source('signature_path.cc')
Source('signature_path_v2.cc')
diff --git a/src/mem/cache/prefetch/irregular_stream_buffer.cc
b/src/mem/cache/prefetch/irregular_stream_buffer.cc
new file mode 100644
index 000..45aba0b
--- /dev/null
+++ b/src/mem/cache/prefetch/irregular_stream_buffer.cc
@@ -0,0 +1,210 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Slim AMPM Prefetcher
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16383
Change subject: mem-cache: Added the Slim AMPM Prefetcher
..
mem-cache: Added the Slim AMPM Prefetcher
Reference:
Towards Bandwidth-Efficient Prefetching with Slim AMPM.
Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship.
Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both
already
in gem5).
Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/SConscript
M src/mem/cache/prefetch/access_map_pattern_matching.cc
M src/mem/cache/prefetch/access_map_pattern_matching.hh
A src/mem/cache/prefetch/slim_ampm.cc
A src/mem/cache/prefetch/slim_ampm.hh
6 files changed, 212 insertions(+), 24 deletions(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 7077417..9811859 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -204,11 +204,16 @@
global_history_register_replacement_policy =
Param.BaseReplacementPolicy(
LRURP(), "Replacement policy of the global history register")
-class AccessMapPatternMatchingPrefetcher(QueuedPrefetcher):
-type = 'AccessMapPatternMatchingPrefetcher'
-cxx_class = 'AccessMapPatternMatchingPrefetcher'
+class AccessMapPatternMatching(ClockedObject):
+type = 'AccessMapPatternMatching'
+cxx_class = 'AccessMapPatternMatching'
cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
+block_size = Param.Unsigned(Parent.block_size,
+"Cacheline size used by the prefetcher using this object")
+
+limit_stride = Param.Unsigned(0,
+"Limit the strides checked up to -X/X, if 0, disable the limit")
start_degree = Param.Unsigned(4,
"Initial degree (Maximum number of prefetches generated")
hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone")
@@ -238,6 +243,13 @@
offchip_memory_latency = Param.Latency("30ns",
"Memory latency used to compute the required memory bandwidth")
+class AMPMPrefetcher(QueuedPrefetcher):
+type = 'AMPMPrefetcher'
+cxx_class = 'AMPMPrefetcher'
+cxx_header = "mem/cache/prefetch/access_map_pattern_matching.hh"
+ampm = Param.AccessMapPatternMatching( AccessMapPatternMatching(),
+"Access Map Pattern Matching object")
+
class DeltaCorrelatingPredictionTables(SimObject):
type = 'DeltaCorrelatingPredictionTables'
cxx_class = 'DeltaCorrelatingPredictionTables'
@@ -266,3 +278,22 @@
DeltaCorrelatingPredictionTables(),
"Delta Correlating Prediction Tables object")
+class SlimAccessMapPatternMatching(AccessMapPatternMatching):
+start_degree = 2
+limit_stride = 4
+
+class
SlimDeltaCorrelatingPredictionTables(DeltaCorrelatingPredictionTables):
+table_entries = "256"
+table_assoc = 256
+deltas_per_entry = 9
+
+class SlimAMPMPrefetcher(QueuedPrefetcher):
+type = 'SlimAMPMPrefetcher'
+cxx_class = 'SlimAMPMPrefetcher'
+cxx_header = "mem/cache/prefetch/slim_ampm.hh"
+
+ampm = Param.AccessMapPatternMatching(SlimAccessMapPatternMatching(),
+"Access Map Pattern Matching object")
+dcpt = Param.DeltaCorrelatingPredictionTables(
+SlimDeltaCorrelatingPredictionTables(),
+"Delta Correlating Prediction Tables object")
diff --git a/src/mem/cache/prefetch/SConscript
b/src/mem/cache/prefetch/SConscript
index a5d84fd..fdb2de9 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -38,5 +38,6 @@
Source('queued.cc')
Source('signature_path.cc')
Source('signature_path_v2.cc')
+Source('slim_ampm.cc')
Source('stride.cc')
Source('tagged.cc')
diff --git a/src/mem/cache/prefetch/access_map_pattern_matching.cc
b/src/mem/cache/prefetch/access_map_pattern_matching.cc
index 0f46eff..df2a9f7 100644
--- a/src/mem/cache/prefetch/access_map_pattern_matching.cc
+++ b/src/mem/cache/prefetch/access_map_pattern_matching.cc
@@ -32,11 +32,12 @@
#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/associative_set_impl.hh"
-#include "params/AccessMapPatternMatchingPrefetcher.hh"
+#include "params/AMPMPrefetcher.hh"
+#include "params/AccessMapPatternMatching.hh"
-AccessMapPatternMatchingPrefetcher::AccessMapPatternMatchingPrefetcher(
-const AccessMapPatternMatchingPrefetcherParams *p)
-: QueuedPrefetcher(p),
+AccessMapPatternMatching::AccessMapPatternMatching(
+const AccessMapPatternMatchingParams *p)
+: ClockedObject(p), blkSize(p->block_size),
limitStride(p->limit_stride),
startDegree(p->start_degree), hotZoneSize(p->hot_zone_size),
highCoverageThreshold(p->high_coverage_threshold),
lowCoverageThreshold(p->low_coverage_threshold),
@@ -62,7 +63,7 @@
}
void
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Hello Nikos Nikoleris, krishnendra nathella, Dam Sunwoo, Daniel Carvalho, Giacomo Travaglini, Andreas Sandberg, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 to look at the new patch set (#7). Change subject: mem-cache: Irregular Stream Buffer Prefetcher .. mem-cache: Irregular Stream Buffer Prefetcher Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 --- M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/prefetch/SConscript A src/mem/cache/prefetch/irregular_stream_buffer.cc A src/mem/cache/prefetch/irregular_stream_buffer.hh 4 files changed, 385 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15215 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Gerrit-Change-Number: 15215 Gerrit-PatchSet: 7 Gerrit-Owner: Javier Bueno Hedo Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Dam Sunwoo Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: krishnendra nathella Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: base: Fix enums checkpointing
Hello Ciro Santilli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/16382
to review the following change.
Change subject: base: Fix enums checkpointing
..
base: Fix enums checkpointing
Creating an extra version of string to number converters (__to_number)
in base/str.hh; it will be used by enums only when unserializing
them. The reason not to have a single helper for both enums and
integers is that std::numeric_limits trait is not specialized for enums.
We fix this by using the std::underlying_type trait.
Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
---
M src/base/str.hh
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/src/base/str.hh b/src/base/str.hh
index 61022bd..1d7c780 100644
--- a/src/base/str.hh
+++ b/src/base/str.hh
@@ -40,6 +40,7 @@
#include
#include
#include
+#include
#include
#include "base/logging.hh"
@@ -108,8 +109,7 @@
* integeral type, as well as enums and floating-point types.
*/
template
-typename std::enable_if<(std::is_integral::value ||
-std::is_enum::value) &&
+typename std::enable_if::value &&
std::is_signed::value, T>::type
__to_number(const std::string )
{
@@ -121,8 +121,7 @@
}
template
-typename std::enable_if<(std::is_integral::value ||
-std::is_enum::value) &&
+typename std::enable_if::value &&
!std::is_signed::value, T>::type
__to_number(const std::string )
{
@@ -134,6 +133,30 @@
}
template
+typename std::enable_if::value, T>::type
+__to_number(const std::string )
+{
+// start big and narrow it down if needed, determine the base
dynamically
+long long r = std::stoll(value, nullptr, 0);
+
+// Check if value is out of range. The check is different depending on
+// whether it is a signed or unsigned enum
+if (std::is_signed::type>::value) {
+if (r < std::numeric_limits<
+typename std::underlying_type::type>::min() ||
+r > std::numeric_limits<
+typename std::underlying_type::type>::max())
+throw std::out_of_range("Out of range");
+} else {
+if (r > std::numeric_limits<
+typename std::underlying_type::type>::max())
+throw std::out_of_range("Out of range");
+}
+
+return static_cast(r);
+}
+
+template
typename std::enable_if::value, T>::type
__to_number(const std::string )
{
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16382
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Gerrit-Change-Number: 16382
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Added the Delta Correlating Prediction Tables Prefetcher
Javier Bueno Hedo has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16062 )
Change subject: mem-cache: Added the Delta Correlating Prediction Tables
Prefetcher
..
mem-cache: Added the Delta Correlating Prediction Tables Prefetcher
Reference:
Multi-level hardware prefetching using low complexity delta correlating
prediction tables with partial matching.
Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
In Proceedings of the 5th international conference on High Performance
Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho
Maintainer: Andreas Sandberg
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/SConscript
M src/mem/cache/prefetch/base.hh
A src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
A src/mem/cache/prefetch/delta_correlating_prediction_tables.hh
M src/mem/cache/prefetch/queued.hh
6 files changed, 347 insertions(+), 2 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 827a66b..7077417 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -237,3 +237,32 @@
epoch_cycles = Param.Cycles(256000, "Cycles in an epoch period")
offchip_memory_latency = Param.Latency("30ns",
"Memory latency used to compute the required memory bandwidth")
+
+class DeltaCorrelatingPredictionTables(SimObject):
+type = 'DeltaCorrelatingPredictionTables'
+cxx_class = 'DeltaCorrelatingPredictionTables'
+cxx_header
= "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
+deltas_per_entry = Param.Unsigned(20,
+"Number of deltas stored in each table entry")
+delta_bits = Param.Unsigned(12, "Bits per delta")
+delta_mask_bits = Param.Unsigned(8,
+"Lower bits to mask when comparing deltas")
+table_entries = Param.MemorySize("128",
+"Number of entries in the table")
+table_assoc = Param.Unsigned(128,
+"Associativity of the table")
+table_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1, assoc = Parent.table_assoc,
+size = Parent.table_entries),
+"Indexing policy of the table")
+table_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
+"Replacement policy of the table")
+
+class DCPTPrefetcher(QueuedPrefetcher):
+type = 'DCPTPrefetcher'
+cxx_class = 'DCPTPrefetcher'
+cxx_header
= "mem/cache/prefetch/delta_correlating_prediction_tables.hh"
+dcpt = Param.DeltaCorrelatingPredictionTables(
+DeltaCorrelatingPredictionTables(),
+"Delta Correlating Prediction Tables object")
+
diff --git a/src/mem/cache/prefetch/SConscript
b/src/mem/cache/prefetch/SConscript
index f9582b5..a5d84fd 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -34,6 +34,7 @@
Source('access_map_pattern_matching.cc')
Source('base.cc')
+Source('delta_correlating_prediction_tables.cc')
Source('queued.cc')
Source('signature_path.cc')
Source('signature_path_v2.cc')
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 06f7749..de275f8 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -76,7 +76,8 @@
};
std::vector listeners;
- protected:
+
+ public:
/**
* Class containing the information needed by the prefetch to train and
@@ -168,6 +169,8 @@
PrefetchInfo(PrefetchInfo const , Addr addr);
};
+ protected:
+
// PARAMETERS
/** Pointr to the parent cache. */
diff --git a/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
b/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
new file mode 100644
index 000..4dbd596
--- /dev/null
+++ b/src/mem/cache/prefetch/delta_correlating_prediction_tables.cc
@@ -0,0 +1,174 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written
[gem5-dev] Change in gem5/gem5[master]: tests: Rewrite Makefiles for pthreads test
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16022 )
Change subject: tests: Rewrite Makefiles for pthreads test
..
tests: Rewrite Makefiles for pthreads test
The Makefiles for the pthreads test don't behave like typical
Makefiles that support cross compilation. Rewrite the Makefile to make
cross-compilation more convenient and add targets for aarch{32,64}.
Change-Id: I7cae378492681744b6bb11dd5af69db81ec54229
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/16022
Reviewed-by: Jason Lowe-Power
---
A tests/test-progs/pthread/Makefile.aarch32
A tests/test-progs/pthread/Makefile.aarch64
A tests/test-progs/pthread/Makefile.common
M tests/test-progs/pthread/Makefile.riscv
M tests/test-progs/pthread/Makefile.x86
5 files changed, 226 insertions(+), 62 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/tests/test-progs/pthread/Makefile.aarch32
b/tests/test-progs/pthread/Makefile.aarch32
new file mode 100644
index 000..b3d441b
--- /dev/null
+++ b/tests/test-progs/pthread/Makefile.aarch32
@@ -0,0 +1,41 @@
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+CROSS_COMPILE = arm-linux-gnueabihf-
+BIN_DIR = bin.aarch32
+
+-include Makefile.common
diff --git a/tests/test-progs/pthread/Makefile.aarch64
b/tests/test-progs/pthread/Makefile.aarch64
new file mode 100644
index 000..f11dffa
--- /dev/null
+++ b/tests/test-progs/pthread/Makefile.aarch64
@@ -0,0 +1,41 @@
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this
[gem5-dev] Change in gem5/gem5[master]: python: Switch to using open instead of file
Hello Gabe Black, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15985 to look at the new patch set (#4). Change subject: python: Switch to using open instead of file .. python: Switch to using open instead of file Python 3 doesn't support the file(name, mode) syntax which has been deprecated in favour of open. Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Signed-off-by: Andreas Sandberg --- M src/python/importer.py M src/python/m5/main.py M src/python/m5/simulate.py M src/python/m5/util/code_formatter.py M src/python/m5/util/grammar.py 5 files changed, 7 insertions(+), 6 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15985 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Gerrit-Change-Number: 15985 Gerrit-PatchSet: 4 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Enforce absolute imports for Python 3 compatibility
Hello Gabe Black, Jason Lowe-Power, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15983 to look at the new patch set (#4). Change subject: python: Enforce absolute imports for Python 3 compatibility .. python: Enforce absolute imports for Python 3 compatibility Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6 Signed-off-by: Andreas Sandberg --- M src/python/importer.py M src/python/m5/SimObject.py M src/python/m5/__init__.py M src/python/m5/core.py M src/python/m5/ext/__init__.py M src/python/m5/ext/pyfdt/pyfdt.py M src/python/m5/internal/params.py M src/python/m5/main.py M src/python/m5/objects/__init__.py M src/python/m5/options.py M src/python/m5/params.py M src/python/m5/proxy.py M src/python/m5/simulate.py M src/python/m5/trace.py M src/python/m5/util/__init__.py M src/python/m5/util/code_formatter.py M src/python/m5/util/dot_writer.py M src/python/m5/util/jobfile.py M src/python/m5/util/pybind.py M src/python/m5/util/smartdict.py M src/python/m5/util/sorteddict.py M src/python/m5/util/terminal.py 22 files changed, 83 insertions(+), 41 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15983 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6 Gerrit-Change-Number: 15983 Gerrit-PatchSet: 4 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Replace DictMixin with Mapping / MutableMapping
Hello Giacomo Travaglini, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/15984 to look at the new patch set (#4). Change subject: python: Replace DictMixin with Mapping / MutableMapping .. python: Replace DictMixin with Mapping / MutableMapping Python 3 has removed support for DictMixin, so switch to Mapping / MutableMapping in collections which provides the same functionality. Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32 Signed-off-by: Andreas Sandberg --- M src/python/m5/debug.py 1 file changed, 10 insertions(+), 14 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15984 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32 Gerrit-Change-Number: 15984 Gerrit-PatchSet: 4 Gerrit-Owner: Andreas Sandberg Gerrit-Assignee: Jason Lowe-Power Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: python: Don't assume SimObjects live in the global namespace
Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/15981 ) Change subject: python: Don't assume SimObjects live in the global namespace .. python: Don't assume SimObjects live in the global namespace The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power Reviewed-by: Giacomo Travaglini --- M src/arch/alpha/AlphaSystem.py M src/arch/alpha/AlphaTLB.py M src/arch/arm/ArmISA.py M src/arch/arm/ArmNativeTrace.py M src/arch/arm/ArmPMU.py M src/arch/arm/ArmSemihosting.py M src/arch/arm/ArmSystem.py M src/arch/arm/ArmTLB.py M src/arch/arm/tracers/TarmacTrace.py M src/arch/mips/MipsSystem.py M src/arch/mips/MipsTLB.py M src/arch/power/PowerTLB.py M src/arch/riscv/RiscvSystem.py M src/arch/riscv/RiscvTLB.py M src/arch/sparc/SparcNativeTrace.py M src/arch/sparc/SparcSystem.py M src/arch/sparc/SparcTLB.py M src/arch/x86/X86LocalApic.py M src/arch/x86/X86NativeTrace.py M src/arch/x86/X86System.py M src/arch/x86/X86TLB.py M src/base/vnc/Vnc.py M src/cpu/BaseCPU.py M src/cpu/CPUTracers.py M src/cpu/CheckerCPU.py M src/cpu/DummyChecker.py M src/cpu/InstPBTrace.py M src/cpu/kvm/BaseKvmCPU.py M src/cpu/kvm/X86KvmCPU.py M src/cpu/minor/MinorCPU.py M src/cpu/o3/FUPool.py M src/cpu/o3/FuncUnitConfig.py M src/cpu/o3/O3CPU.py M src/cpu/o3/O3Checker.py M src/cpu/o3/probe/ElasticTrace.py M src/cpu/o3/probe/SimpleTrace.py M src/cpu/simple/AtomicSimpleCPU.py M src/cpu/simple/BaseSimpleCPU.py M src/cpu/simple/NonCachingSimpleCPU.py M src/cpu/simple/TimingSimpleCPU.py M src/cpu/simple/probes/SimPoint.py M src/cpu/testers/directedtest/RubyDirectedTester.py M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py M src/cpu/testers/memtest/MemTest.py M src/cpu/testers/rubytest/RubyTester.py M src/cpu/testers/traffic_gen/BaseTrafficGen.py M src/cpu/testers/traffic_gen/PyTrafficGen.py M src/cpu/testers/traffic_gen/TrafficGen.py M src/cpu/trace/TraceCPU.py M src/dev/BadDevice.py M src/dev/Device.py M src/dev/Platform.py M src/dev/alpha/AlphaBackdoor.py M src/dev/alpha/Tsunami.py M src/dev/arm/EnergyCtrl.py M src/dev/arm/FlashDevice.py M src/dev/arm/Gic.py M src/dev/arm/NoMali.py M src/dev/arm/RealView.py M src/dev/arm/UFSHostDevice.py M src/dev/arm/VirtIOMMIO.py M src/dev/i2c/I2C.py M src/dev/mips/Malta.py M src/dev/net/Ethernet.py M src/dev/pci/CopyEngine.py M src/dev/pci/PciDevice.py M src/dev/pci/PciHost.py M src/dev/serial/Terminal.py M src/dev/serial/Uart.py M src/dev/sparc/T1000.py M src/dev/storage/Ide.py M src/dev/virtio/VirtIO.py M src/dev/virtio/VirtIO9P.py M src/dev/virtio/VirtIOBlock.py M src/dev/virtio/VirtIOConsole.py M src/dev/x86/Cmos.py M src/dev/x86/I8042.py M src/dev/x86/I82094AA.py M src/dev/x86/I8237.py M src/dev/x86/I8254.py M src/dev/x86/I8259.py M src/dev/x86/Pc.py M src/dev/x86/PcSpeaker.py M src/dev/x86/SouthBridge.py M src/gpu-compute/GPU.py M src/gpu-compute/LdsState.py M src/learning_gem5/part2/SimpleCache.py M src/learning_gem5/part2/SimpleMemobj.py M src/mem/AbstractMemory.py M src/mem/AddrMapper.py M src/mem/Bridge.py M src/mem/CommMonitor.py M src/mem/DRAMCtrl.py M src/mem/ExternalMaster.py M src/mem/ExternalSlave.py M src/mem/HMCController.py M src/mem/MemChecker.py M src/mem/MemDelay.py M src/mem/MemObject.py M src/mem/SerialLink.py M src/mem/SimpleMemory.py M src/mem/XBar.py M src/mem/cache/Cache.py M src/mem/cache/prefetch/Prefetcher.py M src/mem/cache/tags/Tags.py M src/mem/probes/MemFootprintProbe.py M src/mem/probes/MemTraceProbe.py M src/mem/probes/StackDistProbe.py M src/mem/qos/QoSMemCtrl.py M src/mem/qos/QoSMemSinkCtrl.py M src/mem/ruby/network/BasicRouter.py M src/mem/ruby/network/Network.py M src/mem/ruby/network/garnet2.0/GarnetLink.py M src/mem/ruby/network/garnet2.0/GarnetNetwork.py M src/mem/ruby/network/simple/SimpleLink.py M src/mem/ruby/network/simple/SimpleNetwork.py M src/mem/ruby/slicc_interface/Controller.py M src/mem/ruby/structures/LRUReplacementPolicy.py M src/mem/ruby/structures/PseudoLRUReplacementPolicy.py M src/mem/ruby/structures/RubyCache.py M src/mem/ruby/structures/RubyPrefetcher.py M src/mem/ruby/system/GPUCoalescer.py M src/mem/ruby/system/RubySystem.py M src/mem/ruby/system/Sequencer.py M src/mem/ruby/system/VIPERCoalescer.py M src/mem/ruby/system/WeightedLRUReplacementPolicy.py M src/mem/slicc/symbols/StateMachine.py M src/sim/System.py M src/sim/TickedObject.py M src/sim/power/MathExprPowerModel.py M src/sim/power/ThermalModel.py 131 files changed, 300 insertions(+), 267 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Giacomo
[gem5-dev] Change in gem5/gem5[master]: arch-mips: Remove unused Python file
Andreas Sandberg has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/16302 ) Change subject: arch-mips: Remove unused Python file .. arch-mips: Remove unused Python file Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/16302 Reviewed-by: Jason Lowe-Power Reviewed-by: Gabe Black Maintainer: Gabe Black --- D src/arch/mips/MipsCPU.py 1 file changed, 0 insertions(+), 92 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved diff --git a/src/arch/mips/MipsCPU.py b/src/arch/mips/MipsCPU.py deleted file mode 100644 index 48ee417..000 --- a/src/arch/mips/MipsCPU.py +++ /dev/null @@ -1,92 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2007 MIPS Technologies, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Jaidev Patwardhan -# Korey Sewell - -from m5.defines import buildEnv -from m5.params import * - -from BaseCPU import BaseCPU - -class BaseMipsCPU(BaseCPU) -if buildEnv['TARGET_ISA'] == 'mips': -CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") -CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") -CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") -CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") -CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") -CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") -CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") -CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") -CP0_Config_BE = Param.Unsigned(0,"Big Endian?") -CP0_Config_AT = Param.Unsigned(0,"No Description") -CP0_Config_AR = Param.Unsigned(0,"No Description") -CP0_Config_MT = Param.Unsigned(0,"No Description") -CP0_Config_VI = Param.Unsigned(0,"No Description") -CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") -CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") -CP0_Config1_IS = Param.Unsigned(0,"No Description") -CP0_Config1_IL = Param.Unsigned(0,"No Description") -CP0_Config1_IA = Param.Unsigned(0,"No Description") -CP0_Config1_DS = Param.Unsigned(0,"No Description") -CP0_Config1_DL = Param.Unsigned(0,"No Description") -CP0_Config1_DA = Param.Unsigned(0,"No Description") -CP0_Config1_C2 = Param.Bool(False,"No Description") -CP0_Config1_MD = Param.Bool(False,"No Description") -CP0_Config1_PC = Param.Bool(False,"No Description") -CP0_Config1_WR = Param.Bool(False,"No Description") -CP0_Config1_CA = Param.Bool(False,"No Description") -CP0_Config1_EP = Param.Bool(False,"No Description") -CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") -CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") -CP0_Config2_TU = Param.Unsigned(0,"No Description") -CP0_Config2_TS = Param.Unsigned(0,"No Description") -CP0_Config2_TL = Param.Unsigned(0,"No Description") -CP0_Config2_TA = Param.Unsigned(0,"No Description") -CP0_Config2_SU = Param.Unsigned(0,"No Description") -CP0_Config2_SS =
[gem5-dev] Change in gem5/gem5[master]: python: Make exception handling Python 3 safe
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15980 )
Change subject: python: Make exception handling Python 3 safe
..
python: Make exception handling Python 3 safe
Change-Id: I9c2cdfad20deb1ddfa224320cf93f2105d126652
Reviewed-on: https://gem5-review.googlesource.com/c/15980
Maintainer: Andreas Sandberg
Reviewed-by: Giacomo Travaglini
---
M src/python/importer.py
M src/python/m5/SimObject.py
M src/python/m5/main.py
M src/python/m5/params.py
M src/python/m5/proxy.py
M src/python/m5/simulate.py
M src/python/m5/ticks.py
M src/python/m5/util/__init__.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/convert.py
M src/python/m5/util/grammar.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
13 files changed, 177 insertions(+), 182 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
diff --git a/src/python/importer.py b/src/python/importer.py
index fa26080..60b9b35 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -35,7 +35,7 @@
def add_module(self, filename, abspath, modpath, code):
if modpath in self.modules:
-raise AttributeError, "%s already found in importer" % modpath
+raise AttributeError("%s already found in importer" % modpath)
self.modules[modpath] = (filename, abspath, code)
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 44f26ea..97cf6d0 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -483,8 +483,8 @@
if isinstance(c, MetaSimObject):
bTotal += 1
if bTotal > 1:
-raise TypeError, \
- "SimObjects do not support multiple inheritance"
+raise TypeError(
+ "SimObjects do not support multiple inheritance")
base = bases[0]
@@ -543,8 +543,8 @@
def _set_keyword(cls, keyword, val, kwtype):
if not isinstance(val, kwtype):
-raise TypeError, 'keyword %s has bad type %s (expecting %s)' %
\
- (keyword, type(val), kwtype)
+raise TypeError('keyword %s has bad type %s (expecting %s)' % \
+ (keyword, type(val), kwtype))
if isinstance(val, FunctionType):
val = classmethod(val)
type.__setattr__(cls, keyword, val)
@@ -562,7 +562,7 @@
try:
hr_value = value
value = param.convert(value)
-except Exception, e:
+except Exception as e:
msg = "%s\nError setting param %s.%s to %s\n" % \
(e, cls.__name__, name, value)
e.args = (msg, )
@@ -622,10 +622,10 @@
return
if isSimObjectOrSequence(value) and cls._instantiated:
-raise RuntimeError, \
+raise RuntimeError(
"cannot set SimObject parameter '%s' after\n" \
"class %s has been instantiated or subclassed" \
- % (attr, cls.__name__)
+ % (attr, cls.__name__))
# check for param
param = cls._params.get(attr)
@@ -639,8 +639,8 @@
return
# no valid assignment... raise exception
-raise AttributeError, \
- "Class %s has no parameter \'%s\'" % (cls.__name__, attr)
+raise AttributeError(
+ "Class %s has no parameter \'%s\'" % (cls.__name__, attr))
def __getattr__(cls, attr):
if attr == 'cxx_class_path':
@@ -658,8 +658,8 @@
if cls._children.has_key(attr):
return cls._children[attr]
-raise AttributeError, \
- "object '%s' has no attribute '%s'" % (cls.__name__, attr)
+raise AttributeError(
+ "object '%s' has no attribute '%s'" % (cls.__name__, attr))
def __str__(cls):
return cls.__name__
@@ -1152,9 +1152,9 @@
# no memo_dict: must be top-level clone operation.
# this is only allowed at the root of a hierarchy
if self._parent:
-raise RuntimeError, "attempt to clone object %s " \
+raise RuntimeError("attempt to clone object %s " \
"not at the root of a tree (parent = %s)" \
- % (self, self._parent)
+ % (self, self._parent))
# create a new dict and use that.
memo_dict = {}
kwargs['_memo'] = memo_dict
@@ -1196,7 +1196,7 @@
err_string += "\n (C++ object is not yet constructed," \
" so wrapped C++ methods are unavailable.)"
-raise AttributeError, err_string
+raise AttributeError(err_string)
# Set attribute (called on foo.attr = value when foo is an
# instance of class cls).
@@
[gem5-dev] Change in gem5/gem5[master]: python: Fix native module initialisation on Python 3
Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15979 )
Change subject: python: Fix native module initialisation on Python 3
..
python: Fix native module initialisation on Python 3
The approach we currently use to register our native modules doesn't
work on Python 3. Convert the code to use the Python inittab instead
of the old ad-hoc method.
Change-Id: I961f8a33993c621473732faeaab955a882769a4b
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/15979
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
---
M src/sim/init.cc
M src/sim/init.hh
M src/sim/main.cc
3 files changed, 24 insertions(+), 14 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, but someone else must approve
Andreas Sandberg: Looks good to me, approved
diff --git a/src/sim/init.cc b/src/sim/init.cc
index 66ec408..5a49f36 100644
--- a/src/sim/init.cc
+++ b/src/sim/init.cc
@@ -191,7 +191,11 @@
return objs;
}
+#if PY_MAJOR_VERSION >= 3
+PyObject *
+#else
void
+#endif
EmbeddedPyBind::initAll()
{
std::list pending;
@@ -226,13 +230,18 @@
}
}
}
+
+#if PY_MAJOR_VERSION >= 3
+return m_m5.ptr();
+#endif
}
-int
-initM5Python()
+void
+registerNativeModules()
{
-EmbeddedPyBind::initAll();
-return EmbeddedPython::initAll();
+auto result = PyImport_AppendInittab("_m5", EmbeddedPyBind::initAll);
+if (result == -1)
+panic("Failed to add _m5 to Python's inittab\n");
}
/*
@@ -307,10 +316,3 @@
return 0;
}
-
-PyMODINIT_FUNC
-initm5(void)
-{
-initM5Python();
-PyImport_ImportModule(PyCC("m5"));
-}
diff --git a/src/sim/init.hh b/src/sim/init.hh
index de6b44d..40ff9ae 100644
--- a/src/sim/init.hh
+++ b/src/sim/init.hh
@@ -90,7 +90,11 @@
EmbeddedPyBind(const char *_name,
void (*init_func)(pybind11::module &));
+#if PY_MAJOR_VERSION >= 3
+static PyObject *initAll();
+#else
static void initAll();
+#endif
private:
void (*initFunc)(pybind11::module &);
@@ -105,8 +109,8 @@
static std::map ();
};
-int initM5Python();
+void registerNativeModules();
+
int m5Main(int argc, char **argv);
-PyMODINIT_FUNC initm5(void);
#endif // __SIM_INIT_HH__
diff --git a/src/sim/main.cc b/src/sim/main.cc
index a77c5f5..168e439 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -54,11 +54,15 @@
Py_SetProgramName(argv[0]);
#endif
+// Register native modules with Python's init system before
+// initializing the interpreter.
+registerNativeModules();
+
// initialize embedded Python interpreter
Py_Initialize();
// Initialize the embedded m5 python library
-ret = initM5Python();
+ret = EmbeddedPython::initAll();
if (ret == 0) {
// start m5
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15979
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I961f8a33993c621473732faeaab955a882769a4b
Gerrit-Change-Number: 15979
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! *
