[gem5-dev] Change in gem5/gem5[master]: scons: Fix an error about an unrecognized compiler.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25203 )
Change subject: scons: Fix an error about an unrecognized compiler.
..
scons: Fix an error about an unrecognized compiler.
join was being passed a series of strings to join as separate
arguments like os.path.join, but it expects to get them as members of a
single sequence.
Change-Id: Id88ce4e9c5400f256a1af6351b4a964af0036b72
---
M SConstruct
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/SConstruct b/SConstruct
index f378227..eb3a9e4 100755
--- a/SConstruct
+++ b/SConstruct
@@ -389,7 +389,7 @@
'-Wno-error=deprecated',
])
else:
-error('\n'.join(
+error('\n'.join((
"Don't know what compiler options to use for your compiler.",
"compiler: " + main['CXX'],
"version: " + CXX_version.replace('\n', '') if
@@ -400,7 +400,7 @@
"",
"If you are trying to use a compiler other than those listed",
"above you will need to ease fix SConstruct and ",
- "src/SConscript to support that compiler."))
+ "src/SConscript to support that compiler.")))
if main['GCC']:
# Check for a supported version of gcc. >= 4.8 is chosen for its
--
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Gerrit-Change-Id: Id88ce4e9c5400f256a1af6351b4a964af0036b72
Gerrit-Change-Number: 25203
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: FAILED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: FAILED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: FAILED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: FAILED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: FAILED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: FAILED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: FAILED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: FAILED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: FAILED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing: FAILED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! scons: *** [build/HSAIL_X86/gpu-compute/gpu_static_inst.do] Error 1 scons: *** [build/HSAIL_X86/gpu-compute/gpu_dyn_inst.do] Error 1 scons: *** [build/HSAIL_X86/arch/hsail/insts/gpu_static_inst.do] Error 1 scons: *** [build/HSAIL_X86/arch/hsail/i
[gem5-dev] Change in gem5/gem5[master]: configs: Using VExpress_GEM5_V1 as a default for Options.py
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/25183
to review the following change.
Change subject: configs: Using VExpress_GEM5_V1 as a default for Options.py
..
configs: Using VExpress_GEM5_V1 as a default for Options.py
This is replacing deprecated VExpress_EMM for scripts using Options.py,
like fs.py.
Change-Id: I2ba01b248bb9baf49e1f2217d623f3b9bc8a35f9
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
---
M configs/common/Options.py
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 4943486..a126f3c 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -434,7 +434,7 @@
help="List available platform types")
parser.add_option("--machine-type", action="store", type="choice",
choices=ObjectList.platform_list.get_names(),
-default="VExpress_EMM")
+default="VExpress_GEM5_V1")
parser.add_option("--dtb-filename", action="store", type="string",
help="Specifies device tree blob file to use with
device-tree-"\
"enabled kernels")
--
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Gerrit-Branch: master
Gerrit-Change-Id: I2ba01b248bb9baf49e1f2217d623f3b9bc8a35f9
Gerrit-Change-Number: 25183
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: x86: Handle m5 op accesses directly in the mmapped IPR handlers.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23184 )
Change subject: x86: Handle m5 op accesses directly in the mmapped IPR
handlers.
..
x86: Handle m5 op accesses directly in the mmapped IPR handlers.
The common handlers only handle the m5ops, and it takes more plumbing
to get to them than to just handle the m5ops directly from x86.
Also, centralizing the call to PseudoInst::pseudoInst prevents
specializing the ABI per-ISA.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: Ife9cf0d61ac87605ddc9cf9c84feebb8b23cc33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23184
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/mmapped_ipr.hh
M src/arch/x86/tlb.cc
2 files changed, 27 insertions(+), 22 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 27cb4de..53690d9 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -46,47 +46,55 @@
* ISA-specific helper functions for memory mapped IPR accesses.
*/
-#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/regs/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
namespace X86ISA
{
inline Cycles
-handleIprRead(ThreadContext *xc, Packet *pkt)
+handleIprRead(ThreadContext *tc, Packet *pkt)
{
-if (GenericISA::isGenericIprAccess(pkt)) {
-return GenericISA::handleGenericIprRead(xc, pkt);
+Addr addr = pkt->getAddr();
+auto m5opRange = tc->getSystemPtr()->m5opRange();
+if (m5opRange.contains(addr)) {
+uint8_t func;
+PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+uint64_t ret = PseudoInst::pseudoInst(tc, func);
+pkt->setLE(ret);
} else {
-Addr offset = pkt->getAddr() & mask(3);
-MiscRegIndex index = (MiscRegIndex)(
-pkt->getAddr() / sizeof(RegVal));
-RegVal data = htole(xc->readMiscReg(index));
+Addr offset = addr & mask(3);
+MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
+RegVal data = htole(tc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(RegVal));
pkt->setData(((uint8_t *)&data) + offset);
-return Cycles(1);
}
+return Cycles(1);
}
inline Cycles
-handleIprWrite(ThreadContext *xc, Packet *pkt)
+handleIprWrite(ThreadContext *tc, Packet *pkt)
{
-if (GenericISA::isGenericIprAccess(pkt)) {
-return GenericISA::handleGenericIprWrite(xc, pkt);
+Addr addr = pkt->getAddr();
+auto m5opRange = tc->getSystemPtr()->m5opRange();
+if (m5opRange.contains(addr)) {
+uint8_t func;
+PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+PseudoInst::pseudoInst(tc, func);
} else {
-Addr offset = pkt->getAddr() & mask(3);
-MiscRegIndex index = (MiscRegIndex)(
-pkt->getAddr() / sizeof(RegVal));
-RegVal data = htole(xc->readMiscRegNoEffect(index));
+Addr offset = addr & mask(3);
+MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));
+RegVal data = htole(tc->readMiscRegNoEffect(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(RegVal));
pkt->writeData(((uint8_t *)&data) + offset);
-xc->setMiscReg(index, letoh(data));
-return Cycles(1);
+tc->setMiscReg(index, letoh(data));
}
+return Cycles(1);
}
}
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 65ed9c0..a649871 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -230,10 +230,7 @@
Addr paddr = req->getPaddr();
if (m5opRange.contains(paddr)) {
-req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
- Request::STRICT_ORDER);
-req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF,
- paddr & 0xFF));
+req->setFlags(Request::MMAPPED_IPR | Request::STRICT_ORDER);
} else if (FullSystem) {
// Check for an access to the local APIC
LocalApicBase localApicBase =
--
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Ge
[gem5-dev] Change in gem5/gem5[master]: systemc: gem5_to_tlm: treat non-rw as ignorable command
Earl Ou has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/25163 )
Change subject: systemc: gem5_to_tlm: treat non-rw as ignorable command
..
systemc: gem5_to_tlm: treat non-rw as ignorable command
Treat all kinds of non read/write requests in gem5_to_tlm bridge as
ignorable
commands.
Change-Id: I5236e1b31f9a57470dc666d01cbe96249f48ed5d
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index f6ea811..8c11c97 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -105,13 +105,10 @@
trans->set_command(tlm::TLM_IGNORE_COMMAND);
} else if (packet->isRead()) {
trans->set_command(tlm::TLM_READ_COMMAND);
-} else if (packet->isInvalidate()) {
-/* Do nothing */
-trans->set_command(tlm::TLM_IGNORE_COMMAND);
} else if (packet->isWrite()) {
trans->set_command(tlm::TLM_WRITE_COMMAND);
} else {
-SC_REPORT_FATAL("Gem5ToTlmBridge", "No R/W packet");
+trans->set_command(tlm::TLM_IGNORE_COMMAND);
}
// Attach the packet pointer to the TLM transaction to keep track.
@@ -284,10 +281,6 @@
panic_if(packet->cacheResponding(),
"Should not see packets where cache is responding");
-panic_if(!(packet->isRead() || packet->isWrite()),
- "Should only see read and writes at TLM memory\n");
-
-
// We should never get a second request after noting that a retry is
// required.
sc_assert(!needToSendRequestRetry);
--
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Gerrit-Change-Id: I5236e1b31f9a57470dc666d01cbe96249f48ed5d
Gerrit-Change-Number: 25163
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Gerrit-Owner: Earl Ou
Gerrit-MessageType: newchange
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