[gem5-dev] Change in gem5/gem5[develop]: sim-se: Add special paths for MPI, libnuma, ROCm support

2020-03-25 Thread Matthew Poremba (Gerrit) 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25367 )


Change subject: sim-se: Add special paths for MPI, libnuma, ROCm support
..

sim-se: Add special paths for MPI, libnuma, ROCm support

Add new pseudo files which are read by various runtime libraries
including MPI, libnuma, and ROCm. New paths include /proc/self/maps,
/dev/urandom, and /sys/devices/system/cpu/online.

Change-Id: I00a82788cff9d6f4f16fc56230b18be9b76c4015
Signed-off-by: Brandon Potter 
Signed-off-by: Michael LeBeane 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25367
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
---
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
M src/sim/mem_state.cc
M src/sim/mem_state.hh
M src/sim/syscall_emul.hh
5 files changed, 77 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Brandon Potter: Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc
index 1a8c241..ae1d47c 100644
--- a/src/kern/linux/linux.cc
+++ b/src/kern/linux/linux.cc
@@ -33,8 +33,14 @@

 #include "cpu/base.hh"
 #include "debug/SyscallVerbose.hh"
+#include "sim/mem_state.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
+#include "sim/vma.hh"
+
+// The OS methods are called statically. Instantiate the random number
+// generator for access to /dev/urandom here.
+Random Linux::random;

 int
 Linux::openSpecialFile(std::string path, Process *process,
@@ -53,6 +59,15 @@
 } else if (path.compare(0, 11, "/etc/passwd") == 0) {
 data = Linux::etcPasswd(process, tc);
 matched = true;
+} else if (path.compare(0, 15, "/proc/self/maps") == 0) {
+data = Linux::procSelfMaps(process, tc);
+matched = true;
+} else if (path.compare(0, 30, "/sys/devices/system/cpu/online") == 0)  
{

+data = Linux::cpuOnline(process, tc);
+matched = true;
+} else if (path.compare(0, 12 ,"/dev/urandom") == 0) {
+data = Linux::devRandom(process, tc);
+matched = true;
 }

 if (matched) {
@@ -85,3 +100,33 @@
 return csprintf("gem5-user:x:1000:1000:gem5-user,,,:%s:/bin/bash\n",
 process->tgtCwd);
 }
+
+std::string
+Linux::procSelfMaps(Process *process, ThreadContext *tc)
+{
+return process->memState->printVmaList();
+}
+
+std::string
+Linux::cpuOnline(Process *process, ThreadContext *tc)
+{
+return csprintf("0-%d\n",
+tc->getSystemPtr()->numContexts() - 1);
+}
+
+std::string
+Linux::devRandom(Process *process, ThreadContext *tc)
+{
+DPRINTFR(SyscallVerbose,
+ "%d: %s: open: generating urandom\n",
+ curTick(), tc->getCpuPtr()->name());
+
+std::stringstream line;
+int max = 1E5;
+for (int i = 0; i < max; i++) {
+uint8_t rand_uint = random.random(0, 255);
+
+line << rand_uint;
+}
+return line.str();
+}
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index 4b45b8b..5370e2b 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -29,10 +29,10 @@
 #ifndef __LINUX_HH__
 #define __LINUX_HH__

-#include "base/types.hh"
-
 #include 

+#include "base/random.hh"
+#include "base/types.hh"
 #include "kern/operatingsystem.hh"
 #include "sim/process.hh"

@@ -230,11 +230,16 @@
 int64_t ru_nivcsw;  //!< involuntary "
 };

+// For /dev/urandom accesses
+static Random random;
+
 static int openSpecialFile(std::string path, Process *process,
ThreadContext *tc);
 static std::string procMeminfo(Process *process, ThreadContext *tc);
 static std::string etcPasswd(Process *process, ThreadContext *tc);
+static std::string procSelfMaps(Process *process, ThreadContext *tc);
 static std::string cpuOnline(Process *process, ThreadContext *tc);
+static std::string devRandom(Process *process, ThreadContext *tc);

 // For futex system call
 static const unsigned TGT_FUTEX_WAIT= 0;
diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index a6177c3..42d3781 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -473,3 +473,20 @@

 return start;
 }
+
+std::string
+MemState::printVmaList()
+{
+std::stringstream file_content;
+
+for (auto vma : _vmaList) {
+std::stringstream line;
+line << std::hex << vma.start() << "-";
+line << std::hex << vma.end() << " ";
+line << "r-xp  00:00 0 ";
+line << "[" << vma.getName() << "]" << std::endl;
+file_content << line.str();
+}
+
+return file_content.str();
+}
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index 42823ce..1ca80da 100644
--- a/src/sim/mem_state.hh
+++

[gem5-dev] Change in gem5/gem5[develop]: arm: Optionally enable gem5 extended semihosting calls.

2020-03-25 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25947 )


Change subject: arm: Optionally enable gem5 extended semihosting calls.
..

arm: Optionally enable gem5 extended semihosting calls.

ARM's semihosting interface defines call numbers up to 0xff to be
for standardized use, and says that custom calls should go above this
number.

This new mechanism will let the caller decide whether it wants to
enable these extended calls, or if they should be ignored and only
standard calls should be recognized.

Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25947
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/semihosting.cc
M src/arch/arm/semihosting.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
4 files changed, 20 insertions(+), 10 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 5ea894a..b6db38a 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -154,9 +154,14 @@
 }

 void
-ArmSemihosting::call64(ThreadContext *tc)
+ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
 {
 RegVal op = tc->readIntReg(ArmISA::INTREG_X0 & mask(32));
+if (op > MaxStandardOp && !gem5_ops) {
+unrecognizedCall(
+tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
+return;
+}

 auto it = calls.find(op);
 if (it == calls.end()) {
@@ -173,9 +178,14 @@
 }

 void
-ArmSemihosting::call32(ThreadContext *tc)
+ArmSemihosting::call32(ThreadContext *tc, bool gem5_ops)
 {
 RegVal op = tc->readIntReg(ArmISA::INTREG_R0);
+if (op > MaxStandardOp && !gem5_ops) {
+unrecognizedCall(
+tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
+return;
+}

 auto it = calls.find(op);
 if (it == calls.end()) {
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index 4a8aa2b..9aa5b41 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -214,9 +214,9 @@
 ArmSemihosting(const ArmSemihostingParams *p);

 /** Perform an Arm Semihosting call from aarch64 code. */
-void call64(ThreadContext *tc);
+void call64(ThreadContext *tc, bool gem5_ops);
 /** Perform an Arm Semihosting call from aarch32 code. */
-void call32(ThreadContext *tc);
+void call32(ThreadContext *tc, bool gem5_ops);

   public: // SimObject and related interfaces
 void serialize(CheckpointOut ) const override;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 906cc9e..e61402a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -180,15 +180,15 @@
 }

 void
-ArmSystem::callSemihosting64(ThreadContext *tc)
+ArmSystem::callSemihosting64(ThreadContext *tc, bool gem5_ops)
 {
-getArmSystem(tc)->semihosting->call64(tc);
+getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
 }

 void
-ArmSystem::callSemihosting32(ThreadContext *tc)
+ArmSystem::callSemihosting32(ThreadContext *tc, bool gem5_ops)
 {
-getArmSystem(tc)->semihosting->call32(tc);
+getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
 }

 void
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index ae83da0..fc32d0f 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -314,10 +314,10 @@
 static bool haveSemihosting(ThreadContext *tc);

 /** Make a Semihosting call from aarch64 */
-static void callSemihosting64(ThreadContext *tc);
+static void callSemihosting64(ThreadContext *tc, bool gem5_ops=false);

 /** Make a Semihosting call from aarch32 */
-static void callSemihosting32(ThreadContext *tc);
+static void callSemihosting32(ThreadContext *tc, bool gem5_ops=false);

 /** Make a call to notify the power controller of STANDBYWFI assertion  
*/

 static void callSetStandByWfi(ThreadContext *tc);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
Gerrit-Change-Number: 25947
Gerrit-PatchSet: 14
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Chun-Chen TK Hsu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Switch to new MemState API

2020-03-25 Thread Matthew Poremba (Gerrit) 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25366 )


Change subject: sim-se: Switch to new MemState API
..

sim-se: Switch to new MemState API

Switch over to the new MemState API by specifying memory regions for
stack in each ISA, changing brkFunc to use MemState for heap memory,
and calling the MemState fixup in fixupStackFault (renamed to just
fixupFault).

Change-Id: Ie3559a68ce476daedf1a3f28b168a8fbc7face5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25366
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/process.cc
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/riscv/process.cc
M src/arch/riscv/tlb.cc
M src/arch/sparc/faults.cc
M src/arch/sparc/process.cc
M src/arch/x86/faults.cc
M src/arch/x86/process.cc
M src/arch/x86/pseudo_inst.cc
M src/arch/x86/tlb.cc
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/gpu_tlb.cc
M src/mem/se_translating_port_proxy.cc
M src/sim/faults.cc
M src/sim/process.cc
M src/sim/process.hh
M src/sim/syscall_emul.cc
18 files changed, 32 insertions(+), 80 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index c672444..12003f8 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -371,8 +371,8 @@
 memState->setStackSize(memState->getStackBase() -  
memState->getStackMin());


 // map memory
-allocateMem(roundDown(memState->getStackMin(), pageSize),
-  roundUp(memState->getStackSize(), pageSize));
+memState->mapRegion(roundDown(memState->getStackMin(), pageSize),
+roundUp(memState->getStackSize(),  
pageSize), "stack");


 // map out initial stack contents
 IntType sentry_base = memState->getStackBase() - sentry_size;
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index a610fbe..3e7b378 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -151,8 +151,8 @@
 memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
 memState->setStackSize(memState->getStackBase() -  
memState->getStackMin());

 // map memory
-allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(),
-pageSize));
+memState->mapRegion(memState->getStackMin(),
+roundUp(memState->getStackSize(),  
pageSize), "stack");


 // map out initial stack contents; leave room for argc
 IntType argv_array_base = memState->getStackMin() + intSize;
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 5cb9823..914c99f 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -200,8 +200,8 @@
 memState->setStackSize(memState->getStackBase() - stack_min);

 // map memory
-allocateMem(roundDown(stack_min, pageSize),
-roundUp(memState->getStackSize(), pageSize));
+memState->mapRegion(roundDown(stack_min, pageSize),
+roundUp(memState->getStackSize(),  
pageSize), "stack");


 // map out initial stack contents
 uint32_t sentry_base = memState->getStackBase() - sentry_size;
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 474ed68..4026836 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -147,8 +147,8 @@
addrSize + 2 * sizeof(IntType) * auxv.size();
 stack_top &= -2*addrSize;
 memState->setStackSize(memState->getStackBase() - stack_top);
-allocateMem(roundDown(stack_top, pageSize),
-roundUp(memState->getStackSize(), pageSize));
+memState->mapRegion(roundDown(stack_top, pageSize),
+roundUp(memState->getStackSize(),  
pageSize), "stack");


 // Copy random bytes (for AT_RANDOM) to stack
 memState->setStackMin(memState->getStackMin() - RandomBytes);
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 1bf557a..ac4eca7 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -392,7 +392,7 @@

 if (!pte && mode != Execute) {
 // Check if we just need to grow the stack.
-if (process->fixupStackFault(vaddr)) {
+if (process->fixupFault(vaddr)) {
 // If we did, lookup the entry for the new page.
 pte = process->pTable->lookup(vaddr);
 }
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index dc68c01..4197613 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -683,7 +683,7 @@

 Process *p = tc->getProcessPtr();
 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
-if (!pte && p->fixupStackFault(vaddr))
+if (!pte && p->fixupFault(vaddr))
 pte = p->pTable->lookup(vaddr);
 panic_if(!pte, "Tried to access

[gem5-dev] Change in gem5/gem5[develop]: sim-se: Update mmap, munmap, mremap to use MemState

2020-03-25 Thread Matthew Poremba (Gerrit) 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26863 )


Change subject: sim-se: Update mmap, munmap, mremap to use MemState
..

sim-se: Update mmap, munmap, mremap to use MemState

This updates the syscalls for mmap, munmap, and mremap. The mmap
changes now create a virtual memory area through the MemState class
to allow for lazy allocation of mmapped regions. This provides
substantial performance boost for sparse usage of mmaps. The munmap
syscall is added to reclaim the virtual memory area reserved for the
mmapped region. The mremap syscall moves or resizes an mmapped region
and updates the corresponding virtual memory area region to keep the
page tables in sync.

Change-Id: Ide158e69cdff19bc81157e3e9826bcabc2a51140
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26863
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
2 files changed, 111 insertions(+), 116 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 08432e1..bffedfd 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -326,11 +326,22 @@


 SyscallReturn
-munmapFunc(SyscallDesc *desc, ThreadContext *tc)
+munmapFunc(SyscallDesc *desc, ThreadContext *tc, Addr start, size_t length)
 {
-// With mmap more fully implemented, it might be worthwhile to bite
-// the bullet and implement munmap. Should allow us to reuse simulated
-// memory.
+// Even if the system is currently not capable of recycling physical
+// pages, there is no reason we can't unmap them so that we trigger
+// appropriate seg faults when the application mistakenly tries to
+// access them again.
+auto p = tc->getProcessPtr();
+
+if (start & (tc->getSystemPtr()->getPageBytes() - 1) || !length) {
+return -EINVAL;
+}
+
+length = roundUp(length, tc->getSystemPtr()->getPageBytes());
+
+p->memState->unmapRegion(start, length);
+
 return 0;
 }

diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 8fc8994..1270855 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -165,7 +165,8 @@
   uint32_t offset_low, Addr result_ptr, int  
whence);


 /// Target munmap() handler.
-SyscallReturn munmapFunc(SyscallDesc *desc, ThreadContext *tc);
+SyscallReturn munmapFunc(SyscallDesc *desc, ThreadContext *tc, Addr start,
+ size_t length);

 /// Target shutdown() handler.
 SyscallReturn shutdownFunc(SyscallDesc *desc, ThreadContext *tc,
@@ -1112,32 +1113,32 @@
 Addr start, uint64_t old_length, uint64_t new_length, uint64_t  
flags,

 GuestABI::VarArgs varargs)
 {
-auto process = tc->getProcessPtr();
+auto p = tc->getProcessPtr();
+Addr page_bytes = tc->getSystemPtr()->getPageBytes();
 uint64_t provided_address = 0;
 bool use_provided_address = flags & OS::TGT_MREMAP_FIXED;

 if (use_provided_address)
 provided_address = varargs.get();

-if ((start % TheISA::PageBytes != 0) ||
-(provided_address % TheISA::PageBytes != 0)) {
+if ((start % page_bytes != 0) ||
+(provided_address % page_bytes != 0)) {
 warn("mremap failing: arguments not page aligned");
 return -EINVAL;
 }

-new_length = roundUp(new_length, TheISA::PageBytes);
+new_length = roundUp(new_length, page_bytes);

 if (new_length > old_length) {
-std::shared_ptr mem_state = process->memState;
-Addr mmap_end = mem_state->getMmapEnd();
+Addr mmap_end = p->memState->getMmapEnd();

 if ((start + old_length) == mmap_end &&
 (!use_provided_address || provided_address == start)) {
 // This case cannot occur when growing downward, as
 // start is greater than or equal to mmap_end.
 uint64_t diff = new_length - old_length;
-process->allocateMem(mmap_end, diff);
-mem_state->setMmapEnd(mmap_end + diff);
+p->memState->mapRegion(mmap_end, diff, "remapped");
+p->memState->setMmapEnd(mmap_end + diff);
 return start;
 } else {
 if (!use_provided_address && !(flags &  
OS::TGT_MREMAP_MAYMOVE)) {

@@ -1146,38 +1147,45 @@
 } else {
 uint64_t new_start = provided_address;
 if (!use_provided_address) {
-new_start = process->mmapGrowsDown() ?
+new_start = p->mmapGrowsDown() ?
 mmap_end - new_length : mmap_end;
-

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Don't use args and kwargs on attachIO

2020-03-25 Thread Giacomo Travaglini (Gerrit) 

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/27086

to review the following change.


Change subject: dev-arm: Don't use args and kwargs on attachIO
..

dev-arm: Don't use args and kwargs on attachIO

This is matching the attachOnChipIO style, and fixing the error of the
dma_ports kwarg being forwarded to the _attach_mem

Change-Id: Ib3ecf2fc18c488d938bbbf63eab3d7693cdb7d06
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/dev/arm/RealView.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index f9b9cb2..43d2b15 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -625,9 +625,9 @@
 if bridge:
 bridge.ranges = self._off_chip_ranges

-def attachIO(self, *args, **kwargs):
-self._attach_mem(self._off_chip_memory(), *args, **kwargs)
-self._attach_io(self._off_chip_devices(), *args, **kwargs)
+def attachIO(self, bus, dma_ports=None, mem_ports=None):
+self._attach_mem(self._off_chip_memory(), bus, mem_ports)
+self._attach_io(self._off_chip_devices(), bus, dma_ports)

 def setupBootLoader(self, cur_sys, boot_loader, atags_addr,  
load_offset):

 cur_sys.workload.boot_loader = boot_loader

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27086
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib3ecf2fc18c488d938bbbf63eab3d7693cdb7d06
Gerrit-Change-Number: 27086
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Extend MemState API to use VMAs

2020-03-25 Thread Matthew Poremba (Gerrit) 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25483 )


Change subject: sim-se: Extend MemState API to use VMAs
..

sim-se: Extend MemState API to use VMAs

Extend the MemState API to handle tracking dynamically sized memory
regions of a Process class which may be added, moved, removed, or
change in size during the course of simulation. This utilizes the
virtual memory areas (VMA) class to track individual regions and
provides a fixup method to handle physical page allocation in case of
a page fault. This allows for lazy allocation of the stack, heap, and
mmap regions of memory.

Change-Id: I3ef10657e5f8e8f0e328bdf0aa15a27b1dde39bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25483
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/process.cc
M src/arch/mips/process.cc
M src/arch/power/process.cc
M src/arch/riscv/process.cc
M src/arch/sparc/process.hh
M src/arch/x86/process.cc
M src/sim/SConscript
A src/sim/mem_state.cc
M src/sim/mem_state.hh
9 files changed, 647 insertions(+), 49 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 3d041ee..c672444 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -78,8 +78,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x4000L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end);
 }

 ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
@@ -92,8 +93,9 @@
 Addr next_thread_stack_base = stack_base - max_stack_size;
 Addr mmap_end = 0x40L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end);
 }

 void
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 539c7a5..a610fbe 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -67,8 +67,9 @@
 // Set up region for mmaps.  Start it 1GB above the top of the heap.
 Addr mmap_end = brk_point + 0x4000L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end);
 }

 void
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 9bb3b19..5cb9823 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -66,8 +66,9 @@
 // Set up region for mmaps. For now, start at bottom of kuseg space.
 Addr mmap_end = 0x7000L;

-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+ max_stack_size,  
next_thread_stack_base,

+ mmap_end);
 }

 void
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 5feff43..474ed68 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -73,8 +73,8 @@
 const Addr next_thread_stack_base = stack_base - max_stack_size;
 const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
 const Addr mmap_end = 0x4000L;
-memState = make_shared(brk_point, stack_base, max_stack_size,
-next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+max_stack_size, next_thread_stack_base, mmap_end);
 }

 RiscvProcess32::RiscvProcess32(ProcessParams *params, ObjectFile  
*objFile) :

@@ -85,8 +85,8 @@
 const Addr next_thread_stack_base = stack_base - max_stack_size;
 const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
 const Addr mmap_end = 0x4000L;
-memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+memState = make_shared(this, brk_point, stack_base,
+max_stack_size, next_thread_stack_base, mmap_end);
 }

 void
diff --git

[gem5-dev] Change in gem5/gem5[develop]: configs: Use ArmFsWorkload for Arm baremetal

2020-03-25 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26991 )


Change subject: configs: Use ArmFsWorkload for Arm baremetal
..

configs: Use ArmFsWorkload for Arm baremetal

Change-Id: Ie6bfdd9b30438bc6eaf22bc79dcc1690ffa039be
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26991
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M configs/common/FSConfig.py
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 3ae00ad..41b70d7 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -256,6 +256,7 @@
 if bare_metal:
 # EOT character on UART will end the simulation
 self.realview.uart[0].end_on_eot = True
+self.workload = ArmFsWorkload(atags_addr=0)
 else:
 workload = ArmFsLinux()


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6bfdd9b30438bc6eaf22bc79dcc1690ffa039be
Gerrit-Change-Number: 26991
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: IntrControl, clear all and check helpers

2020-03-25 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26809 )


Change subject: cpu: IntrControl, clear all and check helpers
..

cpu: IntrControl, clear all and check helpers

This patch extends the IntrControl to provided additional member
functions for (1) clearing all pending interrupts in a PE and (2)
checking for any pending interrupt in a PE. These are intended to
be used from interrupt management related peripherals.

Change-Id: I06b553872ed469e7449b872a0716865773ace154
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26809
Reviewed-by: Bobby R. Bruce 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/cpu/intr_control.cc
M src/cpu/intr_control.hh
2 files changed, 22 insertions(+), 6 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index 071b9d5..9274b37 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -47,18 +47,32 @@
 IntrControl::post(int cpu_id, int int_num, int index)
 {
 DPRINTF(IntrControl, "post  %d:%d (cpu %d)\n", int_num, index, cpu_id);
-std::vector  = sys->threadContexts;
-BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
-cpu->postInterrupt(tcvec[cpu_id]->threadId(), int_num, index);
+ThreadContext *tc = sys->getThreadContext(cpu_id);
+tc->getCpuPtr()->postInterrupt(tc->threadId(), int_num, index);
 }

 void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
 DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
-std::vector  = sys->threadContexts;
-BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
-cpu->clearInterrupt(tcvec[cpu_id]->threadId(), int_num, index);
+ThreadContext *tc = sys->getThreadContext(cpu_id);
+tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_num, index);
+}
+
+void
+IntrControl::clearAll(int cpu_id)
+{
+DPRINTF(IntrControl, "Clear all pending interrupts for CPU %d\n",  
cpu_id);

+ThreadContext *tc = sys->getThreadContext(cpu_id);
+tc->getCpuPtr()->clearInterrupts(tc->threadId());
+}
+
+bool
+IntrControl::havePosted(int cpu_id) const
+{
+DPRINTF(IntrControl, "Check pending interrupts for CPU %d\n", cpu_id);
+ThreadContext *tc = sys->getThreadContext(cpu_id);
+return tc->getCpuPtr()->checkInterrupts(tc);
 }

 IntrControl *
diff --git a/src/cpu/intr_control.hh b/src/cpu/intr_control.hh
index b7ff2a8..a6f025e 100644
--- a/src/cpu/intr_control.hh
+++ b/src/cpu/intr_control.hh
@@ -45,6 +45,8 @@

 void clear(int cpu_id, int int_num, int index);
 void post(int cpu_id, int int_num, int index);
+void clearAll(int cpu_id);
+bool havePosted(int cpu_id) const;

 void
 clear(int int_num, int index = 0)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I06b553872ed469e7449b872a0716865773ace154
Gerrit-Change-Number: 26809
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Enable Semihosting for baremetal.py

2020-03-25 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26993 )


Change subject: configs: Enable Semihosting for baremetal.py
..

configs: Enable Semihosting for baremetal.py

This is enabled via the --semihosting option

Change-Id: If6961cba8ec4a3aa22e788db6fe0ae54e169bb9c
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26993
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
---
M configs/example/arm/baremetal.py
1 file changed, 21 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index c691a7d..85ded9c 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -104,6 +104,14 @@

 MemConfig.config_mem(args, system)

+if args.semi_enable:
+system.semihosting = ArmSemihosting(
+stdin=args.semi_stdin,
+stdout=args.semi_stdout,
+stderr=args.semi_stderr,
+cmd_line = " ".join([ args.kernel ] + args.args)
+)
+
 # Add the PCI devices we need for this system. The base system
 # doesn't have any PCI devices by default since they are assumed
 # to be added by the configurastion scripts needin them.
@@ -203,7 +211,19 @@
 parser.add_argument("--restore", type=str, default=None)
 parser.add_argument("--dtb-gen", action="store_true",
 help="Doesn't run simulation, it generates a DTB  
only")

-
+parser.add_argument("--semi-enable", action="store_true",
+help="Enable semihosting support")
+parser.add_argument("--semi-stdin", type=str, default="stdin",
+help="Standard input for semihosting " \
+"(default: gem5's stdin)")
+parser.add_argument("--semi-stdout", type=str, default="stdout",
+help="Standard output for semihosting " \
+"(default: gem5's stdout)")
+parser.add_argument("--semi-stderr", type=str, default="stderr",
+help="Standard error for semihosting " \
+"(default: gem5's stderr)")
+parser.add_argument("args", default=[], nargs="*",
+help="Semihosting arguments to pass to benchmark")

 args = parser.parse_args()


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If6961cba8ec4a3aa22e788db6fe0ae54e169bb9c
Gerrit-Change-Number: 26993
Gerrit-PatchSet: 6
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Make --disk-image optional in baremetal.py

2020-03-25 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/26992 )


Change subject: configs: Make --disk-image optional in baremetal.py
..

configs: Make --disk-image optional in baremetal.py

Since the script could be used to run baremetal applications, we don't
have to enforce the presence of a disk image

Change-Id: I511515361cfd7a2e06ede0df3ddcc595de15f38b
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26992
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ciro Santilli 
Maintainer: Jason Lowe-Power 
---
M configs/example/arm/baremetal.py
1 file changed, 7 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Ciro Santilli: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index c162893..c691a7d 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017,2019 ARM Limited
+# Copyright (c) 2016-2017,2019-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -104,22 +104,23 @@

 MemConfig.config_mem(args, system)

-
 # Add the PCI devices we need for this system. The base system
 # doesn't have any PCI devices by default since they are assumed
 # to be added by the configurastion scripts needin them.
-system.pci_devices = [
+pci_devices = []
+if args.disk_image:
 # Create a VirtIO block device for the system's boot
 # disk. Attach the disk image using gem5's Copy-on-Write
 # functionality to avoid writing changes to the stored copy of
 # the disk image.
- 
PciVirtIO(vio=VirtIOBlock(image=create_cow_image(args.disk_image))),

-]
+system.disk = PciVirtIO(vio=VirtIOBlock(
+image=create_cow_image(args.disk_image)))
+pci_devices.append(system.disk)

 # Attach the PCI devices to the system. The helper method in the
 # system assigns a unique PCI bus ID to each of the devices and
 # connects them to the IO bus.
-for dev in system.pci_devices:
+for dev in pci_devices:
 system.attach_pci(dev)

 # Wire up the system's memory system

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I511515361cfd7a2e06ede0df3ddcc595de15f38b
Gerrit-Change-Number: 26992
Gerrit-PatchSet: 6
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Initialize atags_addr in baremetal.py

2020-03-25 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27023 )


Change subject: configs: Initialize atags_addr in baremetal.py
..

configs: Initialize atags_addr in baremetal.py

Change-Id: Iec797d4be607526d68a2813e188a32759418dbcc
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27023
Tested-by: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Ciro Santilli 
Maintainer: Jason Lowe-Power 
---
M configs/example/arm/baremetal.py
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Ciro Santilli: Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 85ded9c..1eb2a82 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -99,6 +99,7 @@
   platform=VExpress_GEM5_V2(),
   mem_mode=mem_mode,
   workload=ArmFsWorkload(
+  atags_addr=0,
   object_file=args.kernel),
   readfile=args.readfile)


--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iec797d4be607526d68a2813e188a32759418dbcc
Gerrit-Change-Number: 27023
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gem5 Cloud Project GCB service account  
<345032938...@cloudbuild.gserviceaccount.com>

Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove info dependency from stats storage

2020-03-25 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27083 )



Change subject: base: Remove info dependency from stats storage
..

base: Remove info dependency from stats storage

Info depends on the storage type, not the other way around.

Change-Id: Ie3deca17b859a217c0c7bd833c017d9436eee4b0
Signed-off-by: Daniel R. Carvalho 
---
M src/base/statistics.hh
M src/base/stats/SConscript
M src/base/stats/info.hh
M src/base/stats/storage.hh
M src/base/stats/storage.test.cc
M src/base/stats/types.hh
6 files changed, 116 insertions(+), 157 deletions(-)



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 7c1d854..2447615 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -410,7 +410,7 @@

 size_t size = self.size();
 for (off_type i = 0; i < size; ++i)
-self.data(i)->prepare(info);
+self.data(i)->prepare(info->storageParams);
 }

 void
@@ -421,7 +421,7 @@

 size_t size = self.size();
 for (off_type i = 0; i < size; ++i)
-self.data(i)->reset(info);
+self.data(i)->reset(info->storageParams);
 }
 };

@@ -520,7 +520,7 @@
 void
 doInit()
 {
-new (storage) Storage(this->info());
+new (storage) Storage(this->info()->storageParams);
 this->setInit();
 }

@@ -595,8 +595,8 @@

 bool zero() { return result() == 0.0; }

-void reset() { data()->reset(this->info()); }
-void prepare() { data()->prepare(this->info()); }
+void reset() { data()->reset(this->info()->storageParams); }
+void prepare() { data()->prepare(this->info()->storageParams); }
 };

 class ProxyInfo : public ScalarInfo
@@ -897,7 +897,7 @@
 storage = reinterpret_cast(ptr);

 for (off_type i = 0; i < _size; ++i)
-new ([i]) Storage(this->info());
+new ([i]) Storage(this->info()->storageParams);

 this->setInit();
 }
@@ -1132,7 +1132,7 @@
 storage = reinterpret_cast(ptr);

 for (off_type i = 0; i < _size; ++i)
-new ([i]) Storage(info);
+new ([i]) Storage(info->storageParams);

 this->setInit();

@@ -1180,7 +1180,7 @@
 size_type size = this->size();

 for (off_type i = 0; i < size; ++i)
-data(i)->prepare(info);
+data(i)->prepare(info->storageParams);

 info->cvec.resize(size);
 for (off_type i = 0; i < size; ++i)
@@ -1196,7 +1196,7 @@
 Info *info = this->info();
 size_type size = this->size();
 for (off_type i = 0; i < size; ++i)
-data(i)->reset(info);
+data(i)->reset(info->storageParams);
 }

 bool
@@ -1252,7 +1252,7 @@
 void
 doInit()
 {
-new (storage) Storage(this->info());
+new (storage) Storage(this->info()->storageParams);
 this->setInit();
 }

@@ -1286,7 +1286,7 @@
 prepare()
 {
 Info *info = this->info();
-data()->prepare(info, info->data);
+data()->prepare(info->storageParams, info->data);
 }

 /**
@@ -1295,7 +1295,7 @@
 void
 reset()
 {
-data()->reset(this->info());
+data()->reset(this->info()->storageParams);
 }

 /**
@@ -1347,7 +1347,7 @@

 Info *info = this->info();
 for (off_type i = 0; i < _size; ++i)
-new ([i]) Storage(info);
+new ([i]) Storage(info->storageParams);

 this->setInit();
 }
@@ -1396,7 +1396,7 @@
 size_type size = this->size();
 info->data.resize(size);
 for (off_type i = 0; i < size; ++i)
-data(i)->prepare(info, info->data[i]);
+data(i)->prepare(info->storageParams, info->data[i]);
 }

 bool
@@ -2217,7 +2217,7 @@
 void
 doInit()
 {
-new (storage) Storage(this->info());
+new (storage) Storage(this->info()->storageParams);
 this->setInit();
 }

@@ -2251,7 +2251,7 @@
 prepare()
 {
 Info *info = this->info();
-data()->prepare(info, info->data);
+data()->prepare(info->storageParams, info->data);
 }

 /**
@@ -2260,7 +2260,7 @@
 void
 reset()
 {
-data()->reset(this->info());
+data()->reset(this->info()->storageParams);
 }
 };

diff --git a/src/base/stats/SConscript b/src/base/stats/SConscript
index fe9e385..79f3691 100644
--- a/src/base/stats/SConscript
+++ b/src/base/stats/SConscript
@@ -35,5 +35,4 @@
 if env['USE_HDF5']:
 Source('hdf5.cc', append={'CXXFLAGS': '-Wno-deprecated-copy'})

-GTest('storage.test', 'storage.test.cc', '../debug.cc', '../str.cc', 'info.cc',
-'storage.cc')
+GTest('storage.test', 'storage.test.cc', 'storage.cc')
diff --git a/src/base/stats/info.hh b/src/base/stats/info.hh
index ad34b39..d07a64b 100644
--- a/src/base/stats/info.hh
+++ b/src/base/stats/info.hh
@@ -170,26

[gem5-dev] Change in gem5/gem5[develop]: base: Use std vector in vector stats

2020-03-25 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27085 )



Change subject: base: Use std vector in vector stats
..

base: Use std vector in vector stats

Use std::vector in vector based stats to avoid data management.

Change-Id: I6b341f03e4861a5b8f80fa8741373065b7c755bf
Signed-off-by: Daniel R. Carvalho 
---
M src/base/statistics.hh
1 file changed, 41 insertions(+), 70 deletions(-)



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index c3f7ebc..89e80b2 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2020 Inria
  * Copyright (c) 2019 Arm Limited
  * All rights reserved.
  *
@@ -72,14 +73,15 @@
 #include 
 #include 

+#include "base/cast.hh"
+#include "base/cprintf.hh"
+#include "base/intmath.hh"
+#include "base/logging.hh"
 #include "base/stats/group.hh"
 #include "base/stats/info.hh"
 #include "base/stats/output.hh"
 #include "base/stats/storage.hh"
 #include "base/stats/types.hh"
-#include "base/cast.hh"
-#include "base/cprintf.hh"
-#include "base/intmath.hh"
 #include "base/str.hh"
 #include "base/types.hh"

@@ -865,8 +867,7 @@

   protected:
 /** The storage of this stat. */
-Storage *storage;
-size_type _size;
+std::vector storage;

   protected:
 /**
@@ -874,28 +875,22 @@
  * @param index The vector index to access.
  * @return The storage object at the given index.
  */
-Storage *data(off_type index) { return [index]; }
+Storage *data(off_type index) { return storage[index]; }

 /**
  * Retrieve a const pointer to the storage.
  * @param index The vector index to access.
  * @return A const pointer to the storage object at the given index.
  */
-const Storage *data(off_type index) const { return [index]; }
+const Storage *data(off_type index) const { return storage[index]; }

 void
 doInit(size_type s)
 {
-assert(s > 0 && "size must be positive!");
-assert(!storage && "already initialized");
-_size = s;
+fatal_if(s <= 0, "Storage size must be positive");
+fatal_if(check(), "Stat has already been initialized");

-char *ptr = new char[_size * sizeof(Storage)];
-storage = reinterpret_cast(ptr);
-
-for (off_type i = 0; i < _size; ++i)
-new ([i]) Storage(this->info()->storageParams);
-
+storage.resize(s, new Storage(this->info()->storageParams));
 this->setInit();
 }

@@ -936,7 +931,7 @@
 /**
  * @return the number of elements in this vector.
  */
-size_type size() const { return _size; }
+size_type size() const { return storage.size(); }

 bool
 zero() const
@@ -950,23 +945,20 @@
 bool
 check() const
 {
-return storage != NULL;
+return size() > 0;
 }

   public:
 VectorBase(Group *parent, const char *name, const char *desc)
 : DataWrapVec(parent, name, desc),
-  storage(nullptr), _size(0)
+  storage()
 {}

 ~VectorBase()
 {
-if (!storage)
-return;
-
-for (off_type i = 0; i < _size; ++i)
-data(i)->~Storage();
-delete [] reinterpret_cast(storage);
+for (auto& stor : storage) {
+delete stor;
+}
 }

 /**
@@ -1087,34 +1079,30 @@
   protected:
 size_type x;
 size_type y;
-size_type _size;
-Storage *storage;
+std::vector storage;

   protected:
-Storage *data(off_type index) { return [index]; }
-const Storage *data(off_type index) const { return [index]; }
+Storage *data(off_type index) { return storage[index]; }
+const Storage *data(off_type index) const { return storage[index]; }

   public:
 Vector2dBase(Group *parent, const char *name, const char *desc)
 : DataWrapVec2d(parent, name, desc),
-  x(0), y(0), _size(0), storage(nullptr)
+  x(0), y(0), storage()
 {}

 ~Vector2dBase()
 {
-if (!storage)
-return;
-
-for (off_type i = 0; i < _size; ++i)
-data(i)->~Storage();
-delete [] reinterpret_cast(storage);
+for (auto& stor : storage) {
+delete stor;
+}
 }

 Derived &
 init(size_type _x, size_type _y)
 {
-assert(_x > 0 && _y > 0 && "sizes must be positive!");
-assert(!storage && "already initialized");
+fatal_if((_x <= 0) || (_y <= 0), "Storage sizes must be positive");
+fatal_if(check(), "Stat has already been initialized");

 Derived  = this->self();
 Info *info = this->info();
@@ -1123,14 +,8 @@
 y = _y;
 info->x = _x;
 info->y = _y;
-_size = x * y;

-char *ptr = new char[_size * sizeof(Storage)];
-storage = reinterpret_cast(ptr);
-
-for (off_type i = 0; i < _size; ++i)
-new

[gem5-dev] Change in gem5/gem5[develop]: base: Make read-only functions const in ScalarBase

2020-03-25 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27084 )



Change subject: base: Make read-only functions const in ScalarBase
..

base: Make read-only functions const in ScalarBase

These functions do not need to modify their storage's contents.

ScalarBase's non-const value() has been removed.

Change-Id: I4dd3899a29a741a7d8cd199ccd254b346d86ae07
Signed-off-by: Daniel R. Carvalho 
---
M src/base/statistics.hh
1 file changed, 8 insertions(+), 11 deletions(-)



diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 2447615..c3f7ebc 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -525,13 +525,6 @@
 }

   public:
-/**
- * Return the current value of this stat as its base type.
- * @return The current value.
- */
-Counter value() const { return data()->value(); }
-
-  public:
 ScalarBase(Group *parent = nullptr, const char *name = nullptr,
const char *desc = nullptr)
 : DataWrap(parent, name, desc)
@@ -587,13 +580,17 @@
  */
 size_type size() const { return 1; }

-Counter value() { return data()->value(); }
+/**
+ * Return the current value of this stat as its base type.
+ * @return The current value.
+ */
+Counter value() const { return data()->value(); }

-Result result() { return data()->result(); }
+Result result() const { return data()->result(); }

-Result total() { return result(); }
+Result total() const { return result(); }

-bool zero() { return result() == 0.0; }
+bool zero() const { return result() == 0.0; }

 void reset() { data()->reset(this->info()->storageParams); }
 void prepare() { data()->prepare(this->info()->storageParams); }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27084
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4dd3899a29a741a7d8cd199ccd254b346d86ae07
Gerrit-Change-Number: 27084
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho 
Gerrit-MessageType: newchange
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