[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix Ruby handling of functional requests
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22022 )
Change subject: mem-ruby: Fix Ruby handling of functional requests
..
mem-ruby: Fix Ruby handling of functional requests
This patch addresses multiple cases:
- When a controller has read/write permissions while others have read
only permissions, the one with r/w permissions performs the read as
the others may have stale data
- When controllers only have lines with stale or busy access permissions,
a valid copy of the line may be in a message in transit in the network
or in a message buffer (not seen by the controller yet). In this case,
we forward the functional request accordingly.
- Sequencer messages should not accept functional reads
- Functional writes also update the packet data on the sequencer
outstanding request lists and the cpu-side response queue.
Change-Id: I6b0656f1a2b81d41bdcf6c783dfa522a77393981
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22022
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Tested-by: kokoro
Reviewed-by: John Alsop
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/RubyRequest.cc
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/RubySystem.cc
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
M src/mem/slicc/symbols/StateMachine.py
9 files changed, 208 insertions(+), 25 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
John Alsop: Looks good to me, but someone else must approve
kokoro: Regressions pass
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 8e17f98..08d30cf 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -291,7 +303,7 @@
MessageSizeType MessageSize, default="MessageSizeType_Request_Control";
bool functionalRead(Packet *pkt) {
-return testAndRead(PhysicalAddress, DataBlk, pkt);
+return false;
}
bool functionalWrite(Packet *pkt) {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 48f9618..15aff12 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -62,6 +62,7 @@
class Network;
class GPUCoalescer;
+class DMASequencer;
// used to communicate that an in_port peeked the wrong message type
class RejectException: public std::exception
@@ -101,6 +102,7 @@
virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
virtual Sequencer* getCPUSequencer() const = 0;
+virtual DMASequencer* getDMASequencer() const = 0;
virtual GPUCoalescer* getGPUCoalescer() const = 0;
// This latency is used by the sequencer when enqueueing requests.
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc
b/src/mem/ruby/slicc_interface/RubyRequest.cc
index dd26ad6..f30bde5 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2011 Mark D. Hill and David A. Wood
* All rights
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow MessageBuffer functional reads
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22019 )
Change subject: mem-ruby: Allow MessageBuffer functional reads
..
mem-ruby: Allow MessageBuffer functional reads
Valid lines withing unhandled messages may need to be checked when the
line is in a transient state.
Change-Id: I433e9bb960680348c25bf19ace2d405109380241
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22019
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
2 files changed, 53 insertions(+), 11 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index f8cab3c..f5562dc 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -438,17 +450,21 @@
}
uint32_t
-MessageBuffer::functionalWrite(Packet *pkt)
+MessageBuffer::functionalAccess(Packet *pkt, bool is_read)
{
-uint32_t num_functional_writes = 0;
+DPRINTF(RubyQueue, "functional %s for %#x\n",
+is_read ? "read" : "write", pkt->getAddr());
+
+uint32_t num_functional_accesses = 0;
// Check the priority heap and write any messages that may
// correspond to the address in the packet.
for (unsigned int i = 0; i < m_prio_heap.size(); ++i) {
Message *msg = m_prio_heap[i].get();
-if (msg->functionalWrite(pkt)) {
-num_functional_writes++;
-}
+if (is_read && msg->functionalRead(pkt))
+return 1;
+else if (!is_read && msg->functionalWrite(pkt))
+num_functional_accesses++;
}
// Check the stall queue and write any messages that may
@@ -461,13 +477,14 @@
it != (map_iter->second).end(); ++it) {
Message *msg = (*it).get();
-if (msg->functionalWrite(pkt)) {
-num_functional_writes++;
-}
+if (is_read && msg->functionalRead(pkt))
+return 1;
+else if (!is_read && msg->functionalWrite(pkt))
+num_functional_accesses++;
}
}
-return num_functional_writes;
+return num_functional_accesses;
}
MessageBuffer *
diff --git a/src/mem/ruby/network/MessageBuffer.hh
b/src/mem/ruby/network/MessageBuffer.hh
index f92d565..0e11529 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -133,12 +145,25 @@
// Function for figuring out if any of the messages in the buffer need
// to be updated with the data from the packet.
// Return value indicates the number of messages that were updated.
-// This required for debugging the code.
-uint32_t functionalWrite(Packet *pkt);
+uint32_t functionalWrite(Packet *pkt)
+{
+return functionalAccess(pkt, false);
+}
+
+// Function for figuring if message in the buffer has valid data for
+// the packet.
+// Returns true only if a message was found with valid data and the
+// read was performed.
+bool functionalRead(Packet *pkt)
+{
+return functionalAccess(pkt, true) == 1;
+}
private:
void reanalyzeList(std::list &, Tick);
+
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add functionalReadBuffers to AbstractController
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22020 )
Change subject: mem-ruby: Add functionalReadBuffers to AbstractController
..
mem-ruby: Add functionalReadBuffers to AbstractController
Forwards a functional read accesses to all message buffers, similar to
functionalWriteBuffers.
Change-Id: I54b0ba16aab84575e4c9d6102f6c519b309aa95b
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22020
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 37 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bradford Beckmann: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 1c34bde..48f9618 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -112,6 +112,7 @@
//! These functions are used by ruby system to read/write the data
blocks
//! that exist with in the controller.
+virtual bool functionalReadBuffers(PacketPtr&) = 0;
virtual void functionalRead(const Addr , PacketPtr) = 0;
void functionalMemoryRead(PacketPtr);
//! The return value indicates the number of messages written with the
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 0e336e6..ee6b5fb 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# Copyright (c) 2013 Advanced Micro Devices, Inc.
@@ -313,6 +325,7 @@
Sequencer* getCPUSequencer() const;
GPUCoalescer* getGPUCoalescer() const;
+bool functionalReadBuffers(PacketPtr&);
int functionalWriteBuffers(PacketPtr&);
void countTransition(${ident}_State state, ${ident}_Event event);
@@ -1041,6 +1054,29 @@
}
''')
+# Function for functional reads to messages buffered in the
controller
+code('''
+bool
+$c_ident::functionalReadBuffers(PacketPtr& pkt)
+{
+''')
+for var in self.objects:
+vtype = var.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt)) return true;')
+
+for var in self.config_parameters:
+vtype = var.type_ast.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt)) return true;')
+
+code('''
+return false;
+}
+''')
+
code.write(path, "%s.cc" % c_ident)
def printCWakeup(self, path, includes):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I54b0ba16aab84575e4c9d6102f6c519b309aa95b
Gerrit-Change-Number: 22020
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: SimpleNetwork implementation of functional reads
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/22021 )
Change subject: mem-ruby: SimpleNetwork implementation of functional reads
..
mem-ruby: SimpleNetwork implementation of functional reads
Change-Id: Id362d992cbf178f15294f0a5e9060a1de2beb394
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22021
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
2 files changed, 33 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 51d4dae..84817e4 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -178,9 +190,12 @@
SimpleNetwork::functionalRead(Packet *pkt)
{
for (unsigned int i = 0; i < m_switches.size(); i++) {
-if (m_switches[i]->functionalRead(pkt)) {
+if (m_switches[i]->functionalRead(pkt))
return true;
-}
+}
+for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
+if (m_int_link_buffers[i]->functionalRead(pkt))
+return true;
}
return false;
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index 71b6636..d1e5026 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -1,5 +1,17 @@
/*
* Copyright (c) 2020 Inria
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -154,6 +166,10 @@
bool
Switch::functionalRead(Packet *pkt)
{
+for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
+if (m_port_buffers[i]->functionalRead(pkt))
+return true;
+}
return false;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id362d992cbf178f15294f0a5e9060a1de2beb394
Gerrit-Change-Number: 22021
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28067
to review the following change.
Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture
..
tests: Refactor the Gem5Fixture to derive from UniqueFixture
Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb
---
M tests/gem5/fixture.py
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index aa316e7..db14115 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -159,6 +159,8 @@
log_call(log.test_log, command, stderr=sys.stderr)
class Gem5Fixture(SConsFixture):
+fixtures = {}
+
def __new__(cls, isa, variant, protocol=None):
target_dir = joinpath(config.build_dir, isa.upper())
if protocol:
--
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Gerrit-Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb
Gerrit-Change-Number: 28067
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base,misc: Added version to code
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27787 )
Change subject: base,misc: Added version to code
..
base,misc: Added version to code
This version ID string can be accessed from elsewhere in the CPP
codebase using `extern const char *gem5Version;`. The python variable
"gem5Version" may be accessed in by importing the generated
"defines.py". When gem5 now runs it will output the version
currently being used to the CLI.
Change-Id: I4feb6b7317cd2922c56eb8ce3e532b0bfa0e6ed3
Issue-on: https://gem5.atlassian.net/browse/GEM5-411
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27787
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/SConscript
M src/base/SConscript
A src/base/version.cc
M src/python/m5/main.py
M src/python/pybind11/core.cc
M tests/gem5/verifier.py
6 files changed, 36 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index 90f9b76..c7251fc 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -830,6 +830,7 @@
buildEnv = m5.util.SmartDict($build_env)
compileDate = _m5.core.compileDate
+gem5Version = _m5.core.gem5Version
_globals = globals()
for key,val in _m5.core.__dict__.items():
if key.startswith('flag_'):
diff --git a/src/base/SConscript b/src/base/SConscript
index f2fb91c..fe4e361 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -73,6 +73,7 @@
Source('str.cc')
GTest('str.test', 'str.test.cc', 'str.cc')
Source('time.cc')
+Source('version.cc')
Source('trace.cc')
GTest('trie.test', 'trie.test.cc')
Source('types.cc')
diff --git a/src/base/version.cc b/src/base/version.cc
new file mode 100644
index 000..7182b55
--- /dev/null
+++ b/src/base/version.cc
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020 The Regents of The University of California
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+const char *gem5Version = "[develop]";
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 82ef4d9..6fe9218 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -273,6 +273,7 @@
done = True
print('Build information:')
print()
+print('gem5 version %s' % defines.gem5Version)
print('compiled %s' % defines.compileDate)
print('build options:')
keys = list(defines.buildEnv.keys())
@@ -336,6 +337,7 @@
print(brief_copyright)
print()
+print("gem5 version %s" % defines.gem5Version)
print("gem5 compiled %s" % defines.compileDate)
print("gem5 started %s" %
diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc
index 4b7defe..8655d73 100644
--- a/src/python/pybind11/core.cc
+++ b/src/python/pybind11/core.cc
@@ -79,6 +79,7 @@
}
extern const char *compileDate;
+extern const char *gem5Version;
#ifdef DEBUG
const bool flag_DEBUG = true;
@@ -260,6 +261,7 @@
/* TODO: These should be read-only */
m_core.attr("compileDate") = py::cast(compileDate);
+m_core.attr("gem5Version") = py::cast(gem5Version);
m_core.attr("flag_DEBUG") = py::cast(flag_DEBUG);
m_core.attr("flag_DEBUG") = py::cast(flag_DEBUG);
diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py
index a7e6d4e..73a7499 100644
--- a/tests/gem5/verifier.py
+++ b/tests/gem5/verifier.py
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fix for ruby latency
Juan Manuel Cebrián González has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28053 )
Change subject: mem-ruby: Fix for ruby latency
..
mem-ruby: Fix for ruby latency
The classic memory model clears L1 hits instantaneously and sets the 'when'
to curTick + hit_latency. Ruby models however advance the curTick instead.
Therefore the legacy '+1' adds an additional cycle to ruby L1 cache hits.
This causes significantly more front-end stalls of the o3 cpu when compared
to real Intel hardware. By applying this fix both performance and
simulation time are improved by around 30%. Front-end stalls look much
closer to real hardware with this fix.
Change-Id: I4c91dc09bff5f45f1d1e42edc13d3c15d6205c46
---
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/request.hh
M src/mem/ruby/system/Sequencer.cc
4 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index dd1ba3d..60b1889 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -148,12 +148,18 @@
// either the packet list is empty or this has to be inserted
// before every other packet
transmitList.emplace_front(when, pkt);
-schedSendEvent(when);
+schedSendEvent(when,pkt);
}
void
PacketQueue::schedSendEvent(Tick when)
{
+schedSendEvent(when,NULL);
+}
+
+void
+PacketQueue::schedSendEvent(Tick when, PacketPtr pkt)
+{
// if we are waiting on a retry just hold off
if (waitingOnRetry) {
DPRINTF(PacketQueue, "Not scheduling send as waiting for retry\n");
@@ -162,10 +168,20 @@
}
if (when != MaxTick) {
+// The classic memory model clears L1 hits instantaneously and
+// sets the 'when' to curTick + hit_latency. Ruby models however
+// advance the curTick instead. Therefore the legacy '+1' adds an
+// additional cycle to ruby L1 cache hits.
// we cannot go back in time, and to be consistent we stick to
// one tick in the future
-when = std::max(when, curTick() + 1);
+Tick initWhen = when;
+when = std::max(initWhen, curTick() + 1);
// @todo Revisit the +1
+if (pkt != NULL) {
+ if (pkt->req->wasHandledByRuby()) {
+when = std::max(initWhen, curTick());
+ }
+}
if (!sendEvent.scheduled()) {
em.schedule(, when);
diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh
index b9c5b75..bac4db2 100644
--- a/src/mem/packet_queue.hh
+++ b/src/mem/packet_queue.hh
@@ -194,6 +194,12 @@
*
* @param when time to schedule an event
*/
+void schedSendEvent(Tick when, PacketPtr pkt);
+
+/**
+ * Wrapper for old schedSendEvent
+ * @param when time to schedule an event
+ */
void schedSendEvent(Tick when);
/**
diff --git a/src/mem/request.hh b/src/mem/request.hh
index aca9fe8..b127a4a 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -251,6 +251,9 @@
ARG_SEGMENT= 0x0800,
};
+/* Flag set when a packet passes through Ruby */
+bool handledByRuby;
+
private:
typedef uint16_t PrivateFlagsType;
typedef ::Flags PrivateFlags;
@@ -299,6 +302,7 @@
privateFlags.set(VALID_PADDR|VALID_SIZE);
depth = 0;
accessDelta = 0;
+handledByRuby = false;
//translateDelta = 0;
}
@@ -399,7 +403,7 @@
_extraData(0), _contextId(0), _pc(0),
_reqInstSeqNum(0), atomicOpFunctor(nullptr), translateDelta(0),
accessDelta(0), depth(0)
-{}
+{ handledByRuby = false; }
Request(Addr paddr, unsigned size, Flags flags, MasterID mid,
InstSeqNum seq_num, ContextID cid)
@@ -540,6 +544,7 @@
accessDelta = 0;
translateDelta = 0;
atomicOpFunctor = std::move(amo_op);
+handledByRuby = false;
}
/**
@@ -908,6 +913,8 @@
bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
bool isAtomicNoReturn() const { return
_flags.isSet(ATOMIC_NO_RETURN_OP); }
+bool wasHandledByRuby() const { return handledByRuby; };
+
bool
isAtomic() const
{
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index a90523e..4f1ba2a 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -520,6 +520,8 @@
return RequestStatus_BufferFull;
}
+pkt->req->handledByRuby = true;
+
RubyRequestType primary_type = RubyRequestType_NULL;
RubyRequestType secondary_type = RubyRequestType_NULL;
--
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Gerrit-Change-Id:
[gem5-dev] Change in gem5/gem5[master]: arch-x86,cpu-o3: Replace M5_UNREACHABLE definition for X86.
Juan Manuel Cebrián González has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28052 )
Change subject: arch-x86,cpu-o3: Replace M5_UNREACHABLE definition for X86.
..
arch-x86,cpu-o3: Replace M5_UNREACHABLE definition for X86.
Now it generates an unknown instruction instead of an exception.
This exception was not handled by the simulator and crashes it.
This situation is triggered when running deep into a mis-speculated data
path when the simulator tries to decode random data from memory.
By generating this instruction we give time to the simulator to squash the
pipeline when it realizes the wrong data path.
Change-Id: Ie552cfc6ca90e4319e7d17553086e6efae989905
---
M src/arch/isa_parser.py
M src/base/compiler.hh
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 7f09b16..f5662dd 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -2314,8 +2314,12 @@
codeObj = t[3]
# just wrap the decoding code from the block as a case in the
# outer switch statement.
-codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
- 'M5_UNREACHABLE;\n')
+if (self.isa_name == "X86ISA"):
+codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
+ 'M5_X86_UNREACHABLE;\n')
+else:
+codeObj.wrap_decode_block('\n%s\n' % ''.join(case_list),
+ 'M5_UNREACHABLE;\n')
codeObj.has_decode_default = (case_list == ['default:'])
t[0] = codeObj
diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 957ef40..b08f4b0 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -56,6 +56,7 @@
# define M5_DEPRECATED __attribute__((deprecated))
# define M5_DEPRECATED_MSG(MSG) __attribute__((deprecated(MSG)))
# define M5_UNREACHABLE __builtin_unreachable()
+# define M5_X86_UNREACHABLE return new Unknown(machInst)
# define M5_PUBLIC __attribute__ ((visibility ("default")))
# define M5_LOCAL __attribute__ ((visibility ("hidden")))
#endif
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie552cfc6ca90e4319e7d17553086e6efae989905
Gerrit-Change-Number: 28052
Gerrit-PatchSet: 1
Gerrit-Owner: Juan Manuel Cebrián González
Gerrit-MessageType: newchange
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[gem5-dev] Re: [gem5-users] [NOTICE] Mailing lists successfully migrated!
Thanks, Bobby! To everyone: In the past few months, we've had many reports of "missing" emails where emails sent to gem5-users or gem5-dev were only received by some people on the list. If you notice this happening again, please let us know ASAP so we can look into it on the new mail server. Cheers, Jason On Tue, Apr 21, 2020 at 6:38 PM Bobby Bruce via gem5-users < gem5-us...@gem5.org> wrote: > Dear all, > > Thank you for your patience. If you have received this email it means our > mailing lists have been successfully migrated. You should experience no > change in service; please continue use the mailing lists as you have done > so before. > > Kind regards, > Bobby > -- > Dr. Bobby R. Bruce > Room 2235, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > ___ > gem5-users mailing list -- gem5-us...@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Creation of PowerState class
Hello Andreas Sandberg, Anouk Van Laer,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28049
to review the following change.
Change subject: sim-power: Creation of PowerState class
..
sim-power: Creation of PowerState class
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.
Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg
Reviewed-by: Sascha Bischoff
Signed-off-by: Nikos Nikoleris
---
M configs/example/arm/fs_power.py
M src/cpu/base.cc
M src/dev/arm/fvp_base_pwr_ctrl.cc
M src/sim/ClockedObject.py
A src/sim/PowerState.py
M src/sim/SConscript
M src/sim/clocked_object.cc
M src/sim/clocked_object.hh
M src/sim/power/power_model.cc
A src/sim/power_state.cc
A src/sim/power_state.hh
11 files changed, 432 insertions(+), 231 deletions(-)
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index abc759e..72c6292 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -114,7 +114,7 @@
if not isinstance(cpu, m5.objects.BaseCPU):
continue
-cpu.default_p_state = "ON"
+cpu.power_state.default_state = "ON"
cpu.power_model = CpuPowerModel(cpu.path())
# Example power model for the L2 Cache of the bigCluster
@@ -122,7 +122,7 @@
if not isinstance(l2, m5.objects.Cache):
continue
-l2.default_p_state = "ON"
+l2.power_state.default_state = "ON"
l2.power_model = L2PowerModel(l2.path())
bL.instantiate(options)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index c0788db..493f08b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -329,11 +329,11 @@
}
if (_switchedOut)
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
// Assumption CPU start to operate instantaneously without any latency
-if (ClockedObject::pwrState() == Enums::PwrState::UNDEFINED)
-ClockedObject::pwrState(Enums::PwrState::ON);
+if (powerState->get() == Enums::PwrState::UNDEFINED)
+powerState->set(Enums::PwrState::ON);
}
@@ -463,7 +463,7 @@
return;
}
-if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED &&
+if (powerState->get() == Enums::PwrState::CLK_GATED &&
powerGatingOnIdle) {
assert(!enterPwrGatingEvent.scheduled());
// Schedule a power gating event when clock gated for the specified
@@ -492,7 +492,7 @@
if (enterPwrGatingEvent.scheduled())
deschedule(enterPwrGatingEvent);
// For any active thread running, update CPU power state to active (ON)
-ClockedObject::pwrState(Enums::PwrState::ON);
+powerState->set(Enums::PwrState::ON);
updateCycleCounters(CPU_STATE_WAKEUP);
}
@@ -513,7 +513,7 @@
updateCycleCounters(CPU_STATE_SLEEP);
// All CPU threads suspended, enter lower power state for the CPU
-ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
+powerState->set(Enums::PwrState::CLK_GATED);
// If pwrGatingLatency is set to 0 then this mechanism is disabled
if (powerGatingOnIdle) {
@@ -532,7 +532,7 @@
void
BaseCPU::enterPwrGating(void)
{
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
}
void
@@ -548,7 +548,7 @@
flushTLBs();
// Go to the power gating state
-ClockedObject::pwrState(Enums::PwrState::OFF);
+powerState->set(Enums::PwrState::OFF);
}
void
@@ -561,7 +561,7 @@
_pid = oldCPU->getPid();
_taskId = oldCPU->taskId();
// Take over the power state of the switchedOut CPU
-ClockedObject::pwrState(oldCPU->pwrState());
+powerState->set(oldCPU->powerState->get());
previousState = oldCPU->previousState;
previousCycle = oldCPU->previousCycle;
diff --git a/src/dev/arm/fvp_base_pwr_ctrl.cc
b/src/dev/arm/fvp_base_pwr_ctrl.cc
index a6650b8..5113c92 100644
--- a/src/dev/arm/fvp_base_pwr_ctrl.cc
+++ b/src/dev/arm/fvp_base_pwr_ctrl.cc
@@ -280,7 +280,7 @@
npwrs->pc = 0;
}
}
-tc->getCpuPtr()->pwrState(Enums::PwrState::ON);
+tc->getCpuPtr()->powerState->set(Enums::PwrState::ON);
}
void
@@ -295,7 +295,7 @@
pwrs->pc = 0;
// Clear power-on reason
pwrs->wk = 0;
-tc->getCpuPtr()->pwrState(Enums::PwrState::OFF);
+tc->getCpuPtr()->powerState->set(Enums::PwrState::OFF);
}
void
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 3819093..8732613
[gem5-dev] Change in gem5/gem5[develop]: sim-power: Specify the states a PowerState object can be in
Hello Andreas Sandberg, Anouk Van Laer,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28050
to review the following change.
Change subject: sim-power: Specify the states a PowerState object can be in
..
sim-power: Specify the states a PowerState object can be in
This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.
Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg
Signed-off-by: Nikos Nikoleris
---
M src/cpu/BaseCPU.py
M src/sim/PowerState.py
M src/sim/power_state.cc
M src/sim/power_state.hh
4 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 53652bf..feb0eed 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -302,3 +302,7 @@
cpus_node.append(node)
yield cpus_node
+
+def __init__(self, **kwargs):
+super(BaseCPU, self).__init__(**kwargs)
+self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py
index 59491ec..bfa53e2 100644
--- a/src/sim/PowerState.py
+++ b/src/sim/PowerState.py
@@ -62,6 +62,11 @@
# routine
default_state = Param.PwrState("UNDEFINED", "Default Power State")
+# Possible power states this object can be in sorted from the most
+# to the least performant
+possible_states = VectorParam.PwrState(
+[], "Power states this object can be in")
+
clk_gate_min = Param.Latency('1ns',"Min value of the distribution")
clk_gate_max = Param.Latency('1s',"Max value of the distribution")
clk_gate_bins = Param.Unsigned('20', "# bins in clk gated
distribution")
diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index 7074dd6..a2ed7fe 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -40,8 +40,10 @@
#include "base/logging.hh"
PowerState::PowerState(const PowerStateParams *p) :
-SimObject(p), _currState(p->default_state), prvEvalTick(0),
-stats(*this)
+SimObject(p), _currState(p->default_state),
+possibleStates(p->possible_states.begin(),
+ p->possible_states.end()),
+prvEvalTick(0), stats(*this)
{
}
@@ -68,6 +70,11 @@
void
PowerState::set(Enums::PwrState p)
{
+// Check if this power state is actually allowed by checking whether
it is
+// present in pwrStateToIndex-dictionary
+panic_if(possibleStates.find(p) == possibleStates.end(),
+ "Cannot go to %s in %s \n", Enums::PwrStateStrings[p],
name());
+
// Function should ideally be called only when there is a state change
if (_currState == p) {
warn_once("PowerState: Already in the requested power state, "
diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh
index 8cb3b3b..af7527f 100644
--- a/src/sim/power_state.hh
+++ b/src/sim/power_state.hh
@@ -98,11 +98,22 @@
*/
void computeStats();
+/**
+ * Return the power states this object can be in
+ */
+std::set getPossibleStates() const
+{
+return possibleStates;
+}
+
protected:
/** To keep track of the current power state */
Enums::PwrState _currState;
+/** The possible power states this object can be in */
+const std::set possibleStates;
+
/** Last tick the power stats were calculated */
Tick prvEvalTick;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Gerrit-Change-Number: 28050
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-power: Addition of PowerDomains
Hello Andreas Sandberg, Anouk Van Laer, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28051 to review the following change. Change subject: sim-power: Addition of PowerDomains .. sim-power: Addition of PowerDomains PowerDomains group multiple objects together to regulate their power state. There are 2 types of objects in a PowerDomain: leaders and followers. The power state of a PowerDomain is the most performant power state of any of the leaders. The power state of the followers is determined by the power state of the PowerDomain they belong to: they need to be in a power state which is more or equally performant to the power state of the PowerDomain. Leaders can be ClockedObjects or other PowerDomains. Followers can only be ClockedObjects. PowerDomains can be be nested but a PowerDomain can only be a leader of another PowerDomain, NOT a follower. PowerDomains are not present in the hierarchy by default, the user needs to create and configure them in the configuration file. The user can add an hierachy by setting the led_by parameter. gem5 will then create leaders and followers for each domain and calculate the allowed power states for the domain. Objects in a PowerDomain need to have at least the ON state in the possible_states. An example of a powerDomain config is: pd = PowerDomain() cpu0 = BaseCPU() cpu1 = BaseCPU() shared_cache = BaseCache() cache.power_state.led_by = pd pd.led_by = [cpu0, cpu1] This will create a PowerDomain, where the CPUs determine their own power states and the shared cache (via the PowerDomain) follows those power states (when possible). Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff Reviewed-by: Andreas Sandberg Reviewed-by: Sascha Bischoff Signed-off-by: Nikos Nikoleris --- A src/sim/PowerDomain.py M src/sim/PowerState.py M src/sim/SConscript A src/sim/power_domain.cc A src/sim/power_domain.hh M src/sim/power_state.cc M src/sim/power_state.hh 7 files changed, 585 insertions(+), 2 deletions(-) diff --git a/src/sim/PowerDomain.py b/src/sim/PowerDomain.py new file mode 100644 index 000..9d45252 --- /dev/null +++ b/src/sim/PowerDomain.py @@ -0,0 +1,49 @@ +# Copyright (c) 2017, 2019-2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +import sys + +from m5.params import * +from m5.objects.PowerState import PowerState + +# A power domain groups multiple ClockedObjects and creates a +# hierarchy in which follower ClockedObjects (caches for example) can +# change power state depeding on what the leader objects (CPUs for +# example) do. The power domain is the link between these. +class PowerDomain(PowerState): +type = 'PowerDomain' +cxx_header = 'sim/power_domain.hh' + diff --git a/src/sim/PowerState.py b/src/sim/PowerState.py index bfa53e2..30f62e0 100644 --- a/src/sim/PowerState.py +++ b/src/sim/PowerState.py @@ -70,3
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher page crossing
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28048
to review the following change.
Change subject: mem-ruby: MESI_Three_level prefetcher page crossing
..
mem-ruby: MESI_Three_level prefetcher page crossing
This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.
Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index 429fd25..5a69ba8 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -127,7 +127,7 @@
nonunit_filter = 256,
train_misses = 5,
num_startup_pfs = 4,
-cross_page = False
+cross_page = True
)
l0_cntrl = L0Cache_Controller(
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 7c7eca1..a62ed84 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -140,6 +140,7 @@
PF_Load, desc="Load request from prefetcher";
PF_Ifetch, desc="Instruction fetch request from prefetcher";
PF_Store,desc="Exclusive load request from prefetcher";
+PF_Bad_Addr, desc="Throw away prefetch request due to bad address
generation";
}
// TYPES
@@ -323,7 +324,16 @@
in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank =
2) {
if (optionalQueue_in.isReady(clockEdge())) {
peek(optionalQueue_in, RubyRequest) {
-if (in_msg.Type == RubyRequestType:IFETCH) {
+// first check for valid address
+MachineID mid := mapAddressToMachine(in_msg.LineAddress,
MachineType:Directory);
+NodeID nid := machineIDToNodeID(mid);
+int nidint := IDToInt(nid);
+int numDirs := machineCount(MachineType:Directory);
+if (nidint >= numDirs) {
+ Entry cache_entry := static_cast(Entry, "pointer",
Dcache.getNullEntry());
+ TBE tbe := TBEs.getNullEntry();
+ trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
+} else if (in_msg.Type == RubyRequestType:IFETCH) {
// Instruction Prefetch
Entry icache_entry := getICacheEntry(in_msg.LineAddress);
if (is_valid(icache_entry)) {
@@ -1162,4 +1172,8 @@
o_popIncomingResponseQueue;
kd_wakeUpDependents;
}
+
+ transition(I, PF_Bad_Addr) {
+pq_popPrefetchQueue;
+ }
}
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Gerrit-Change-Number: 28048
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Timothy Hayes
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MESI_Three_Level erroneous transition
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28047
to review the following change.
Change subject: mem-ruby: fix MESI_Three_Level erroneous transition
..
mem-ruby: fix MESI_Three_Level erroneous transition
The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.
Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
---
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
index 00d897a..de82635 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -996,7 +996,7 @@
}
// Transitions from IM
- transition({IM,SM}, Inv, IM) {
+ transition(IM, Inv, IM) {
fi_sendInvAck;
l_popL2RequestQueue;
}
@@ -1029,7 +1029,7 @@
kd_wakeUpDependents;
}
- transition(SM, L0_Invalidate_Else, SM_IL0) {
+ transition(SM, {Inv,L0_Invalidate_Else}, SM_IL0) {
forward_eviction_to_L0_else;
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Gerrit-Change-Number: 28047
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Timothy Hayes
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base,arch,sim,cpu: Move object file loader components into a namespace.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/24783 ) Change subject: base,arch,sim,cpu: Move object file loader components into a namespace. .. base,arch,sim,cpu: Move object file loader components into a namespace. The components in base/loader were moved into a namespace called Loader. This will make it easier to add loader components with fairly short natural names which don't invite name collisions. gem5 should use namespaces more in general for that reason and to make it easier to write independent components without having to worry about name collisions being added in the future. Unfortunately this namespace has the same name as a class used to load an object file into a process object. These names can be disambiguated because the Process loader is inside the Process scope and the Loader namespace is at global scope, but it's still confusing to read. Fortunately, this shouldn't last for very long since the responsibility for loading Processes is going to move to a fake OS object which will expect to load a particular type of Process, for instance, fake 64 bit x86 linux will load either 32 or 64 bit x86 processes. That means that the capability to feed any binary that matches the current build into gem5 and have gem5 figure out what to do with it will likely be going away in the future. That's likely for the best, since it will force users to be more explicit about what they're trying to do, ie what OS they want to try to load a given binary, and also will prevent loading two or more Processes which are for different OSes to the same system, something that's possible today as far as I know since there are no consistency checks. Change-Id: Iea0012e98f39f5e20a7c351b78cdff9401f5e326 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24783 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/arch/arm/freebsd/fs_workload.cc M src/arch/arm/freebsd/process.cc M src/arch/arm/freebsd/process.hh M src/arch/arm/fs_workload.cc M src/arch/arm/fs_workload.hh M src/arch/arm/insts/branch.cc M src/arch/arm/insts/branch.hh M src/arch/arm/insts/branch64.cc M src/arch/arm/insts/branch64.hh M src/arch/arm/insts/data64.cc M src/arch/arm/insts/data64.hh M src/arch/arm/insts/macromem.cc M src/arch/arm/insts/macromem.hh M src/arch/arm/insts/mem.cc M src/arch/arm/insts/mem.hh M src/arch/arm/insts/mem64.cc M src/arch/arm/insts/mem64.hh M src/arch/arm/insts/misc.cc M src/arch/arm/insts/misc.hh M src/arch/arm/insts/misc64.cc M src/arch/arm/insts/misc64.hh M src/arch/arm/insts/pred_inst.cc M src/arch/arm/insts/pred_inst.hh M src/arch/arm/insts/pseudo.cc M src/arch/arm/insts/pseudo.hh M src/arch/arm/insts/static_inst.cc M src/arch/arm/insts/static_inst.hh M src/arch/arm/insts/sve.cc M src/arch/arm/insts/sve.hh M src/arch/arm/insts/sve_macromem.hh M src/arch/arm/insts/sve_mem.cc M src/arch/arm/insts/sve_mem.hh M src/arch/arm/insts/vfp.cc M src/arch/arm/insts/vfp.hh M src/arch/arm/isa/templates/sve_mem.isa M src/arch/arm/linux/fs_workload.cc M src/arch/arm/linux/process.cc M src/arch/arm/linux/process.hh M src/arch/arm/process.cc M src/arch/arm/process.hh M src/arch/arm/stacktrace.cc M src/arch/arm/system.cc M src/arch/mips/isa/base.isa M src/arch/mips/isa/formats/branch.isa M src/arch/mips/isa/formats/control.isa M src/arch/mips/isa/formats/fp.isa M src/arch/mips/isa/formats/int.isa M src/arch/mips/isa/formats/mem.isa M src/arch/mips/isa/formats/mt.isa M src/arch/mips/isa/formats/noop.isa M src/arch/mips/isa/formats/tlbop.isa M src/arch/mips/isa/formats/trap.isa M src/arch/mips/isa/formats/unimp.isa M src/arch/mips/isa/formats/unknown.isa M src/arch/mips/linux/process.cc M src/arch/mips/linux/process.hh M src/arch/mips/process.cc M src/arch/mips/process.hh M src/arch/power/insts/branch.cc M src/arch/power/insts/branch.hh M src/arch/power/insts/condition.cc M src/arch/power/insts/condition.hh M src/arch/power/insts/floating.cc M src/arch/power/insts/floating.hh M src/arch/power/insts/integer.cc M src/arch/power/insts/integer.hh M src/arch/power/insts/mem.cc M src/arch/power/insts/mem.hh M src/arch/power/insts/misc.cc M src/arch/power/insts/misc.hh M src/arch/power/insts/static_inst.cc M src/arch/power/insts/static_inst.hh M src/arch/power/isa/formats/unimp.isa M src/arch/power/isa/formats/unknown.isa M src/arch/power/linux/process.cc M src/arch/power/linux/process.hh M src/arch/power/process.cc M src/arch/power/process.hh M src/arch/riscv/bare_metal/fs_workload.cc M src/arch/riscv/bare_metal/fs_workload.hh M src/arch/riscv/insts/amo.cc M src/arch/riscv/insts/amo.hh M src/arch/riscv/insts/compressed.cc M src/arch/riscv/insts/compressed.hh M src/arch/riscv/insts/mem.cc M src/arch/riscv/insts/mem.hh M src/arch/riscv/insts/pseudo.hh M src/arch/riscv/insts/standard.cc M src/arch/riscv/insts/standard.hh M src/arch/riscv/insts/unknown.hh M
