[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: x86: Set a physical address for local accesses.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/29008 )
Change subject: x86: Set a physical address for local accesses.
..
x86: Set a physical address for local accesses.
This avoids problems when other parts of the simulator blindly try to
retrieve the physical address.
Change-Id: Ia13a2b85b9f919e1e81a6a0f67d10858e98244e5
---
M src/arch/x86/tlb.cc
1 file changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ceccba8..71ab563 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -206,6 +206,7 @@
if (!msrAddrToIndex(regNum, vaddr))
return std::make_shared(0);
+req->setPaddr(req->getVaddr());
req->setLocalAccessor(
[read,regNum](ThreadContext *tc, PacketPtr pkt)
{
@@ -223,6 +224,7 @@
// space.
assert(!(IOPort & ~0x));
if (IOPort == 0xCF8 && req->getSize() == 4) {
+req->setPaddr(req->getVaddr());
req->setLocalAccessor(
[read](ThreadContext *tc, PacketPtr pkt)
{
@@ -262,6 +264,7 @@
req->setFlags(Request::STRICT_ORDER);
uint8_t func;
PseudoInst::decodeAddrOffset(paddr - m5opRange.start(), func);
+req->setPaddr(req->getVaddr());
req->setLocalAccessor(
[func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Ia13a2b85b9f919e1e81a6a0f67d10858e98244e5
Gerrit-Change-Number: 29008
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Get gem5 to build with Clang 8
Mark Hildebrand has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28947 )
Change subject: misc: Get gem5 to build with Clang 8
..
misc: Get gem5 to build with Clang 8
Added missing overrides:
- src/mem/token_port.hh
- src/sim/power/mathexpr_powermodel.hh
Remove Unused static constants:
- src/arch/x86/process.cc
Related Issue: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-534
Change-Id: Icc725e2522dcee919e299f4ea7a9f1773f5dfa4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28947
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/process.cc
M src/mem/token_port.hh
M src/sim/power/mathexpr_powermodel.hh
3 files changed, 3 insertions(+), 29 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index f377e2a..1b7fd3e 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -67,32 +67,6 @@
using namespace std;
using namespace X86ISA;
-static const int ArgumentReg[] = {
-INTREG_RDI,
-INTREG_RSI,
-INTREG_RDX,
-// This argument register is r10 for syscalls and rcx for C.
-INTREG_R10W,
-// INTREG_RCX,
-INTREG_R8W,
-INTREG_R9W
-};
-
-static const int NumArgumentRegs M5_VAR_USED =
-sizeof(ArgumentReg) / sizeof(const int);
-
-static const int ArgumentReg32[] = {
-INTREG_EBX,
-INTREG_ECX,
-INTREG_EDX,
-INTREG_ESI,
-INTREG_EDI,
-INTREG_EBP
-};
-
-static const int NumArgumentRegs32 M5_VAR_USED =
-sizeof(ArgumentReg) / sizeof(const int);
-
template class MultiLevelPageTable,
LongModePTE<38, 30>,
LongModePTE<29, 21>,
diff --git a/src/mem/token_port.hh b/src/mem/token_port.hh
index 3d74315..7112a41 100644
--- a/src/mem/token_port.hh
+++ b/src/mem/token_port.hh
@@ -94,7 +94,7 @@
std::deque respQueue;
-void recvRespRetry();
+void recvRespRetry() override;
public:
TokenSlavePort(const std::string& name, ClockedObject *owner,
diff --git a/src/sim/power/mathexpr_powermodel.hh
b/src/sim/power/mathexpr_powermodel.hh
index 1edb800..37ea190 100644
--- a/src/sim/power/mathexpr_powermodel.hh
+++ b/src/sim/power/mathexpr_powermodel.hh
@@ -64,14 +64,14 @@
*
* @return Power (Watts) consumed by this object (dynamic component)
*/
-double getDynamicPower() const { return eval(dyn_expr); }
+double getDynamicPower() const override { return eval(dyn_expr); }
/**
* Get the static power consumption.
*
* @return Power (Watts) consumed by this object (static component)
*/
-double getStaticPower() const { return eval(st_expr); }
+double getStaticPower() const override { return eval(st_expr); }
/**
* Get the value for a variable (maps to a stat)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Icc725e2522dcee919e299f4ea7a9f1773f5dfa4d
Gerrit-Change-Number: 28947
Gerrit-PatchSet: 3
Gerrit-Owner: Mark Hildebrand
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Mark Hildebrand
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: x86: Set a physical address for local accesses.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28987 )
Change subject: x86: Set a physical address for local accesses.
..
x86: Set a physical address for local accesses.
This avoids problems when other parts of the simulator blindly try to
retrieve the physical address.
Change-Id: Ia13a2b85b9f919e1e81a6a0f67d10858e98244e5
---
M src/arch/x86/tlb.cc
1 file changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ceccba8..71ab563 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -206,6 +206,7 @@
if (!msrAddrToIndex(regNum, vaddr))
return std::make_shared(0);
+req->setPaddr(req->getVaddr());
req->setLocalAccessor(
[read,regNum](ThreadContext *tc, PacketPtr pkt)
{
@@ -223,6 +224,7 @@
// space.
assert(!(IOPort & ~0x));
if (IOPort == 0xCF8 && req->getSize() == 4) {
+req->setPaddr(req->getVaddr());
req->setLocalAccessor(
[read](ThreadContext *tc, PacketPtr pkt)
{
@@ -262,6 +264,7 @@
req->setFlags(Request::STRICT_ORDER);
uint8_t func;
PseudoInst::decodeAddrOffset(paddr - m5opRange.start(), func);
+req->setPaddr(req->getVaddr());
req->setLocalAccessor(
[func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28987
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia13a2b85b9f919e1e81a6a0f67d10858e98244e5
Gerrit-Change-Number: 28987
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Change setCPU to setThreadContext in Interrupts.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28988 )
Change subject: arch,cpu: Change setCPU to setThreadContext in Interrupts.
..
arch,cpu: Change setCPU to setThreadContext in Interrupts.
The ThreadContext can be used to access the cpu if needed, and is a
more representative interface to various pieces of state than the CPU
itself. Also convert some of the methods in Interupts to use the
locally stored ThreadContext pointer instead of taking one as an
argument. This makes calling those methods simpler and less error
prone.
Change-Id: I740bd99f92e54e052a618a4ae2927ea1c4ece193
---
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa/insts/misc.isa
M src/arch/generic/interrupts.hh
M src/arch/mips/interrupts.cc
M src/arch/mips/interrupts.hh
M src/arch/power/interrupts.hh
M src/arch/riscv/interrupts.hh
M src/arch/sparc/interrupts.hh
M src/arch/x86/interrupts.cc
M src/arch/x86/interrupts.hh
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/intr_control.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/execute.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/simple/base.cc
19 files changed, 113 insertions(+), 166 deletions(-)
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
index 02f1e6d..ae1d435 100644
--- a/src/arch/arm/interrupts.cc
+++ b/src/arch/arm/interrupts.cc
@@ -46,7 +46,7 @@
}
bool
-ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type)
const
+ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
{
// Table G1-17~19 of ARM V8 ARM
InterruptMask mask;
diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh
index e365a00..814fd71 100644
--- a/src/arch/arm/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -57,19 +57,11 @@
class Interrupts : public BaseInterrupts
{
private:
-BaseCPU * cpu;
-
bool interrupts[NumInterruptTypes];
uint64_t intStatus;
public:
-void
-setCPU(BaseCPU * _cpu)
-{
-cpu = _cpu;
-}
-
typedef ArmInterruptsParams Params;
const Params *
@@ -78,7 +70,7 @@
return dynamic_cast(_params);
}
-Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
+Interrupts(Params * p) : BaseInterrupts(p)
{
clearAll();
}
@@ -128,10 +120,10 @@
INT_MASK_P // pending
};
-bool takeInt(ThreadContext *tc, InterruptTypes int_type) const;
+bool takeInt(InterruptTypes int_type) const;
bool
-checkInterrupts(ThreadContext *tc) const
+checkInterrupts() const
{
HCR hcr = tc->readMiscReg(MISCREG_HCR);
@@ -150,9 +142,9 @@
(hcr.va && allowVAbort)) )
return false;
-bool take_irq = takeInt(tc, INT_IRQ);
-bool take_fiq = takeInt(tc, INT_FIQ);
-bool take_ea = takeInt(tc, INT_ABT);
+bool take_irq = takeInt(INT_IRQ);
+bool take_fiq = takeInt(INT_FIQ);
+bool take_ea = takeInt(INT_ABT);
return ((interrupts[INT_IRQ] && take_irq) ||
(interrupts[INT_FIQ] && take_fiq) ||
@@ -220,9 +212,9 @@
}
Fault
-getInterrupt(ThreadContext *tc)
+getInterrupt() override
{
-assert(checkInterrupts(tc));
+assert(checkInterrupts());
HCR hcr = tc->readMiscReg(MISCREG_HCR);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@@ -236,9 +228,9 @@
bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
-bool take_irq = takeInt(tc, INT_IRQ);
-bool take_fiq = takeInt(tc, INT_FIQ);
-bool take_ea = takeInt(tc, INT_ABT);
+bool take_irq = takeInt(INT_IRQ);
+bool take_fiq = takeInt(INT_FIQ);
+bool take_ea = takeInt(INT_ABT);
if (interrupts[INT_IRQ] && take_irq)
return std::make_shared();
@@ -262,21 +254,17 @@
panic("intStatus and interrupts not in sync\n");
}
-void
-updateIntrInfo(ThreadContext *tc)
-{
-; // nothing to do
-}
+void updateIntrInfo() override {} // nothing to do
void
-serialize(CheckpointOut &cp) const
+serialize(CheckpointOut &cp) const override
{
SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
SERIALIZE_SCALAR(intStatus);
}
void
-unserialize(CheckpointIn &cp)
+unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
UNSERIALIZE_SCALAR(intStatus);
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 88c473d..d0fd4e0 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -721,7 +721,7 @@
SevMailbox = 0;
PseudoInst::quiesceSkip(tc);
} else if (tc->getCpuPtr()->getInterruptCon
[gem5-dev] Re: c64 simulation
This is interesting, Gabe! I agree that keeping it in EXTRAS makes sense. IMO, since we probably don't need code review on it, a github repo or something similar would probably be best. We should link to it on the website, though! Cheers, Jason On Mon, May 11, 2020 at 12:03 AM Gabe Black via gem5-dev wrote: > It isn't it's own ISA for a few reasons, but basically the CPU is a regular > device model. It's running the kernal (they spell it with an a) ROM, and > the basic ROM. I've mostly implemented the board logic and have started on > the graphics, but then there's audio, interface devices, and then a > mechanism for cartridge, disk, or cassette based program loading. It's a > very simple computer from a modern perspective, but it still has a lot of > parts. I've been ignoring timing mode for the time being. I would actually > rather not check it into the main repository since that puts it more in the > middle of things than it deserves or is warranted, but I thought it might > be amusing/educational/interesting for other people that want to play with > it. > > Gabe > > On Sun, May 10, 2020 at 11:51 PM Ciro Santilli > wrote: > > > So this adds a new ISA is that correct? > > > > I say add it to the main tree, it could serve as a good small ISA > example. > > > > Is it running ROMs fine? Is the simulation fast enough for interactive > > play? Wiki says it run at 1MHz so its just about what Atomic does, so I'm > > guessing it could. > > > > -- > > *From:* Gabe Black via gem5-dev > > *Sent:* Monday, May 11, 2020 1:33 AM > > *To:* gem5 Developer List > > *Cc:* Gabe Black > > *Subject:* [gem5-dev] c64 simulation > > > > Hi folks. For my own amusement, I've been working on a c64 emulator based > > on gem5 which can be built in using EXTRAS. Would it make sense to put > that > > up on gerrit somewhere in its own repository? I put what I have so far > in a > > directory called "toys" to make it clear it's just for fun. > > > > Gabe > > ___ > > gem5-dev mailing list -- gem5-dev@gem5.org > > To unsubscribe send an email to gem5-dev-le...@gem5.org > > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > IMPORTANT NOTICE: The contents of this email and any attachments are > > confidential and may also be privileged. If you are not the intended > > recipient, please notify the sender immediately and do not disclose the > > contents to any other person, use it for any purpose, or store or copy > the > > information in any medium. Thank you. > > > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: GCB status
Hey Giacomo, Yes, it's intended. We're still planning to replace Kokoro with the GCB system (I'd actually like to call it Kokoro v2, as I'm rather fond of the name :) ). We treated the time GCB was on Gerrit as an experiment to see if it did what we wanted. By and large, it does. The outstanding problem is it'd trigger on every patchset submitted to Gerrit. Most of the patchsets submitted to Gerrit are just things like trivial changes due to rebases, and contributors altering code in response to reviewer comments. It's a really inefficient way to do it (not to mention costly), so we turned it off and fell back on Kokoro for the time being . It's currently on my TODO list to write a better trigger that works the same way as Kokoro does (triggering on a Maintainer+1 vote), but that's on the back-burner until gem5-20 is out the door. Hopefully I will return to this soon. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Tue, May 12, 2020 at 7:10 AM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi Bobby, > > > > It seems like we are just using kokoro now as CI platform. Is this > intended? > > (What happened with GCB?) > > > > Kind Regards > > > > Giacomo > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Remove infinite queue between Ruby and memory
Bradford Beckmann has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28387 )
Change subject: mem: Remove infinite queue between Ruby and memory
..
mem: Remove infinite queue between Ruby and memory
AbstractController sends requests using a QueuedMasterPort which has an
implicit buffer which is unbounded. Remove this by changing the port to
a MasterPort and implement a retry mechanism for AbstractController.
Although the request remains in the MessageBuffer if a retry is needed,
the additional retry logic optimizes serviceMemoryQueue slightly and
prevents the DRAMCtrl retry stats from being incorrect due to multiple
calls to sendTimingReq.
Change-Id: I8c592af92a1a499a418f34cfee16dd69d84803ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28387
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
Maintainer: Bradford Beckmann
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
2 files changed, 20 insertions(+), 20 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
Bradford Beckmann: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 59611ae..b729d26 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -56,7 +56,7 @@
m_transitions_per_cycle(p->transitions_per_cycle),
m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
m_mandatory_queue_latency(p->mandatory_queue_latency),
- memoryPort(csprintf("%s.memory", name()), this, ""),
+ memoryPort(csprintf("%s.memory", name()), this),
addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
{
if (m_version == 0) {
@@ -250,12 +250,15 @@
// to make more progress. Make sure it wakes up
scheduleEvent(Cycles(1));
recvTimingResp(pkt);
-} else {
+} else if (memoryPort.sendTimingReq(pkt)) {
mem_queue->dequeue(clockEdge());
-memoryPort.schedTimingReq(pkt, clockEdge());
// Since the queue was popped the controller may be able
// to make more progress. Make sure it wakes up
scheduleEvent(Cycles(1));
+} else {
+scheduleEvent(Cycles(1));
+delete pkt;
+delete s;
}
return true;
@@ -306,11 +309,6 @@
{
int num_functional_writes = 0;
-// Check the buffer from the controller to the memory.
-if (memoryPort.trySatisfyFunctional(pkt)) {
-num_functional_writes++;
-}
-
// Update memory itself.
memoryPort.sendFunctional(pkt);
return num_functional_writes + 1;
@@ -369,12 +367,15 @@
return true;
}
+void
+AbstractController::MemoryPort::recvReqRetry()
+{
+controller->serviceMemoryQueue();
+}
+
AbstractController::MemoryPort::MemoryPort(const std::string &_name,
AbstractController *_controller,
- const std::string &_label)
-: QueuedMasterPort(_name, _controller, reqQueue, snoopRespQueue),
- reqQueue(*_controller, *this, _label),
- snoopRespQueue(*_controller, *this, false, _label),
- controller(_controller)
+ PortID id)
+: MasterPort(_name, _controller, id), controller(_controller)
{
}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 15aff12..1577cfa 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -228,26 +228,25 @@
/**
* Port that forwards requests and receives responses from the
- * memory controller. It has a queue of packets not yet sent.
+ * memory controller.
*/
-class MemoryPort : public QueuedMasterPort
+class MemoryPort : public MasterPort
{
private:
-// Packet queues used to store outgoing requests and snoop
responses.
-ReqPacketQueue reqQueue;
-SnoopRespPacketQueue snoopRespQueue;
-
// Controller that operates this port.
AbstractController *controller;
public:
MemoryPort(const std::string &_name, AbstractController
*_controller,
- const std::string &_label);
+ PortID id = InvalidPortID);
+ protected:
// Function for receiving a timing response from the peer port.
// Currently the pkt is handed to the coherence controller
// associated with this port.
bool recvTimingResp(PacketPtr pkt);
+
+void recvReqRetry();
};
/* Master port to the memory controller. */
--
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Added missing optional dependencies to 18.04 Docker
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28892 ) Change subject: misc: Added missing optional dependencies to 18.04 Docker .. misc: Added missing optional dependencies to 18.04 Docker Change-Id: Ibc43664f99ce9fbd28d14352243fb17b7754289b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28892 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile index a0064b6..95511a8 100644 --- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile +++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile @@ -30,4 +30,5 @@ RUN apt -y upgrade RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \ libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \ -python-dev python python-six doxygen +python-dev python python-six doxygen libboost-all-dev libhdf5-serial-dev \ +python-pydot libpng-dev -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28892 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: Ibc43664f99ce9fbd28d14352243fb17b7754289b Gerrit-Change-Number: 28892 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Added Dockerfile for Ubuntu 20.04
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28889 ) Change subject: misc: Added Dockerfile for Ubuntu 20.04 .. misc: Added Dockerfile for Ubuntu 20.04 This Dockerfile creates an image which simulates an Ubuntu 20.04 environment. Unlike the Ubuntu 18.04 Dockerfile, this does not use Python2. It uses exclusively Python3. Ubuntu 20.04 has Python3 installed by default. The image this Dockerfile creates can be obtained from "gcr.io/gem5-test/ubuntu-20.04_all-dependencies". To pull: docker pull gcr.io/gem5-test/ubuntu-20.04_all-dependencies Change-Id: I73b51028e0d6a3198aa6e7b1906d20ed6eb6c815 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28889 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile 1 file changed, 35 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile new file mode 100644 index 000..814ef75 --- /dev/null +++ b/util/dockerfiles/ubuntu-20.04_all-dependencies/Dockerfile @@ -0,0 +1,35 @@ +# Copyright (c) 2020 The Regents of the University of California +# All Rights Reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +FROM ubuntu:20.04 + +ENV DEBIAN_FRONTEND=noninteractive +RUN apt -y update +RUN apt -y upgrade +RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \ +libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \ +python3-dev python3-six python-is-python3 doxygen libboost-all-dev \ +libhdf5-serial-dev python3-pydot libpng-dev -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28889 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I73b51028e0d6a3198aa6e7b1906d20ed6eb6c815 Gerrit-Change-Number: 28889 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Added python-six as a dependency in 18.04 docker
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28891 ) Change subject: misc: Added python-six as a dependency in 18.04 docker .. misc: Added python-six as a dependency in 18.04 docker Previously the docker utilized Python-Pip. This is an intermediate dependency we don't need. We can install the Python-six module directly via the APT framework. Change-Id: I30e3e1cdca802ca19422140f39af7dc9dc166ed7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28891 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile index 95923f5..a0064b6 100644 --- a/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile +++ b/util/dockerfiles/ubuntu-18.04_all-dependencies/Dockerfile @@ -30,5 +30,4 @@ RUN apt -y upgrade RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \ libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \ -python-dev python python-pip doxygen -RUN pip install six +python-dev python python-six doxygen -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28891 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I30e3e1cdca802ca19422140f39af7dc9dc166ed7 Gerrit-Change-Number: 28891 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Removed python3 Dockerfile
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/28890 ) Change subject: misc: Removed python3 Dockerfile .. misc: Removed python3 Dockerfile This was previously used to test gem5 being compiled and run in a Python3 environment. This is redundant with the introduction of "util/dockerfiles/ubuntu-20.04_all-dependencies", which uses python3 exclusively. Change-Id: Ie837da338c3985ba92aff84144948a23fd6ece3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28890 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- D util/dockerfiles/python3/Dockerfile 1 file changed, 0 insertions(+), 37 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/util/dockerfiles/python3/Dockerfile b/util/dockerfiles/python3/Dockerfile deleted file mode 100644 index 2529f36..000 --- a/util/dockerfiles/python3/Dockerfile +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2020 The Regents of the University of California -# All Rights Reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -FROM ubuntu:18.04 - -RUN apt -y update -RUN apt -y upgrade -RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \ -libprotobuf-dev protobuf-compiler libprotoc-dev libgoogle-perftools-dev \ -python-dev python python3-dev python3.6 python-six python3-venv - -ENV VIRTUAL_ENV "/venv" -RUN python3 -m venv $VIRTUAL_ENV -ENV PATH "$VIRTUAL_ENV/bin:$PATH" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28890 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: Ie837da338c3985ba92aff84144948a23fd6ece3f Gerrit-Change-Number: 28890 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: sim: Fixes for mremap
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28948 )
Change subject: sim: Fixes for mremap
..
sim: Fixes for mremap
Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redundant mapRegion as remapRegion covers
its functionality.
JIRA: https://gem5.atlassian.net/browse/GEM5-475
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
---
M src/sim/mem_state.cc
M src/sim/syscall_emul.hh
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index 42d3781..f998fff 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -369,6 +369,7 @@
new_start_addr);
start_addr += _pageBytes;
+new_start_addr += _pageBytes;
/**
* The regions need to always be page-aligned otherwise the while
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..290c48e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1177,7 +1177,6 @@
warn("returning %08p as start\n", new_start);
p->memState->remapRegion(start, new_start, old_length);
-p->memState->mapRegion(new_start, new_length, "remapped");
return new_start;
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
Gerrit-Change-Number: 28948
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Factor out DRAM interface
Wendy Elsasser has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28967 )
Change subject: mem: Factor out DRAM interface
..
mem: Factor out DRAM interface
Separate out the DRAM specific functions into a new class:
- DRAMInterface
Move the Rank class to DRAMInterface since rank functions are
specific to the media.
Move DRAMPacket and Bank class definitions outside of DRAMCtrl.
This is patch 1 within a set of patches that separate the
memory controller and media interface. These changes enable
future incorporation of new media interfaces into the model.
Change-Id: Ief632d73ec27176a61f16b4f642c10d56630f376
---
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
2 files changed, 1,408 insertions(+), 1,051 deletions(-)
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 0a8479e..dc244fe 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -58,67 +58,23 @@
retryRdReq(false), retryWrReq(false),
nextReqEvent([this]{ processNextReqEvent(); }, name()),
respondEvent([this]{ processRespondEvent(); }, name()),
-deviceSize(p->device_size),
-deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
-deviceRowBufferSize(p->device_rowbuffer_size),
-devicesPerRank(p->devices_per_rank),
-burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
-rowBufferSize(devicesPerRank * deviceRowBufferSize),
-columnsPerRowBuffer(rowBufferSize / burstSize),
-columnsPerStripe(range.interleaved() ? range.granularity() /
burstSize : 1),
-ranksPerChannel(p->ranks_per_channel),
-bankGroupsPerRank(p->bank_groups_per_rank),
-bankGroupArch(p->bank_groups_per_rank > 0),
-banksPerRank(p->banks_per_rank), rowsPerBank(0),
readBufferSize(p->read_buffer_size),
writeBufferSize(p->write_buffer_size),
writeHighThreshold(writeBufferSize * p->write_high_thresh_perc /
100.0),
writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
minWritesPerSwitch(p->min_writes_per_switch),
-writesThisTime(0), readsThisTime(0),
-tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
-tBURST_MIN(p->tBURST_MIN),
-tCCD_L_WR(p->tCCD_L_WR),
-tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP),
tRAS(p->tRAS),
-tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI),
tRRD(p->tRRD),
-tRRD_L(p->tRRD_L), tPPD(p->tPPD), tAAD(p->tAAD), tXAW(p->tXAW),
-tXP(p->tXP), tXS(p->tXS),
-clkResyncDelay(tCL + p->tBURST_MAX),
-maxCommandsPerBurst(burstLength / p->beats_per_clock),
-dataClockSync(p->data_clock_sync),
-twoCycleActivate(p->two_cycle_activate),
-activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST),
-wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST),
-wrToRdDlySameBG(tCL + p->tBURST_MAX + p->tWTR_L),
-rdToWrDlySameBG(tRTW + p->tBURST_MAX),
-burstInterleave(tBURST != tBURST_MIN),
-burstDataCycles(burstInterleave ? p->tBURST_MAX / 2 : tBURST),
-memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
-pageMgmt(p->page_policy),
-maxAccessesPerRow(p->max_accesses_per_row),
+writesThisTime(0), readsThisTime(0), tCS(p->tCS),
+memSchedPolicy(p->mem_sched_policy),
frontendLatency(p->static_frontend_latency),
backendLatency(p->static_backend_latency),
nextBurstAt(0), prevArrival(0),
nextReqTime(0),
stats(*this),
-activeRank(0), timeStampOffset(0),
-lastStatsResetTick(0), enableDRAMPowerdown(p->enable_dram_powerdown)
+lastStatsResetTick(0)
{
-// sanity check the ranks since we rely on bit slicing for the
-// address decoding
-fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not "
- "allowed, must be a power of two\n", ranksPerChannel);
-
-fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, "
- "must be a power of two\n", burstSize);
readQueue.resize(p->qos_priorities);
writeQueue.resize(p->qos_priorities);
-for (int i = 0; i < ranksPerChannel; i++) {
-Rank* rank = new Rank(*this, p, i);
-ranks.push_back(rank);
-}
-
// perform a basic check of the write thresholds
if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
fatal("Write buffer low threshold %d must be smaller than the "
@@ -128,65 +84,13 @@
// determine the rows per bank by looking at the total capacity
uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
-// determine the dram actual capacity from the DRAM config in Mbytes
-uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank *
-ranksPerChannel;
-
-// if actual DRAM size does not match memory capacity in system warn!
-if (deviceCapacity != capacity / (1024 * 1024))
-warn("DRAM device capacity (%d Mbytes) does not match the "
- "addres
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Get gem5 to build with Clang 8
Mark Hildebrand has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28947 )
Change subject: misc: Get gem5 to build with Clang 8
..
misc: Get gem5 to build with Clang 8
Added missing overrides:
- src/mem/token_port.hh
- src/sim/power/mathexpr_powermodel.hh
Annotate global constants with M5_VAR_USED
- src/arch/x86/process.cc
Related Issue: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-534
Change-Id: Icc725e2522dcee919e299f4ea7a9f1773f5dfa4d
---
M src/arch/x86/process.cc
M src/mem/token_port.hh
M src/sim/power/mathexpr_powermodel.hh
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index f377e2a..6f9ad8a 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -67,7 +67,7 @@
using namespace std;
using namespace X86ISA;
-static const int ArgumentReg[] = {
+M5_VAR_USED static const int ArgumentReg[] = {
INTREG_RDI,
INTREG_RSI,
INTREG_RDX,
@@ -81,7 +81,7 @@
static const int NumArgumentRegs M5_VAR_USED =
sizeof(ArgumentReg) / sizeof(const int);
-static const int ArgumentReg32[] = {
+M5_VAR_USED static const int ArgumentReg32[] = {
INTREG_EBX,
INTREG_ECX,
INTREG_EDX,
diff --git a/src/mem/token_port.hh b/src/mem/token_port.hh
index 3d74315..7112a41 100644
--- a/src/mem/token_port.hh
+++ b/src/mem/token_port.hh
@@ -94,7 +94,7 @@
std::deque respQueue;
-void recvRespRetry();
+void recvRespRetry() override;
public:
TokenSlavePort(const std::string& name, ClockedObject *owner,
diff --git a/src/sim/power/mathexpr_powermodel.hh
b/src/sim/power/mathexpr_powermodel.hh
index 1edb800..37ea190 100644
--- a/src/sim/power/mathexpr_powermodel.hh
+++ b/src/sim/power/mathexpr_powermodel.hh
@@ -64,14 +64,14 @@
*
* @return Power (Watts) consumed by this object (dynamic component)
*/
-double getDynamicPower() const { return eval(dyn_expr); }
+double getDynamicPower() const override { return eval(dyn_expr); }
/**
* Get the static power consumption.
*
* @return Power (Watts) consumed by this object (static component)
*/
-double getStaticPower() const { return eval(st_expr); }
+double getStaticPower() const override { return eval(st_expr); }
/**
* Get the value for a variable (maps to a stat)
--
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Gerrit-Change-Number: 28947
Gerrit-PatchSet: 1
Gerrit-Owner: Mark Hildebrand
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[gem5-dev] Change in gem5/gem5[develop]: sim: Convert GuestABI example signatures to comments.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28308 )
Change subject: sim: Convert GuestABI example signatures to comments.
..
sim: Convert GuestABI example signatures to comments.
In the base Result and Argument templates, there were private static
functions which weren't meant to be used, but which would act as
documentation for what those functions should look like. They were
marked as private to prevent them from being accidentally used and
causing confusing, hard to debug errors.
Unfortunately, that also meant that those functions exist, and
apparently cause inconsistent problems with SFINAE. I assume if the
functions don't exist at all, then SFINAE will work properly. When
they're private, that seems to cause a substitution failure which
actually is an error which makes the build fail.
Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28308
Reviewed-by: Nikos Nikoleris
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/sim/guest_abi/definition.hh
1 file changed, 12 insertions(+), 9 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/guest_abi/definition.hh
b/src/sim/guest_abi/definition.hh
index becdb3c..4928b93 100644
--- a/src/sim/guest_abi/definition.hh
+++ b/src/sim/guest_abi/definition.hh
@@ -57,27 +57,28 @@
template
struct Result
{
- private:
/*
* Store result "ret" into the state accessible through tc. Optionally
* accept "state" in case it holds some signature wide information.
*
* Note that the declaration below is only to document the expected
- * signature and is private so it won't be used by accident.
+ * signature and is commented out so it won't be used by accident.
* Specializations of this Result class should define their own version
- * of this method which actually does something and is public.
+ * of this method which actually does something.
+ *
+ * static void store(ThreadContext *tc, const Ret &ret);
+ * static void store(ThreadContext *tc, const Ret &ret,
+ * typename ABI::State &state);
*/
-static void store(ThreadContext *tc, const Ret &ret);
-static void store(ThreadContext *tc, const Ret &ret,
- typename ABI::State &state);
/*
* Prepare for a result of type Ret. This might mean, for instance,
* allocating an argument register for a result pointer.
*
* This method can be excluded if no preparation is necessary.
+ *
+ * static void prepare(ThreadContext *tc, typename ABI::State &state);
*/
-static void prepare(ThreadContext *tc, typename ABI::State &state);
};
/*
@@ -98,16 +99,18 @@
*
* Like Result::store above, the declaration below is only to document
* the expected method signature.
+ *
+ * static Arg get(ThreadContext *tc, typename ABI::State &state);
*/
-static Arg get(ThreadContext *tc, typename ABI::State &state);
/*
* Prepare for an argument of type Arg. This might mean, for instance,
* allocating an argument register for a result pointer.
*
* This method can be excluded if no preparation is necessary.
+ *
+ * static void allocate(ThreadContext *tc, typename ABI::State &state);
*/
-static void allocate(ThreadContext *tc, typename ABI::State &state);
};
} // namespace GuestABI
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
Gerrit-Change-Number: 28308
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-CC: Yu-hsin Wang
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arm,x86,sim: Use the new return value suppression in GuestABI.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28289 )
Change subject: arm,x86,sim: Use the new return value suppression in
GuestABI.
..
arm,x86,sim: Use the new return value suppression in GuestABI.
This gets rid of some dummy Return structure definitions. Also augment
the PseudoInst::pseudoInst dispatch function so it can store or not
store results, depending on what's needed at each call sight.
Change-Id: If4a53bc0a27e5214a26ef1a100c99948ca95418d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28289
Reviewed-by: Gabe Black
Reviewed-by: Nikos Nikoleris
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/semihosting.cc
M src/arch/x86/tlb.cc
M src/sim/pseudo_inst.hh
3 files changed, 23 insertions(+), 30 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 7711a86..61a049d 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -696,18 +696,6 @@
namespace GuestABI
{
-// Ignore return values since those will be handled by semihosting.
-template
-struct Result
-{
-static void store(ThreadContext *tc, const T &ret) {}
-};
-template
-struct Result
-{
-static void store(ThreadContext *tc, const T &ret) {}
-};
-
// Handle arguments the same as for semihosting operations. Skipping the
first
// slot is handled internally by the State type.
template
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ceccba8..4464702 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -266,7 +266,7 @@
[func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
{
uint64_t ret;
-PseudoInst::pseudoInst(tc, func, ret);
+PseudoInst::pseudoInst(tc, func,
ret);
if (mode == Read)
pkt->setLE(ret);
return Cycles(1);
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 6a63812..982d6c8 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -59,16 +59,6 @@
namespace GuestABI
{
-template
-struct Result
-{
-static void
-store(ThreadContext *tc, const T &ret)
-{
-// Don't do anything with the pseudo inst results by default.
-}
-};
-
template <>
struct Argument
{
@@ -134,9 +124,9 @@
* @return Whether the pseudo instruction was recognized/handled.
*/
-template
+template
bool
-pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
+pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
{
DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
@@ -160,11 +150,11 @@
return true;
case M5OP_QUIESCE_TIME:
-result = invokeSimcall(tc, quiesceTime);
+result = invokeSimcall(tc, quiesceTime);
return true;
case M5OP_RPNS:
-result = invokeSimcall(tc, rpns);
+result = invokeSimcall(tc, rpns);
return true;
case M5OP_WAKE_CPU:
@@ -180,7 +170,7 @@
return true;
case M5OP_INIT_PARAM:
-result = invokeSimcall(tc, initParam);
+result = invokeSimcall(tc, initParam);
return true;
case M5OP_LOAD_SYMBOL:
@@ -204,11 +194,11 @@
return true;
case M5OP_WRITE_FILE:
-result = invokeSimcall(tc, writefile);
+result = invokeSimcall(tc, writefile);
return true;
case M5OP_READ_FILE:
-result = invokeSimcall(tc, readfile);
+result = invokeSimcall(tc, readfile);
return true;
case M5OP_DEBUG_BREAK:
@@ -262,6 +252,21 @@
}
}
+template
+bool
+pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
+{
+return pseudoInstWork(tc, func, result);
+}
+
+template
+bool
+pseudoInst(ThreadContext *tc, uint8_t func)
+{
+uint64_t result;
+return pseudoInstWork(tc, func, result);
+}
+
} // namespace PseudoInst
#endif // __SIM_PSEUDO_INST_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4a53bc0a27e5214a26ef1a100c99948ca95418d
Gerrit-Change-Number: 28289
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-CC: Earl Ou
Gerrit-CC: Yu-hsin Wang
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: DRAM changes in gem5-20 RELEASE-NOTES.md
Hello Wendy Elsasser, Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28927 to review the following change. Change subject: misc: DRAM changes in gem5-20 RELEASE-NOTES.md .. misc: DRAM changes in gem5-20 RELEASE-NOTES.md Change-Id: I5717480876d0a679cf932da271187618decdadef Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-by: Wendy Elsasser --- M RELEASE-NOTES.md 1 file changed, 6 insertions(+), 0 deletions(-) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index d86a48b..7d26721 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -11,3 +11,9 @@ * Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V. * Implemented ARMv8.3-CompNum, SIMD complex number extension * Support for Arm Trusted Firmware + u-boot with the new VExpress_GEM5_Foundation platform +* Changes in the DRAM Controller: +1) Added support for verifying available command bandwidth +2) Added support for multi-cycle commands +3) Added new timing parameters +4) Added ability to interleave bursts +5) Added LPDDR5 configurations -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28927 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I5717480876d0a679cf932da271187618decdadef Gerrit-Change-Number: 28927 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Wendy Elsasser Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Arm architectural extensions in gem5-20 RELEASE-NOTES.md
Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28908 to review the following change. Change subject: misc: Arm architectural extensions in gem5-20 RELEASE-NOTES.md .. misc: Arm architectural extensions in gem5-20 RELEASE-NOTES.md Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris --- M RELEASE-NOTES.md 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 6f80906..8ea08d8 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -9,3 +9,4 @@ * Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules. * Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible. * Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V. +* Implemented ARMv8.3-CompNum, SIMD complex number extension -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28908 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77 Gerrit-Change-Number: 28908 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: misc: Arm TFA support in gem5-20 RELEASE-NOTES.md
Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/28909 to review the following change. Change subject: misc: Arm TFA support in gem5-20 RELEASE-NOTES.md .. misc: Arm TFA support in gem5-20 RELEASE-NOTES.md Change-Id: Ib48d458acc2c79ce0c603b24a32c7a0c43f4965a Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris --- M RELEASE-NOTES.md 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 8ea08d8..d86a48b 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -10,3 +10,4 @@ * Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible. * Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V. * Implemented ARMv8.3-CompNum, SIMD complex number extension +* Support for Arm Trusted Firmware + u-boot with the new VExpress_GEM5_Foundation platform -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28909 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: Ib48d458acc2c79ce0c603b24a32c7a0c43f4965a Gerrit-Change-Number: 28909 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Fixes for mremap
Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28907 )
Change subject: sim: Fixes for mremap
..
sim: Fixes for mremap
Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redudnant mapRegion as remapRegion covers
its functionality.
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
---
M src/sim/mem_state.cc
M src/sim/syscall_emul.hh
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/sim/mem_state.cc b/src/sim/mem_state.cc
index 42d3781..f998fff 100644
--- a/src/sim/mem_state.cc
+++ b/src/sim/mem_state.cc
@@ -369,6 +369,7 @@
new_start_addr);
start_addr += _pageBytes;
+new_start_addr += _pageBytes;
/**
* The regions need to always be page-aligned otherwise the while
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..290c48e 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1177,7 +1177,6 @@
warn("returning %08p as start\n", new_start);
p->memState->remapRegion(start, new_start, old_length);
-p->memState->mapRegion(new_start, new_length, "remapped");
return new_start;
}
}
--
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Gerrit-Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
Gerrit-Change-Number: 28907
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba
Gerrit-MessageType: newchange
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[gem5-dev] GCB status
Hi Bobby, It seems like we are just using kokoro now as CI platform. Is this intended? (What happened with GCB?) Kind Regards Giacomo IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: scons: Update python-config flags for python3.8
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28687 )
Change subject: scons: Update python-config flags for python3.8
..
scons: Update python-config flags for python3.8
Starting in python 3.8 the python3-config utility requires the --embed
flag to output -lpython3.8. Without this flag, gem5 won't link to the
python library.
More details: https://bugs.python.org/issue36721
https://github.com/python/cpython/pull/13500
Change-Id: Id9c63577dcd2defa7ae62cc32e042c4a245e7082
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28687
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M SConstruct
1 file changed, 16 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index ba4affa..b7608a8 100755
--- a/SConstruct
+++ b/SConstruct
@@ -97,7 +97,7 @@
import SCons.Node
import SCons.Node.FS
-from m5.util import compareVersions, readCommand
+from m5.util import compareVersions, readCommand, readCommandWithReturn
help_texts = {
"options" : "",
@@ -683,8 +683,21 @@
# Read the linker flags and split them into libraries and other link
# flags. The libraries are added later through the call the CheckLib.
-py_ld_flags = readCommand([python_config, '--ldflags'],
-exception='').split()
+# Note: starting in Python 3.8 the --embed flag is required to get the
+# -lpython3.8 linker flag
+retcode, cmd_stdout = readCommandWithReturn(
+[python_config, '--ldflags', '--embed'], exception='')
+if retcode != 0:
+# If --embed isn't detected then we're running python <3.8
+retcode, cmd_stdout = readCommandWithReturn(
+[python_config, '--ldflags'], exception='')
+
+# Checking retcode again
+if retcode != 0:
+error("Failing on python-config --ldflags command")
+
+py_ld_flags = cmd_stdout.split()
+
py_libs = []
for lib in py_ld_flags:
if not lib.startswith('-l'):
--
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Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Id9c63577dcd2defa7ae62cc32e042c4a245e7082
Gerrit-Change-Number: 28687
Gerrit-PatchSet: 5
Gerrit-Owner: Jason Lowe-Power
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: scons: Add readCommandWithReturn helper
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28847 )
Change subject: scons: Add readCommandWithReturn helper
..
scons: Add readCommandWithReturn helper
In this way it will be possible to reliably catch any error
in the command execution which is not raising an exception
to Popen.
Change-Id: I4dc15648423f9bb8e8a470d97291dbd065c48eba
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28847
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/m5/util/__init__.py
1 file changed, 26 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/util/__init__.py b/src/python/m5/util/__init__.py
index 98a7a08..c59f40a 100644
--- a/src/python/m5/util/__init__.py
+++ b/src/python/m5/util/__init__.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016 ARM Limited
+# Copyright (c) 2016, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -177,9 +177,16 @@
line += item
print(line)
-def readCommand(cmd, **kwargs):
-"""run the command cmd, read the results and return them
-this is sorta like `cmd` in shell"""
+def readCommandWithReturn(cmd, **kwargs):
+"""
+run the command cmd, read the results and return them
+this is sorta like `cmd` in shell
+
+:param cmd: command to run with Popen
+:type cmd: string, list
+:returns: pair consisting on Popen retcode and the command stdout
+:rtype: (int, string)
+"""
from subprocess import Popen, PIPE, STDOUT
if isinstance(cmd, str):
@@ -196,10 +203,23 @@
subp = Popen(cmd, **kwargs)
except Exception as e:
if no_exception:
-return exception
+return -1, exception
raise
-return subp.communicate()[0].decode('utf-8')
+output = subp.communicate()[0].decode('utf-8')
+return subp.returncode, output
+
+def readCommand(cmd, **kwargs):
+"""
+run the command cmd, read the results and return them
+this is sorta like `cmd` in shell
+
+:param cmd: command to run with Popen
+:type cmd: string, list
+:returns: command stdout
+:rtype: string
+"""
+return readCommandWithReturn(cmd, **kwargs)[1]
def makeDir(path):
"""Make a directory if it doesn't exist. If the path does exist,
--
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Gerrit-Change-Id: I4dc15648423f9bb8e8a470d97291dbd065c48eba
Gerrit-Change-Number: 28847
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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