[gem5-dev] Change in gem5/gem5[develop]: arm: Don't use pseudo instructions to implement regular instructions.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27790 )
Change subject: arm: Don't use pseudo instructions to implement regular
instructions.
..
arm: Don't use pseudo instructions to implement regular instructions.
Some ARM instructions were using quiesce and quiesceSkip pseudo
instruction bodies instead of implementing the one line of each of those
functions themselves. This creates two problems. First, it adds an
artificial depedence on the pseudo instruction implementations. Second,
it would confusing cause pseudo instruction DPRINTFs to fire when normal
instructions were executing.
This change simply replaces the calls with their targets one line
implementation, with some very minor duplication from multiple call
sights factored out into a local variable.
Change-Id: I596eafd8714227fa7f69edd542108598c9809b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27790
Reviewed-by: Giacomo Travaglini
Reviewed-by: Jason Lowe-Power
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/templates/pred.isa
2 files changed, 13 insertions(+), 9 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index b2f4591..64bf791 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -721,18 +721,19 @@
// WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
ThreadContext *tc = xc->tcBase();
+Tick next_cycle = tc->getCpuPtr()->nextCycle();
if (SevMailbox == 1) {
SevMailbox = 0;
-PseudoInst::quiesceSkip(tc);
+tc->quiesceTick(next_cycle + 1);
} else if (tc->getCpuPtr()->getInterruptController(
tc->threadId())->checkInterrupts()) {
-PseudoInst::quiesceSkip(tc);
+tc->quiesceTick(next_cycle + 1);
} else {
fault = trapWFx(tc, cpsr, scr, true);
if (fault == NoFault) {
-PseudoInst::quiesce(tc);
+tc->quiesce();
} else {
-PseudoInst::quiesceSkip(tc);
+tc->quiesceTick(next_cycle + 1);
}
}
'''
@@ -760,15 +761,16 @@
ThreadContext *tc = xc->tcBase();
auto *ic = dynamic_cast(
tc->getCpuPtr()->getInterruptController(tc->threadId()));
+Tick next_cycle = tc->getCpuPtr()->nextCycle();
if (ic->checkWfiWake(hcr, cpsr, scr)) {
-PseudoInst::quiesceSkip(tc);
+tc->quiesceTick(next_cycle + 1);
} else {
fault = trapWFx(tc, cpsr, scr, false);
if (fault == NoFault) {
-PseudoInst::quiesce(tc);
+tc->quiesce();
ArmSystem::callSetStandByWfi(tc);
} else {
-PseudoInst::quiesceSkip(tc);
+tc->quiesceTick(next_cycle + 1);
}
}
tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
diff --git a/src/arch/arm/isa/templates/pred.isa
b/src/arch/arm/isa/templates/pred.isa
index ee48f90..9b08fc3 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -206,7 +206,8 @@
}
} else {
xc->setPredicate(false);
-PseudoInst::quiesceSkip(xc->tcBase());
+ThreadContext *tc = xc->tcBase();
+tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1);
}
return fault;
@@ -233,7 +234,8 @@
} else {
xc->setPredicate(false);
%(pred_fixup)s;
-PseudoInst::quiesceSkip(xc->tcBase());
+ThreadContext *tc = xc->tcBase();
+tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1);
}
return fault;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I596eafd8714227fa7f69edd542108598c9809b11
Gerrit-Change-Number: 27790
Gerrit-PatchSet: 19
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Verify number of CPUs when restoring Generic Timer Cpts.
Richard Cooper has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30576 )
Change subject: dev-arm: Verify number of CPUs when restoring Generic Timer
Cpts.
..
dev-arm: Verify number of CPUs when restoring Generic Timer Cpts.
When restoring a checkpoint containing a generic timer, the checkpoint
expects to connect the timer to the same number of CPUs that were
present when the checkpoint was taken. If the number of CPUs in the
new simulation is different, deserialization will fail. In the case
that the number of CPUs expected by the checkpoint is greater than the
number of CPUs present, this will cause a segmentation fault caused by
reading off the end of the list of Thread Contexts.
This commit fixes the problem by checking the number of CPUs present
in the simulation matches the number of CPUs expected by the generic
timer checkpoint. If there is a mismatch, a fatal error is triggered
with an informative message to the user.
Change-Id: Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6
Reviewed-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30576
Tested-by: kokoro
Maintainer: Giacomo Travaglini
---
M src/dev/arm/generic_timer.cc
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 4f92dac..1b75728 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -415,6 +415,13 @@
cpu_count = OLD_CPU_MAX;
}
+if (cpu_count != system.threads.size()) {
+fatal("The simulated system has been initialized with %d CPUs, "
+ "but the Generic Timer checkpoint expects %d CPUs. Consider "
+ "restoring the checkpoint specifying %d CPUs.",
+ system.threads.size(), cpu_count, cpu_count);
+}
+
for (int i = 0; i < cpu_count; ++i) {
CoreTimers (getTimers(i));
core.unserializeSection(cp, csprintf("pe_implementation%d", i));
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30576
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6
Gerrit-Change-Number: 30576
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Cooper
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Clarify the meaning of shared_backstore param
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31034 )
Change subject: mem: Clarify the meaning of shared_backstore param
..
mem: Clarify the meaning of shared_backstore param
Change-Id: I36bb2b0633aed4e00db2f213a84a172279c10c78
---
M src/sim/System.py
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/sim/System.py b/src/sim/System.py
index 36b7e3f..e028f48 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -78,7 +78,9 @@
# I/O bridge or cache
mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main
memory")
-shared_backstore = Param.String("", "backstore's shmem segment
filename")
+shared_backstore = Param.String("", "backstore's shmem segment
filename, "
+"use to directly address the backstore from another host-OS
process. "
+"Leave this empty to unset the MAP_SHARED flag.")
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I36bb2b0633aed4e00db2f213a84a172279c10c78
Gerrit-Change-Number: 31034
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented
Ciro Santilli has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30934 ) Change subject: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented .. arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented The feature was implemented at: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28 Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30934 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- M src/arch/arm/ArmISA.py 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index f701f7d..b2513f7 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013, 2015-2019 ARM Limited +# Copyright (c) 2012-2013, 2015-2020 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -101,8 +101,8 @@ id_aa64isar0_el1 = Param.UInt64(0x, "AArch64 Instruction Set Attribute Register 0") -# GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1 | FCMA -id_aa64isar1_el1 = Param.UInt64(0x01010010, +# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1 +id_aa64isar1_el1 = Param.UInt64(0x01011010, "AArch64 Instruction Set Attribute Register 1") # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30934 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84 Gerrit-Change-Number: 30934 Gerrit-PatchSet: 2 Gerrit-Owner: Ciro Santilli Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Avoid passing ReExec 'faults' on CPU tracing interface
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30554 )
Change subject: cpu-o3: Avoid passing ReExec 'faults' on CPU tracing
interface
..
cpu-o3: Avoid passing ReExec 'faults' on CPU tracing interface
The O3 model uses ReExec faults to flush the pipeline and restart
after a memory ordering violation, e.g. due to an incoming snoop.
These, just like branch mispredict flushes, are not architectural
faults but micro-architectural events, and should therefore not
show up on the instruction tracing interface.
This adds a check on faulting instructions in commit, to verify
if the instruction faulted due to ReExec, to avoid tracing it.
Change-Id: I1d3eaffb0ff22411e0e16a69ef07961924c88c10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30554
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/cpu/o3/commit_impl.hh
1 file changed, 5 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 4f467e9..49b40e3 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1259,7 +1259,11 @@
"[tid:%i] [sn:%llu] Committing instruction with fault\n",
tid, head_inst->seqNum);
if (head_inst->traceData) {
-if (DTRACE(ExecFaulting)) {
+// We ignore ReExecution "faults" here as they are not real
+// (architectural) faults but signal flush/replays.
+if (DTRACE(ExecFaulting)
+&& dynamic_cast(inst_fault.get()) == nullptr) {
+
head_inst->traceData->setFaulting(true);
head_inst->traceData->setFetchSeq(head_inst->seqNum);
head_inst->traceData->setCPSeq(thread[tid]->numOp);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1d3eaffb0ff22411e0e16a69ef07961924c88c10
Gerrit-Change-Number: 30554
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix routeToHyp conditions for Excp Type
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30620 )
Change subject: arch-arm: Fix routeToHyp conditions for Excp Type
..
arch-arm: Fix routeToHyp conditions for Excp Type
Change-Id: I8eadd8e1f8c53d5e61969b492d9f2cbd12110188
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30620
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/faults.cc
1 file changed, 10 insertions(+), 43 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ecc9e4d..743e08d 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -884,17 +884,8 @@
bool
SupervisorCall::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if in Hyp mode then stay in Hyp mode
-toHyp = scr.ns && (cpsr.mode == MODE_HYP);
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
}
ExceptionClass
@@ -1028,15 +1019,8 @@
bool
SupervisorTrap::routeToHyp(ThreadContext *tc) const
{
-bool toHyp = false;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge;
}
uint32_t
@@ -1323,6 +1307,7 @@
// if in Hyp mode then stay in Hyp mode
toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1) && hcr.tge;
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
@@ -1384,6 +1369,7 @@
// if in Hyp mode then stay in Hyp mode
toHyp = scr.ns && (currEL(tc) == EL2);
+toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
// otherwise, check whether to take to Hyp mode through Hyp Trap vector
toHyp |= (stage2 ||
((currEL(tc) != EL2) &&
@@ -1484,15 +1470,9 @@
bool
Interrupt::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.imo));
}
bool
@@ -1523,15 +1503,9 @@
bool
FastInterrupt::routeToHyp(ThreadContext *tc) const
{
-bool toHyp;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-// Determine whether IRQs are routed to Hyp mode.
-toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
-(cpsr.mode == MODE_HYP);
-return toHyp;
+return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
}
bool
@@ -1571,15 +1545,8 @@
bool
PCAlignmentFault::routeToHyp(ThreadContext *tc) const
{
-bool toHyp = false;
-
-SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
-// if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
-toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
-return toHyp;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
}
SPAlignmentFault::SPAlignmentFault()
@@ -1590,7 +1557,7 @@
{
assert(from64);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
-return EL2Enabled(tc) && hcr.tge==1;
+return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
}
SystemError::SystemError()
--
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Gerrit-Change-Number: 30620
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer:
