[gem5-dev] Change in gem5/gem5[develop]: tests: fix .testsignore for long regression

2020-07-19 Thread mike upton (Gerrit) via gem5-dev
mike upton has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31594 )



Change subject: tests: fix .testsignore for long regression
..

tests: fix .testsignore for long regression

removed 2 tests from long regression to get nightly tests to pass
fixed .testignore, -arch64 changed to -aarch64, this enables running on ARM  
hw


Change-Id: Ic8456fef83dfba3417d1edcf62e90873d197d3d6
---
M tests/gem5/.testignore
1 file changed, 26 insertions(+), 24 deletions(-)



diff --git a/tests/gem5/.testignore b/tests/gem5/.testignore
index c76d7c6..405f005 100644
--- a/tests/gem5/.testignore
+++ b/tests/gem5/.testignore
@@ -110,24 +110,24 @@
 test-hello-linux-TimingSimpleCPU-MIPS-x86_64-opt
 test-hello-linux-AtomicSimpleCPU-MIPS-x86_64-opt
 test-hello-linux-DerivO3CPU-MIPS-x86_64-opt
-test-hello-linux-MinorCPU-RISCV-arch64-debug
-test-hello-linux-TimingSimpleCPU-SPARC-arch64-debug
-test-hello-linux-AtomicSimpleCPU-SPARC-arch64-debug
-test-hello-linux-TimingSimpleCPU-MIPS-arch64-debug
-test-hello-linux-AtomicSimpleCPU-MIPS-arch64-debug
-test-hello-linux-DerivO3CPU-MIPS-arch64-debug
-test-hello-linux-MinorCPU-RISCV-arch64-fast
-test-hello-linux-TimingSimpleCPU-SPARC-arch64-fast
-test-hello-linux-AtomicSimpleCPU-SPARC-arch64-fast
-test-hello-linux-TimingSimpleCPU-MIPS-arch64-fast
-test-hello-linux-AtomicSimpleCPU-MIPS-arch64-fast
-test-hello-linux-DerivO3CPU-MIPS-arch64-fast
-test-hello-linux-MinorCPU-RISCV-arch64-opt
-test-hello-linux-TimingSimpleCPU-SPARC-arch64-opt
-test-hello-linux-AtomicSimpleCPU-SPARC-arch64-opt
-test-hello-linux-TimingSimpleCPU-MIPS-arch64-opt
-test-hello-linux-AtomicSimpleCPU-MIPS-arch64-opt
-test-hello-linux-DerivO3CPU-MIPS-arch64-opt
+test-hello-linux-MinorCPU-RISCV-aarch64-debug
+test-hello-linux-TimingSimpleCPU-SPARC-aarch64-debug
+test-hello-linux-AtomicSimpleCPU-SPARC-aarch64-debug
+test-hello-linux-TimingSimpleCPU-MIPS-aarch64-debug
+test-hello-linux-AtomicSimpleCPU-MIPS-aarch64-debug
+test-hello-linux-DerivO3CPU-MIPS-aarch64-debug
+test-hello-linux-MinorCPU-RISCV-aarch64-fast
+test-hello-linux-TimingSimpleCPU-SPARC-aarch64-fast
+test-hello-linux-AtomicSimpleCPU-SPARC-aarch64-fast
+test-hello-linux-TimingSimpleCPU-MIPS-aarch64-fast
+test-hello-linux-AtomicSimpleCPU-MIPS-aarch64-fast
+test-hello-linux-DerivO3CPU-MIPS-aarch64-fast
+test-hello-linux-MinorCPU-RISCV-aarch64-opt
+test-hello-linux-TimingSimpleCPU-SPARC-aarch64-opt
+test-hello-linux-AtomicSimpleCPU-SPARC-aarch64-opt
+test-hello-linux-TimingSimpleCPU-MIPS-aarch64-opt
+test-hello-linux-AtomicSimpleCPU-MIPS-aarch64-opt
+test-hello-linux-DerivO3CPU-MIPS-aarch64-opt
 test-hello-linux-MinorCPU-RISCV-i386-debug
 test-hello-linux-TimingSimpleCPU-SPARC-i386-debug
 test-hello-linux-AtomicSimpleCPU-SPARC-i386-debug
@@ -152,15 +152,17 @@
 test-atomic-TimingSimpleCPU-SPARC-x86_64-debug
 test-atomic-DerivO3CPU-SPARC-x86_64-fast
 test-atomic-TimingSimpleCPU-SPARC-x86_64-fast
-test-atomic-DerivO3CPU-SPARC-arch64-opt
-test-atomic-TimingSimpleCPU-SPARC-arch64-opt
-test-atomic-DerivO3CPU-SPARC-arch64-debug
-test-atomic-TimingSimpleCPU-SPARC-arch64-debug
-test-atomic-DerivO3CPU-SPARC-arch64-fast
-test-atomic-TimingSimpleCPU-SPARC-arch64-fast
+test-atomic-DerivO3CPU-SPARC-aarch64-opt
+test-atomic-TimingSimpleCPU-SPARC-aarch64-opt
+test-atomic-DerivO3CPU-SPARC-aarch64-debug
+test-atomic-TimingSimpleCPU-SPARC-aarch64-debug
+test-atomic-DerivO3CPU-SPARC-aarch64-fast
+test-atomic-TimingSimpleCPU-SPARC-aarch64-fast
 test-atomic-DerivO3CPU-SPARC-i386-opt
 test-atomic-TimingSimpleCPU-SPARC-i386-opt
 test-atomic-DerivO3CPU-SPARC-i386-debug
 test-atomic-TimingSimpleCPU-SPARC-i386-debug
 test-atomic-DerivO3CPU-SPARC-i386-fast
 test-atomic-TimingSimpleCPU-SPARC-i386-fast
+realview-o3-checker-ARM-x86_64-opt
+realview64-o3-checker-ARM-x86_64-opt

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic8456fef83dfba3417d1edcf62e90873d197d3d6
Gerrit-Change-Number: 31594
Gerrit-PatchSet: 1
Gerrit-Owner: mike upton 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Implement GDB XML target description for MIPS

2020-07-19 Thread Boris Shingarov (Gerrit) via gem5-dev
Boris Shingarov has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31574 )



Change subject: arch-mips: Implement GDB XML target description for MIPS
..

arch-mips: Implement GDB XML target description for MIPS

Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
---
A ext/gdb-xml/mips.xml
M src/arch/mips/SConscript
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
4 files changed, 123 insertions(+), 2 deletions(-)



diff --git a/ext/gdb-xml/mips.xml b/ext/gdb-xml/mips.xml
new file mode 100644
index 000..23133d7
--- /dev/null
+++ b/ext/gdb-xml/mips.xml
@@ -0,0 +1,94 @@
+
+
+
+
+
+ mips
+ 
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
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+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
+  
+  
+  
+  
+  
+  
+
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
+  
+  
+ 
+
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index cac589f..d8771de 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,7 @@
 # -*- mode:python -*-

 # Copyright (c) 2004-2006 The Regents of The University of Michigan
+# Copyright (c) 2020 LabWare
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -50,3 +51,5 @@
 DebugFlag('MipsPRA')

 ISADesc('isa/main.isa')
+
+GdbXml('mips.xml', 'gdb_xml_mips')
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 48138ee..bd9a40f 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2010 ARM Limited
  * All rights reserved
@@ -136,6 +136,7 @@
 #include 

 #include "arch/mips/decoder.hh"
+#include "blobs/gdb_xml_mips.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
@@ -201,3 +202,20 @@
 {
 return 
 }
+
+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string  
)

+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_mips),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 407a557..2119d8e 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2007 The Regents of The University of Michigan
  * All rights reserved.
@@ -79,6 +79,12 @@
   public:
 RemoteGDB(System *_system, ThreadContext *tc, int _port);
 BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string  
);

 };

 } // namespace MipsISA

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Gerrit-Change-Number: 31574
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov 
Gerrit-MessageType: newchange
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