[gem5-dev] Jenkins build is back to normal : Compiler-Checks #24

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See 

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[gem5-dev] Re: gem5 python version?

[Jason Lowe-Power via gem5-dev]

Hi Mike,

I believe we've decided to drop 2.7 support after the 20.1 release. This
hasn't been checked into develop, yet, but I think it's a safe assumption
that develop now only supports python3.

Cheers,
Jason

On Sun, Sep 20, 2020 at 10:52 AM mike upton via gem5-dev 
wrote:

>
> Do we still support python2.7?
>
> I am adding some functionality and it is cleanest in python3, but the code
> will fail if running in python2.
>
>
> thanks
>
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[gem5-dev] gem5 python version?

[mike upton via gem5-dev]

Do we still support python2.7?

I am adding some functionality and it is cleanest in python3, but the code
will fail if running in python2.


thanks
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,sim: Route system calls through the workload.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33282 )


Change subject: arch,cpu,sim: Route system calls through the workload.
..

arch,cpu,sim: Route system calls through the workload.

System calls should now be requested from the workload directly and not
routed through ExecContext or ThreadContext interfaces. That removes a
major special case for SE mode from those interfaces.

For now, when the SE workload gets a request for a system call, it
dispatches it to the appropriate Process object. In the future, the
ISA specific Workload subclasses will be responsible for handling system
calls and not the Process classes.

For simplicity, the Workload syscall() method is defined in the base
class but will panic everywhere except when SEWorkload overrides it. In
the future, this mechanism will turn into a way to request generic
services from the workload which are not necessarily system calls. For
instance, it could be a way to request handling of a page fault without
having to have another PseudoInst just for that purpose.

Change-Id: I18d36d64c54adf4f4f17a62e7e006ff2fc0b22f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33282
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/faults.cc
M src/arch/riscv/faults.cc
M src/arch/sparc/linux/process.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_state.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M src/sim/faults.cc
M src/sim/pseudo_inst.cc
M src/sim/se_workload.cc
M src/sim/se_workload.hh
M src/sim/workload.hh
21 files changed, 21 insertions(+), 88 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 56e1814..c590d78 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -865,7 +865,7 @@

 // As of now, there isn't a 32 bit thumb version of this instruction.
 assert(!machInst.bigThumb);
-tc->syscall();
+tc->getSystemPtr()->workload->syscall(tc);

 // Advance the PC since that won't happen automatically.
 PCState pc = tc->pcState();
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 7a1c7bd..ac4c582 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -194,7 +194,7 @@
 void
 SyscallFault::invokeSE(ThreadContext *tc, const StaticInstPtr )
 {
-tc->syscall();
+tc->getSystemPtr()->workload->syscall(tc);
 }

 } // namespace RiscvISA
diff --git a/src/arch/sparc/linux/process.cc  
b/src/arch/sparc/linux/process.cc

index 79bbaee..ce051ba 100644
--- a/src/arch/sparc/linux/process.cc
+++ b/src/arch/sparc/linux/process.cc
@@ -92,7 +92,7 @@
 {
 switch (trapNum) {
   case 0x10: //Linux 32 bit syscall trap
-tc->syscall();
+tc->getSystemPtr()->workload->syscall(tc);
 break;
   default:
 SparcProcess::handleTrap(trapNum, tc);
@@ -129,7 +129,7 @@
 switch (trapNum) {
   // case 0x10: // Linux 32 bit syscall trap
   case 0x6d: // Linux 64 bit syscall trap
-tc->syscall();
+tc->getSystemPtr()->workload->syscall(tc);
 break;
   case 0x6e: // Linux 64 bit getcontext trap
 getContext(tc);
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index f2395d7..f5d7834 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -610,9 +610,6 @@
 /

 void wakeup(ThreadID tid) override { }
-// Assume that the normal CPU's call to syscall was successful.
-// The checker's state would have already been updated by the syscall.
-void syscall() override { }

 void
 handleError()
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index b5a974b..d07de62 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -171,9 +171,6 @@
 actualTC->connectMemPorts(tc);
 }

-/** Executes a syscall in SE mode. */
-void syscall() override { return actualTC->syscall(); }
-
 Status status() const override { return actualTC->status(); }

 void
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index cfef3c3..b1cdbd8 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -300,18 +300,6 @@

 /** @} */

-/**
- * @{
- * @name SysCall Emulation Interfaces
- */
-
-/**
- * Executes a syscall.
- */
-virtual void syscall() = 0;
-
-/** @} */
-
 /** Returns a pointer to the ThreadContext. */
 virtual 

[gem5-dev] Change in gem5/gem5[develop]: sim: Create a Workload object for SE mode.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33278 )


Change subject: sim: Create a Workload object for SE mode.
..

sim: Create a Workload object for SE mode.

The workload object is still optional for the sake of compatibility,
even though it probably shouldn't be in the long term. If a simulation
is just a collection of components with nothing in particular running on
it, for instance driven by a traffic generator, should it even have a
System object in the first place?

Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33278
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M configs/dram/low_power_sweep.py
M configs/example/apu_se.py
M configs/example/arm/starter_se.py
M configs/example/hmc_hello.py
M configs/example/se.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M src/sim/SConscript
M src/sim/System.py
M src/sim/Workload.py
A src/sim/se_workload.cc
A src/sim/se_workload.hh
M tests/configs/gpu-ruby.py
M tests/gem5/cpu_tests/run.py
M tests/gem5/m5threads_test_atomic/atomic_system.py
20 files changed, 155 insertions(+), 5 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/dram/low_power_sweep.py  
b/configs/dram/low_power_sweep.py

index 292b0fa..a9f7057 100644
--- a/configs/dram/low_power_sweep.py
+++ b/configs/dram/low_power_sweep.py
@@ -93,6 +93,8 @@
voltage_domain =
VoltageDomain(voltage = '1V'))

+system.workload = SEWorkload()
+
 # We are fine with 256 MB memory for now.
 mem_range = AddrRange('256MB')
 # Start address is 0
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 03418c3..077ce4c 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -500,7 +500,8 @@
 system = System(cpu = cpu_list,
 mem_ranges = [AddrRange(options.mem_size)],
 cache_line_size = options.cacheline_size,
-mem_mode = mem_mode)
+mem_mode = mem_mode,
+workload = SEWorkload())
 if fast_forward:
 system.future_cpu = future_cpu_list
 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index 0003ce9..d342420 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -171,6 +171,8 @@
   (len(processes), args.num_cores))
 sys.exit(1)

+system.workload = SEWorkload()
+
 # Assign one workload to each CPU
 for cpu, workload in zip(system.cpu_cluster.cpus, processes):
 cpu.workload = workload
diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py
index a682519..706fc2b 100644
--- a/configs/example/hmc_hello.py
+++ b/configs/example/hmc_hello.py
@@ -50,6 +50,7 @@
 options = parser.parse_args()
 # create the system we are going to simulate
 system = System()
+system.workload = SEWorkload()
 # use timing mode for the interaction between master-slave ports
 system.mem_mode = 'timing'
 # set the clock fequency of the system
diff --git a/configs/example/se.py b/configs/example/se.py
index 200a0de..f3fea61 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -173,7 +173,7 @@
 mem_mode = test_mem_mode,
 mem_ranges = [AddrRange(options.mem_size)],
 cache_line_size = options.cacheline_size,
-workload = NULL)
+workload = SEWorkload())

 if numThreads > 1:
 system.multi_thread = True
diff --git a/configs/learning_gem5/part1/simple.py  
b/configs/learning_gem5/part1/simple.py

index 22b2cf7..cb785b6 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -94,6 +94,8 @@
 binary = os.path.join(thispath, '../../../',
   'tests/test-progs/hello/bin/', isa, 'linux/hello')

+system.workload = SEWorkload()
+
 # Create a process for a simple "Hello World" application
 process = Process()
 # Set the command
diff --git a/configs/learning_gem5/part1/two_level.py  
b/configs/learning_gem5/part1/two_level.py

index 53e1137..50d1d5f 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -137,6 +137,8 @@
 system.mem_ctrl.dram.range = system.mem_ranges[0]
 system.mem_ctrl.port = system.membus.master

+system.workload = SEWorkload()
+
 # Create a process for a simple "Hello World" application
 process = Process()
 # Set the 

[gem5-dev] Change in gem5/gem5[develop]: dev: Stop using the OS page size in the IDE controller.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34178 )


Change subject: dev: Stop using the OS page size in the IDE controller.
..

dev: Stop using the OS page size in the IDE controller.

This size was used to break up DMA transactions so that a single
transaction would not cross a page boundary. This was because on Alpha,
there was an actual page table which translated between PCI and DMA
address spaces. On all currently implemented systems, the mapping is
simply to add a scalar offset, so it's not possible for a legal region
of memory to be contiguous in one space but not in the other.

Additionally, if it *was* possible for there to be a mismatch, it was
only coincidence that Alpha used a page table which had the same sized
pages as it normally used. There is no requirement that there even would
be fixed sized pages in the first place.

To avoid this artificial dependency between the IDE controller and the
ISA, this change simply changes the chunk size for DMA accesses to 4K.
That's the page size at least on x86 and probably other architectures,
and will be a pretty close approximation of the previous behavior.

It's possible that even having this chunking in the first place is
unnecessary and functionally useless, but there are some checks which
happen between chunks, and changing how big they are would change the
frequency of those checks. For instance, the controller/disk may not
notice in the same amount of time if a DMA was cancelled somehow.

Change-Id: I1ec840d1f158c3faa31ba0184458b69bf654c252
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34178
Reviewed-by: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/storage/ide_ctrl.cc
M src/dev/storage/ide_disk.cc
M src/dev/storage/ide_disk.hh
3 files changed, 10 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 47cdd10..5efa42b 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -120,7 +120,8 @@
 panic("IDE controllers support a maximum "
   "of 4 devices attached!\n");
 }
-params()->disks[i]->setController(this, sys->getPageBytes());
+// Arbitrarily set the chunk size to 4K.
+params()->disks[i]->setController(this, 4 * 1024);
 }

 primary.select(false);
diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc
index e97e23b..57fa076 100644
--- a/src/dev/storage/ide_disk.cc
+++ b/src/dev/storage/ide_disk.cc
@@ -435,7 +435,7 @@
 // clear out the data buffer
 memset(dataBuffer, 0, MAX_DMA_SIZE);
 dmaReadCG = new ChunkGenerator(curPrd.getBaseAddr(),
-curPrd.getByteCount(), pageBytes);
+curPrd.getByteCount(), chunkBytes);

 }
 if (ctrl->dmaPending() || ctrl->drainState() != DrainState::Running) {
@@ -447,7 +447,7 @@
 , dataBuffer + dmaReadCG->complete());
 dmaReadBytes += dmaReadCG->size();
 dmaReadTxs++;
-if (dmaReadCG->size() == pageBytes)
+if (dmaReadCG->size() == chunkBytes)
 dmaReadFullPages++;
 dmaReadCG->next();
 } else {
@@ -518,7 +518,7 @@
 if (!dmaWriteCG) {
 // clear out the data buffer
 dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
-curPrd.getByteCount(), pageBytes);
+curPrd.getByteCount(), chunkBytes);
 }
 if (ctrl->dmaPending() || ctrl->drainState() != DrainState::Running) {
 schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
@@ -532,7 +532,7 @@
 curPrd.getByteCount(), curPrd.getEOT());
 dmaWriteBytes += dmaWriteCG->size();
 dmaWriteTxs++;
-if (dmaWriteCG->size() == pageBytes)
+if (dmaWriteCG->size() == chunkBytes)
 dmaWriteFullPages++;
 dmaWriteCG->next();
 } else {
diff --git a/src/dev/storage/ide_disk.hh b/src/dev/storage/ide_disk.hh
index 9f42941..90cbf57 100644
--- a/src/dev/storage/ide_disk.hh
+++ b/src/dev/storage/ide_disk.hh
@@ -239,8 +239,8 @@
 DmaState_t dmaState;
 /** Dma transaction is a read */
 bool dmaRead;
-/** Size of OS pages. */
-Addr pageBytes;
+/** Size of chunks to DMA. */
+Addr chunkBytes;
 /** PRD table base address */
 uint32_t curPrdAddr;
 /** PRD entry */
@@ -283,11 +283,11 @@
  * @param c The IDE controller
  */
 void
-setController(IdeController *c, Addr page_bytes)
+setController(IdeController *c, Addr chunk_bytes)
 {
 panic_if(ctrl, "Cannot change the controller once set!\n");
 ctrl = c;
-pageBytes = page_bytes;
+chunkBytes = chunk_bytes;
 }

 // Device register read/write