[gem5-dev] Change in gem5/gem5[develop]: arch-sparc,misc: Added M5_VAR_USED to SparcProcess var
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/37536 ) Change subject: arch-sparc,misc: Added M5_VAR_USED to SparcProcess var .. arch-sparc,misc: Added M5_VAR_USED to SparcProcess var Compiling sparc/gem5.fast fails without specifying this variable is used. Change-Id: I86aa5c6495de111421458c2b62200ddb2a89076e --- M src/arch/sparc/faults.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 53e7576..b480558 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -814,7 +814,7 @@ Process *p = tc->getProcessPtr(); -SparcProcess *sp = dynamic_cast(p); +M5_VAR_USED SparcProcess *sp = dynamic_cast(p); assert(sp); auto *workload = dynamic_cast*>(tc->getSystemPtr()->workload); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37536 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I86aa5c6495de111421458c2b62200ddb2a89076e Gerrit-Change-Number: 37536 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,misc: Added missing overrides to gpu_thread.hh
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37538 )
Change subject: arch-gcn3,misc: Added missing overrides to gpu_thread.hh
..
arch-gcn3,misc: Added missing overrides to gpu_thread.hh
Compiling GCN3 with clang will result in errors within this change.
Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
---
M src/cpu/testers/gpu_ruby_test/gpu_thread.hh
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
b/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
index 00a69be..c81b421 100644
--- a/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
+++ b/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
@@ -90,8 +90,8 @@
: Event(CPU_Tick_Pri), thread(_thread), desc(_description)
{}
void setDesc(std::string _description) { desc = _description; }
-void process() { thread->wakeup(); }
-const std::string name() { return desc; }
+void process() override { thread->wakeup(); }
+const std::string name() const override { return desc; }
};
GpuThreadEvent threadEvent;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37538
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Gerrit-Change-Number: 37538
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3, misc: Added missing override to protocol_tester.hh
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37537 )
Change subject: arch-gcn3, misc: Added missing override to
protocol_tester.hh
..
arch-gcn3, misc: Added missing override to protocol_tester.hh
Clang will return a missing-override error when compiling X86_GCN4
without this change.
Change-Id: Ib5fd9ba5c27ddc15561198bfc90d27b7599a7923
---
M src/cpu/testers/gpu_ruby_test/protocol_tester.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
b/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
index 6109e5a..1d01fd2 100644
--- a/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
+++ b/src/cpu/testers/gpu_ruby_test/protocol_tester.hh
@@ -117,7 +117,7 @@
typedef AddressManager::Location Location;
typedef AddressManager::Value Value;
-void init();
+void init() override;
RequestorID requestorId() { return _requestorId; };
Port& getPort(const std::string _name,
PortID idx=InvalidPortID) override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37537
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib5fd9ba5c27ddc15561198bfc90d27b7599a7923
Gerrit-Change-Number: 37537
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-cache,misc: Added missing override to operator
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/37535 ) Change subject: mem-cache,misc: Added missing override to operator .. mem-cache,misc: Added missing override to operator Clang compilation was failing in error due to this missing override. Change-Id: I92f1774cd2f1f5ef90ab1d72d038f6c65cba70ad --- M src/mem/cache/tags/super_blk.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mem/cache/tags/super_blk.hh b/src/mem/cache/tags/super_blk.hh index 64d73bd..1ffd0f7 100644 --- a/src/mem/cache/tags/super_blk.hh +++ b/src/mem/cache/tags/super_blk.hh @@ -90,7 +90,7 @@ * variables will remain the same. */ CompressionBlk& operator=(CompressionBlk&& other); -CacheBlk& operator=(CacheBlk&& other); +CacheBlk& operator=(CacheBlk&& other) override; ~CompressionBlk() = default; /** -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37535 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I92f1774cd2f1f5ef90ab1d72d038f6c65cba70ad Gerrit-Change-Number: 37535 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-memorysize-division]: cpu,stats: Fix incorrect stat names of ThreadStateStats
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37455 )
Change subject: cpu,stats: Fix incorrect stat names of ThreadStateStats
..
cpu,stats: Fix incorrect stat names of ThreadStateStats
Previously, ThreadStateStats uses ThreadState::threadId() to
determine the name of the stats. However, in the ThreadState
constructor, ThreadStateStats is initialized before ThreadState
is intialized. As a result, the name of ThreadStateStats has
a wrong ThreadID.
This commit uses ThreadID instead of ThreadState to determine
the name of the stats.
This causes a name collision between ThreadStateStats and
ExecContextStats as both have the name of "thread_[tid]".
Ideally, those stats should be merged to the BaseSimpleCPU.
However, both ThreadStateStats and ExecContextStats have
a stat named numInsts. So, for now, ExecContextStats will
have a name of "exec_context.thread_[tid]", while ThreadStateStats
keeps its name.
Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37455
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
2 files changed, 4 insertions(+), 4 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index a142f57..5e59eb2 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -39,7 +39,7 @@
#include "sim/system.hh"
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
-: numInst(0), numOp(0), threadStats(cpu, this),
+: numInst(0), numOp(0), threadStats(cpu, _tid),
numLoad(0), startNumLoad(0),
_status(ThreadContext::Halted), baseCpu(cpu),
_contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
@@ -119,8 +119,8 @@
}
ThreadState::ThreadStateStats::ThreadStateStats(BaseCPU *cpu,
-ThreadState *thread)
- : Stats::Group(cpu, csprintf("thread%i",
thread->threadId()).c_str()),
+const ThreadID& tid)
+ : Stats::Group(cpu, csprintf("thread_%i", tid).c_str()),
ADD_STAT(numInsts, "Number of Instructions committed"),
ADD_STAT(numOps, "Number of Ops committed"),
ADD_STAT(numMemRefs, "Number of Memory References")
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 3ac473d..53817c8 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -111,7 +111,7 @@
// Defining the stat group
struct ThreadStateStats : public Stats::Group
{
-ThreadStateStats(BaseCPU *cpu, ThreadState *thread);
+ThreadStateStats(BaseCPU *cpu, const ThreadID& thread);
/** Stat for number instructions committed. */
Stats::Scalar numInsts;
/** Stat for number ops (including micro ops) committed. */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37455
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: hotfix-memorysize-division
Gerrit-Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Gerrit-Change-Number: 37455
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests,misc: Added gem5.fast clang compilation to Kokoro
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37478 )
Change subject: tests,misc: Added gem5.fast clang compilation to Kokoro
..
tests,misc: Added gem5.fast clang compilation to Kokoro
Compilation issues in Clang and in compiling gem5.fast are normally
only caught during gem5's weekly, intensive, compilation checks:
http://jenkins.gem5.org/job/Compiler-Checks. The purpose of this change
is to have smaller checks on every commit, reducing the chance of
uncompilable code being submitted.
Change-Id: Idd8c6795ff73e21b1814281c31fc7ae39f09dcc5
---
M tests/jenkins/presubmit.sh
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 68a7320..79fde53 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -37,7 +37,8 @@
set -e
-DOCKER_IMAGE=gcr.io/gem5-test/ubuntu-20.04_all-dependencies
+DOCKER_IMAGE_ALL_DEP=gcr.io/gem5-test/ubuntu-20.04_all-dependencies
+DOCKER_IMAGE_CLANG_COMPILE=gcr.io/gem5-test/clang-version-9
PRESUBMIT_STAGE2=tests/jenkins/presubmit-stage2.sh
# Move the docker base directory to tempfs.
@@ -52,4 +53,13 @@
# Enter a docker image which has all the tools we need, and run the actual
# presubmit tests.
docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm \
-"${DOCKER_IMAGE}" "${PRESUBMIT_STAGE2}"
+"${DOCKER_IMAGE_ALL_DEP}" "${PRESUBMIT_STAGE2}"
+
+# DOCKER_IMAGE_ALL_DEP compiles gem5.opt with GCC. We run a compilation of
+# gem5.fast on the Clang compiler to ensure changes are compilable with the
+# clang compiler. Due to the costs of compilation, we only compile X86
+# at this point. Further compiler tests are carried out nightly as part of
+# our weekly "Compiler Check" tests:
+# http://jenkins.gem5.org/job/Compiler-Checks
+docker run -u $UID:$GID --volume $(pwd):$(pwd) -w $(pwd) --rm \
+"${DOCKER_IMAGE_ALL_DEP}" scons build/X86/gem5.fast -j4
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37478
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idd8c6795ff73e21b1814281c31fc7ae39f09dcc5
Gerrit-Change-Number: 37478
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Explicitly sign-extend simm16
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37495 )
Change subject: arch-gcn3: Explicitly sign-extend simm16
..
arch-gcn3: Explicitly sign-extend simm16
In some instructions, simm16 needs to be sign extended. Previous code
simply casted the simm16 to a 32-bit or 64-bit datatype, however this
didn't actually sign-extend the value.
This patch explicitly calls sext<16> on simm16 whenever it's supposed
to be sign-extended.
Change-Id: I32f02e51fbab220d1a73dc7e68c7410937db21c7
---
M src/arch/gcn3/insts/instructions.cc
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 93fc142..e8951a9 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -1369,7 +1369,7 @@
void
Inst_SOPK__S_MOVK_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
sdst = simm16;
@@ -1393,7 +1393,7 @@
void
Inst_SOPK__S_CMOVK_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
ConstScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1419,7 +1419,7 @@
void
Inst_SOPK__S_CMPK_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
ScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1444,7 +1444,7 @@
void
Inst_SOPK__S_CMPK_LG_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
ScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1469,7 +1469,7 @@
void
Inst_SOPK__S_CMPK_GT_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
ScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1494,7 +1494,7 @@
void
Inst_SOPK__S_CMPK_GE_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
ScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1519,7 +1519,7 @@
void
Inst_SOPK__S_CMPK_LT_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
ScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1544,7 +1544,7 @@
void
Inst_SOPK__S_CMPK_LE_I32::execute(GPUDynInstPtr gpuDynInst)
{
-ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+ScalarRegI32 simm16 = (ScalarRegI32)sext<16>(instData.SIMM16);
ConstScalarOperandI32 src(gpuDynInst, instData.SDST);
ScalarOperandU32 scc(gpuDynInst, REG_SCC);
@@ -1727,7 +1727,7 @@
src.read();
-sdst = src.rawData() + (ScalarRegI32)simm16;
+sdst = src.rawData() + (ScalarRegI32)sext<16>(simm16);
scc = (bits(src.rawData(), 31) == bits(simm16, 15)
&& bits(src.rawData(), 31) != bits(sdst.rawData(), 31)) ? 1 :
0;
@@ -1754,7 +1754,7 @@
sdst.read();
-sdst = sdst.rawData() * (ScalarRegI32)simm16;
+sdst = sdst.rawData() * (ScalarRegI32)sext<16>(simm16);
sdst.write();
}
@@ -3902,7 +3902,7 @@
Addr pc = wf->pc();
ScalarRegI16 simm16 = instData.SIMM16;
-pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
wf->pc(pc);
}
@@ -3948,7 +3948,7 @@
scc.read();
if (!scc.rawData()) {
-pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
}
wf->pc(pc);
@@ -3977,7 +3977,7 @@
scc.read();
if (scc.rawData()) {
-pc = pc + ((ScalarRegI64)simm16 * 4LL) + 4LL;
+pc = pc + ((ScalarRegI64)sext<16>(simm16 * 4LL)) + 4LL;
}
wf->pc(pc);
@@ -4007,7 +4007,7 @@
vcc.read();
if
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix deadlock in VIPERCoalescer
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37477 )
Change subject: mem-ruby: Fix deadlock in VIPERCoalescer
..
mem-ruby: Fix deadlock in VIPERCoalescer
Certain instructions (some atomics and buffer_wbinvl1_vol) deadlock
in the coalescer, where sendTimingReq fails, fails a retry, and then
never retries again.
This fix sets m_cache_inv_pkt to null before calling
completeHitCallback(), as that allows the failed packets to be retried
again.
Change-Id: I4a51c741360f385f8b4c3f2a31a9410f18e095d9
---
M src/mem/ruby/system/VIPERCoalescer.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/system/VIPERCoalescer.cc
b/src/mem/ruby/system/VIPERCoalescer.cc
index 111f9f2..1aea4a3 100644
--- a/src/mem/ruby/system/VIPERCoalescer.cc
+++ b/src/mem/ruby/system/VIPERCoalescer.cc
@@ -269,8 +269,8 @@
if (m_num_pending_invs == 0) {
std::vector pkt_list { m_cache_inv_pkt };
-completeHitCallback(pkt_list);
m_cache_inv_pkt = nullptr;
+completeHitCallback(pkt_list);
}
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37477
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4a51c741360f385f8b4c3f2a31a9410f18e095d9
Gerrit-Change-Number: 37477
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Implement flat_load_sbyte instruction
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37476 )
Change subject: arch-gcn3: Implement flat_load_sbyte instruction
..
arch-gcn3: Implement flat_load_sbyte instruction
Change-Id: I3aa7547a393b9ecb4b3d4d107394c54d690a0ac2
---
M src/arch/gcn3/insts/instructions.cc
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 64f0c36..93fc142 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -39497,17 +39497,61 @@
void
Inst_FLAT__FLAT_LOAD_SBYTE::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (wf->execMask().none()) {
+wf->decVMemInstsIssued();
+wf->decLGKMInstsIssued();
+wf->rdGmReqsInPipe--;
+wf->rdLmReqsInPipe--;
+gpuDynInst->exec_mask = wf->execMask();
+wf->computeUnit->vrf[wf->simdId]->
+scheduleWriteOperandsFromLoad(wf, gpuDynInst);
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->exec_mask = gpuDynInst->wavefront()->execMask();
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+
+addr.read();
+
+calcAddr(gpuDynInst, addr);
+
+if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+gpuDynInst->computeUnit()->globalMemoryPipe
+.issueRequest(gpuDynInst);
+wf->rdGmReqsInPipe--;
+wf->outstandingReqsRdGm++;
+} else {
+fatal("Non global flat instructions not implemented yet.\n");
+}
+
+gpuDynInst->wavefront()->outstandingReqs++;
+gpuDynInst->wavefront()->validateRequestCounters();
}
void
Inst_FLAT__FLAT_LOAD_SBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
{
+initMemRead(gpuDynInst);
} // initiateAcc
void
Inst_FLAT__FLAT_LOAD_SBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
{
+VecOperandI32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] = (VecElemI32)((reinterpret_cast(
+gpuDynInst->d_data))[lane]);
+}
+}
+vdst.write();
}
Inst_FLAT__FLAT_LOAD_USHORT::Inst_FLAT__FLAT_LOAD_USHORT(InFmt_FLAT
*iFmt)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37476
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3aa7547a393b9ecb4b3d4d107394c54d690a0ac2
Gerrit-Change-Number: 37476
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Implement s_setreg_imm32_b32 instruction
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/37475 )
Change subject: arch-gcn3: Implement s_setreg_imm32_b32 instruction
..
arch-gcn3: Implement s_setreg_imm32_b32 instruction
Change-Id: I5383243403156dc17d4997106085a62fb0483fec
---
M src/arch/gcn3/insts/instructions.cc
1 file changed, 23 insertions(+), 0 deletions(-)
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index b501167..64f0c36 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -1847,6 +1847,7 @@
InFmt_SOPK *iFmt)
: Inst_SOPK(iFmt, "s_setreg_imm32_b32")
{
+setFlag(ALU);
} // Inst_SOPK__S_SETREG_IMM32_B32
Inst_SOPK__S_SETREG_IMM32_B32::~Inst_SOPK__S_SETREG_IMM32_B32()
@@ -1860,6 +1861,28 @@
void
Inst_SOPK__S_SETREG_IMM32_B32::execute(GPUDynInstPtr gpuDynInst)
{
+ScalarRegI16 simm16 = instData.SIMM16;
+ScalarRegU32 hwregId = simm16 & 0x3f;
+ScalarRegU32 offset = (simm16 >> 6) & 31;
+ScalarRegU32 size = ((simm16 >> 11) & 31) + 1;
+
+ScalarOperandU32 hwreg(gpuDynInst, hwregId);
+ScalarRegU32 simm32 = extData.imm_u32;
+hwreg.read();
+
+ScalarRegU32 mask = (((1U << size) - 1U) << offset);
+hwreg = ((hwreg.rawData() & ~mask)
+| ((simm32 << offset) & mask));
+hwreg.write();
+
+if (hwregId==1 && size==2
+&& (offset==4 || offset==0)) {
+warn_once("Be cautious that s_setreg_imm32_b32 has no real
effect "
+"on FP modes: %s\n",
gpuDynInst->disassemble());
+return;
+}
+
+// panic if not changing MODE of floating-point numbers
panicUnimplemented();
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37475
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5383243403156dc17d4997106085a62fb0483fec
Gerrit-Change-Number: 37475
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-memorysize-division]: cpu,stats: Fix incorrect stat names of ThreadStateStats
Attention is currently required from: Hoa Nguyen.
Hello Hoa Nguyen,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/37455
to review the following change.
Change subject: cpu,stats: Fix incorrect stat names of ThreadStateStats
..
cpu,stats: Fix incorrect stat names of ThreadStateStats
Previously, ThreadStateStats uses ThreadState::threadId() to
determine the name of the stats. However, in the ThreadState
constructor, ThreadStateStats is initialized before ThreadState
is intialized. As a result, the name of ThreadStateStats has
a wrong ThreadID.
This commit uses ThreadID instead of ThreadState to determine
the name of the stats.
This causes a name collision between ThreadStateStats and
ExecContextStats as both have the name of "thread_[tid]".
Ideally, those stats should be merged to the BaseSimpleCPU.
However, both ThreadStateStats and ExecContextStats have
a stat named numInsts. So, for now, ExecContextStats will
have a name of "exec_context.thread_[tid]", while ThreadStateStats
keeps its name.
Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Signed-off-by: Hoa Nguyen
---
M src/cpu/thread_state.cc
M src/cpu/thread_state.hh
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index a142f57..5e59eb2 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -39,7 +39,7 @@
#include "sim/system.hh"
ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
-: numInst(0), numOp(0), threadStats(cpu, this),
+: numInst(0), numOp(0), threadStats(cpu, _tid),
numLoad(0), startNumLoad(0),
_status(ThreadContext::Halted), baseCpu(cpu),
_contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0),
@@ -119,8 +119,8 @@
}
ThreadState::ThreadStateStats::ThreadStateStats(BaseCPU *cpu,
-ThreadState *thread)
- : Stats::Group(cpu, csprintf("thread%i",
thread->threadId()).c_str()),
+const ThreadID& tid)
+ : Stats::Group(cpu, csprintf("thread_%i", tid).c_str()),
ADD_STAT(numInsts, "Number of Instructions committed"),
ADD_STAT(numOps, "Number of Ops committed"),
ADD_STAT(numMemRefs, "Number of Memory References")
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 3ac473d..53817c8 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -111,7 +111,7 @@
// Defining the stat group
struct ThreadStateStats : public Stats::Group
{
-ThreadStateStats(BaseCPU *cpu, ThreadState *thread);
+ThreadStateStats(BaseCPU *cpu, const ThreadID& thread);
/** Stat for number instructions committed. */
Stats::Scalar numInsts;
/** Stat for number ops (including micro ops) committed. */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37455
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: hotfix-memorysize-division
Gerrit-Change-Id: If9a21549f98bd6e3ce6dc29bdf183e8fd5f51a67
Gerrit-Change-Number: 37455
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Attention: Hoa Nguyen
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
