[gem5-dev] Change in gem5/gem5[develop]: systemc: Make tlm/gem5 packet conversion flexible
Jui-min Lee has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37075 )
Change subject: systemc: Make tlm/gem5 packet conversion flexible
..
systemc: Make tlm/gem5 packet conversion flexible
We used to have a hard-coded packet2payload and payload2packet in the
tlm_bridge implementation. However, as the conversion is operated on
generic tlm payload, we're not able to handle information stored in any
user defined SystemC extensions.
In this CL, we add a pair of function to register extra conversion steps
between tlm payload and gem5 packet. This decouples the exact conversion
logic and enables SystemC users to register any necessary steps for
their extensions.
Change-Id: I70b3405395fed0f757f0fb7e19136f47d84ac115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37075
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
M src/systemc/tlm_bridge/tlm_to_gem5.hh
4 files changed, 71 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc
b/src/systemc/tlm_bridge/gem5_to_tlm.cc
index ba8f121..f03548c 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -58,6 +58,8 @@
#include "systemc/tlm_bridge/gem5_to_tlm.hh"
+#include
+
#include "params/Gem5ToTlmBridge32.hh"
#include "params/Gem5ToTlmBridge64.hh"
#include "sim/system.hh"
@@ -73,6 +75,27 @@
*/
Gem5SystemC::MemoryManager mm;
+namespace
+{
+/**
+ * Hold all the callbacks necessary to convert a gem5 packet to tlm
payload.
+ */
+std::vector extraPacketToPayloadSteps;
+} // namespace
+
+/**
+ * Notify the Gem5ToTlm bridge that we need an extra step to properly
convert a
+ * gem5 packet to tlm payload. This can be useful when there exists a
SystemC
+ * extension that requires information in gem5 packet. For example, if a
user
+ * defined a SystemC extension the carries stream_id, the user may add a
step
+ * here to read stream_id out and set the extension properly.
+ */
+void
+addPacketToPayloadConversionStep(PacketToPayloadConversionStep step)
+{
+extraPacketToPayloadSteps.push_back(std::move(step));
+}
+
/**
* Convert a gem5 packet to a TLM payload by copying all the relevant
* information to new tlm payload.
@@ -110,6 +133,11 @@
auto *extension = new Gem5SystemC::Gem5Extension(packet);
trans->set_auto_extension(extension);
+// Apply all conversion steps necessary in this specific setup.
+for (auto : extraPacketToPayloadSteps) {
+step(packet, *trans);
+}
+
return trans;
}
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh
b/src/systemc/tlm_bridge/gem5_to_tlm.hh
index 2572027..d29bfd7 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -59,6 +59,7 @@
#ifndef __SYSTEMC_TLM_BRIDGE_GEM5_TO_TLM_HH__
#define __SYSTEMC_TLM_BRIDGE_GEM5_TO_TLM_HH__
+#include
#include
#include "mem/port.hh"
@@ -73,6 +74,11 @@
namespace sc_gem5
{
+using PacketToPayloadConversionStep =
+std::function;
+
+void addPacketToPayloadConversionStep(PacketToPayloadConversionStep step);
+
tlm::tlm_generic_payload *packet2payload(PacketPtr packet);
class Gem5ToTlmBridgeBase : public sc_core::sc_module
diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc
b/src/systemc/tlm_bridge/tlm_to_gem5.cc
index 0cc0d7f..a1a8382 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -57,6 +57,8 @@
#include "systemc/tlm_bridge/tlm_to_gem5.hh"
+#include
+
#include "params/TlmToGem5Bridge32.hh"
#include "params/TlmToGem5Bridge64.hh"
#include "sim/system.hh"
@@ -66,6 +68,27 @@
namespace sc_gem5
{
+namespace
+{
+/**
+ * Hold all the callbacks necessary to convert a tlm payload to gem5
packet.
+ */
+std::vector extraPayloadToPacketSteps;
+} // namespace
+
+/**
+ * Notify the Tlm2Gem5 bridge that we need an extra step to properly
convert a
+ * tlm payload to gem5 packet. This can be useful when there exists a
SystemC
+ * extension that carries extra information. For example, SystemC user
might
+ * define an extension to store stream_id, the user may then add an extra
step
+ * to set the generated request's stream_id accordingly.
+ */
+void
+addPayloadToPacketConversionStep(PayloadToPacketConversionStep step)
+{
+extraPayloadToPacketSteps.push_back(std::move(step));
+}
+
PacketPtr
payload2packet(RequestorID _id, tlm::tlm_generic_payload )
{
@@ -96,6 +119,11 @@
auto pkt = new Packet(req, cmd);
pkt->dataStatic(trans.get_data_ptr());
+// Apply all conversion steps necessary in this specific setup.
+for (auto : extraPayloadToPacketSteps) {
+step(pkt,
[gem5-dev] Change in gem5/gem5[develop]: arch: Add some format strings to the parser for reg indexes.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36878 )
Change subject: arch: Add some format strings to the parser for reg indexes.
..
arch: Add some format strings to the parser for reg indexes.
There are two new strings, reg_idx_arr_decl which declares the source
and dest register index arrays, and set_reg_idx_arr which installs them
in the base class.
The set_reg_idx_arr code needs to implicitly figure out what type to use
based on the type of the "this" pointer. The name of the containing
class is not *necessarily* the same as class_name, since the generated
code can use that name, something based on that name, or whatever else
it wants. No other format string (other than class_name itself) uses the
class name internally, so we can't count on that working in existing ISA
definitions.
Change-Id: Id995a46896e71a2fcf3103c34a1e1e67e24f88f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36878
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 15 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser/isa_parser.py
b/src/arch/isa_parser/isa_parser.py
index 999d92f..ff54889 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -105,6 +105,21 @@
operands = SubOperandList(self.parser, compositeCode,
d.operands)
+myDict['reg_idx_arr_decl'] = \
+'RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]' % \
+(d.operands.numSrcRegs, d.operands.numDestRegs)
+
+# The reinterpret casts are largely because an array with a
known
+# size cannot be passed as an argument which is an array with
an
+# unknown size in C++.
+myDict['set_reg_idx_arr'] = '''
+setRegIdxArrays(
+reinterpret_cast(
+::remove_pointer_t::srcRegIdxArr),
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+'''
+
myDict['op_decl'] = operands.concatAttrStrings('op_decl')
if operands.readPC or operands.setPC:
myDict['op_decl'] += 'TheISA::PCState
__parserAutoPCState;\n'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id995a46896e71a2fcf3103c34a1e1e67e24f88f4
Gerrit-Change-Number: 36878
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Add an StaticInst accessor for setting register index storage.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36877 )
Change subject: cpu: Add an StaticInst accessor for setting register index
storage.
..
cpu: Add an StaticInst accessor for setting register index storage.
Change-Id: I66adccd8851f035b5d61ace9153ae7acc57403ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36877
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/cpu/static_inst.hh
1 file changed, 13 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 22e55ca..e5d9753 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -271,6 +271,19 @@
protected:
/**
+ * Set the pointers which point to the arrays of source and destination
+ * register indices. These will be defined in derived classes which
know
+ * what size they need to be, and installed here so they can be
accessed
+ * with the base class accessors.
+ */
+void
+setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
+{
+_srcRegIdxPtr = src;
+_destRegIdxPtr = dest;
+}
+
+/**
* Base mnemonic (e.g., "add"). Used by generateDisassembly()
* methods. Also useful to readily identify instructions from
* within the debugger when #cachedDisassembly has not been
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I66adccd8851f035b5d61ace9153ae7acc57403ed
Gerrit-Change-Number: 36877
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: this is a bug fix for MinorCPU for thread cloning.
Liao Xiongfei has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37315 )
Change subject: cpu-minor: this is a bug fix for MinorCPU for thread
cloning.
..
cpu-minor: this is a bug fix for MinorCPU for thread cloning.
Inside the code of cloneFunc(…) //syscall_emul.hh
cp->initState(); //line 1483
p->clone(tc, ctc, cp, flags); //line 1484
…
ctc->clearArchRegs(); //line 1503
OS::archClone(flags, p, cp, tc, ctc, newStack, tlsPtr); //line 1505
…
At line 1483, initState() is called and the activateContext() of the
corresponding MinorCPU is eventually called. The actual architecture
clone happens at line 1505 where PC of the new thread could have a
correct value.
In the existing implementation of MinorCPU::activateContext(ThreadID
thread_id), the below line 275 is called
pipeline->wakeupFetch(thread_id);
to start fetching instruction with current value of PC, which is 0x0,
leading to panic “Page table fault when accessing virtual address 0”.
This is because the OS::archClone() is not yet called. So, the below bug
fix handles the wakeup fetch for a thread for two scenarios:
...
if (!threads[thread_id]->getUseForClone())
{ //the thread is not cloned
pipeline->wakeupFetch(thread_id);
} else {//the thread from clone
if (fetchEventWrapper != NULL)
delete fetchEventWrapper;
fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
{pipeline->wakeupFetch(thread_id);}, "wakeupFetch");
schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
}
...
If a thread is not cloned, pipeline->wakeupFetch() is called
immediately.
For the cloned thread, the above bug fix delays the execution of
pipeline->wakeupFetch()
after the OS::archClone is done. ThreadContext::getUseForClone() return
true if a thread is cloned.
A member variable fetchEventWrapper is added to MinorCPU class for
delayed fetch event.
A member variable useForClone and its corresponding get/set methods are
added to ThreadContext class. This approach allows future reuse of this
useForClone variable by other CPU models if needed and also avoid lots
of changes resulted by modifying parameters of activateContext () and
activate() which are defined as override.
Inside the syscall cloneFunc, the useForClone member of a ThreadContext
object is set via its set method right before Process's initState() is
called, shown as below.
ctc->setUseForClone(true);
cp->initState();
p->clone(tc, ctc, cp, flags);
A few previously failed RISC-V ASM tests have been open in tests.py file
after the bug fix works.
JIRA issue: https://gem5.atlassian.net/browse/GEM5-374
Change-Id: Ibffe46522e2617443d29f49df180692c54830f14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37315
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/cpu/minor/cpu.cc
M src/cpu/minor/cpu.hh
M src/cpu/thread_context.hh
M src/sim/syscall_emul.hh
M tests/gem5/asmtest/tests.py
5 files changed, 41 insertions(+), 15 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 18a3fee..de74256 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -77,12 +77,17 @@
pipeline = new Minor::Pipeline(*this, params);
activityRecorder = pipeline->getActivityRecorder();
+
+fetchEventWrapper = NULL;
}
MinorCPU::~MinorCPU()
{
delete pipeline;
+if (fetchEventWrapper != NULL)
+delete fetchEventWrapper;
+
for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++) {
delete threads[thread_id];
}
@@ -266,7 +271,17 @@
/* Wake up the thread, wakeup the pipeline tick */
threads[thread_id]->activate();
wakeupOnEvent(Minor::Pipeline::CPUStageId);
-pipeline->wakeupFetch(thread_id);
+
+if (!threads[thread_id]->getUseForClone())//the thread is not cloned
+{
+pipeline->wakeupFetch(thread_id);
+} else { //the thread from clone
+if (fetchEventWrapper != NULL)
+delete fetchEventWrapper;
+fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
+ { pipeline->wakeupFetch(thread_id); }, "wakeupFetch");
+schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
+}
BaseCPU::activateContext(thread_id);
}
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index ac9831a..0e919f33 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -186,6 +186,7 @@
* already been idled. The stage argument should be from the
* enumeration Pipeline::StageId */
void wakeupOnEvent(unsigned int stage_id);
+EventFunctionWrapper *fetchEventWrapper;
};
#endif /* __CPU_MINOR_CPU_HH__ */
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
[gem5-dev] Change in gem5/gem5[develop]: x86: Fix object scope in the CPUID code.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37695 )
Change subject: x86: Fix object scope in the CPUID code.
..
x86: Fix object scope in the CPUID code.
The original version of the code takes a pointer from a temporary object
which gets destroyed before the pointer is used.
Change-Id: I16af4eefdf202f769a672e230330d8e0bfce3bb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37695
Reviewed-by: Matthew Poremba
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/cpuid.cc
1 file changed, 8 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index 8c9f29c..2a560f5 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -94,12 +94,12 @@
case VendorAndLargestExtFunc:
{
ISA *isa = dynamic_cast(tc->getIsaPtr());
- const char *vendor_string =
isa->getVendorString().c_str();
+ auto vendor_string = isa->getVendorString();
result = CpuidResult(
0x8000 + NumExtendedCpuidFuncs - 1,
- stringToRegister(vendor_string),
- stringToRegister(vendor_string + 4),
- stringToRegister(vendor_string + 8));
+ stringToRegister(vendor_string.c_str()),
+ stringToRegister(vendor_string.c_str() + 4),
+ stringToRegister(vendor_string.c_str() + 8));
}
break;
case FamilyModelSteppingBrandFeatures:
@@ -155,12 +155,12 @@
case VendorAndLargestStdFunc:
{
ISA *isa = dynamic_cast(tc->getIsaPtr());
- const char *vendor_string =
isa->getVendorString().c_str();
+ auto vendor_string = isa->getVendorString();
result = CpuidResult(
NumExtendedCpuidFuncs - 1,
- stringToRegister(vendor_string),
- stringToRegister(vendor_string + 4),
- stringToRegister(vendor_string + 8));
+ stringToRegister(vendor_string.c_str()),
+ stringToRegister(vendor_string.c_str() + 4),
+ stringToRegister(vendor_string.c_str() + 8));
}
break;
case FamilyModelStepping:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I16af4eefdf202f769a672e230330d8e0bfce3bb7
Gerrit-Change-Number: 37695
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,misc: Added missing overrides to gpu_thread.hh
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37538 )
Change subject: arch-gcn3,misc: Added missing overrides to gpu_thread.hh
..
arch-gcn3,misc: Added missing overrides to gpu_thread.hh
Compiling GCN3 with clang will result in errors within this change.
Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37538
Maintainer: Bobby R. Bruce
Tested-by: kokoro
Reviewed-by: Matthew Poremba
---
M src/cpu/testers/gpu_ruby_test/gpu_thread.hh
1 file changed, 9 insertions(+), 4 deletions(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
b/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
index 00a69be..1c9fedc 100644
--- a/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
+++ b/src/cpu/testers/gpu_ruby_test/gpu_thread.hh
@@ -90,8 +90,8 @@
: Event(CPU_Tick_Pri), thread(_thread), desc(_description)
{}
void setDesc(std::string _description) { desc = _description; }
-void process() { thread->wakeup(); }
-const std::string name() { return desc; }
+void process() override { thread->wakeup(); }
+const std::string name() const override { return desc; }
};
GpuThreadEvent threadEvent;
@@ -105,8 +105,13 @@
DeadlockCheckEvent(GpuThread* _thread)
: Event(CPU_Tick_Pri), thread(_thread)
{}
-void process() { thread->checkDeadlock(); }
-const std::string name() const { return "Tester deadlock check"; }
+void process() override { thread->checkDeadlock(); }
+
+const std::string
+name() const override
+{
+return "Tester deadlock check";
+}
};
DeadlockCheckEvent deadlockCheckEvent;
--
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Gerrit-Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Gerrit-Change-Number: 37538
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Kyle Roarty
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tuan Ta
Gerrit-Reviewer: kokoro
Gerrit-CC: Anthony Gutierrez
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Replace xrange with range to be python3 compliant
Attention is currently required from: Nikos Nikoleris. Hello Nikos Nikoleris, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/37716 to review the following change. Change subject: fastmodel: Replace xrange with range to be python3 compliant .. fastmodel: Replace xrange with range to be python3 compliant Change-Id: I69ef5d744e2642af95383fbda920464178380757 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris --- M src/arch/arm/fastmodel/GIC/FastModelGIC.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py b/src/arch/arm/fastmodel/GIC/FastModelGIC.py index 3298be9..ac81de5 100644 --- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py +++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py @@ -509,7 +509,7 @@ ] ranges += [ AddrRange(its_bases[i], size=2 * gic_frame_size) -for i in xrange(sc_gic.its_count) +for i in range(sc_gic.its_count) ] return ranges -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37716 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I69ef5d744e2642af95383fbda920464178380757 Gerrit-Change-Number: 37716 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Nikos Nikoleris Gerrit-Attention: Nikos Nikoleris Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Use BaseMMU in the CortexR52 wrapper
Attention is currently required from: Nikos Nikoleris.
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/37715
to review the following change.
Change subject: fastmodel: Use BaseMMU in the CortexR52 wrapper
..
fastmodel: Use BaseMMU in the CortexR52 wrapper
Signed-off-by: Giacomo Travaglini
Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Reviewed-by: Nikos Nikoleris
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
index 648a39a..e8e0aa7 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -36,10 +36,10 @@
{
CortexR52TC::CortexR52TC(
-::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB
*itb,
+::BaseCPU *cpu, int id, System *system, ::BaseMMU *mmu,
::BaseISA *isa, iris::IrisConnectionInterface *iris_if,
const std::string _path) :
-ThreadContext(cpu, id, system, dtb, itb, isa, iris_if, iris_path)
+ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
{}
bool
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
index 74ac1a0..41223c9 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -44,7 +44,7 @@
public:
CortexR52TC(::BaseCPU *cpu, int id, System *system,
-::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa,
+::BaseMMU *mmu, ::BaseISA *isa,
iris::IrisConnectionInterface *iris_if,
const std::string _path);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Gerrit-Change-Number: 37715
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Attention: Nikos Nikoleris
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Access src and dest reg indexes using a pointer to member.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36876 )
Change subject: cpu: Access src and dest reg indexes using a pointer to
member.
..
cpu: Access src and dest reg indexes using a pointer to member.
This will eventually let subclasses provide their own appropriately
sized storage for these indexes. By using a pointer to member instead of
a regular pointer, we ensure that even if the StaticInst is copied/moved
somewhere, it will still find its indexes correctly, without any
additional performance overhead or maintenance.
Unfortunately C++ has decided that arrays with known bounds are not
convertible/compatible with arrays with unknown bounds. I've found at
least two standards proposals in various stages of acceptance which say
that that's dumb and they should change that (because it's dumb and they
should change that), but in the mean time we can get everything to
compile by using the reinterpret_cast hammer. While this is
*technically* undefined behavior, it's basically not and should be
pretty safe.
Change-Id: Id747b0cf68d1a0b4809ebb66a32472187110d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36876
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/cpu/static_inst.hh
1 file changed, 28 insertions(+), 10 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 4f3dd04..22e55ca 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -93,11 +93,16 @@
MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
};
+using RegIdArrayPtr = RegId (StaticInst:: *)[];
+
private:
-/// See destRegIdx().
-RegId _destRegIdx[MaxInstDestRegs];
/// See srcRegIdx().
RegId _srcRegIdx[MaxInstSrcRegs];
+RegIdArrayPtr _srcRegIdxPtr = nullptr;
+
+/// See destRegIdx().
+RegId _destRegIdx[MaxInstDestRegs];
+RegIdArrayPtr _destRegIdxPtr = nullptr;
protected:
@@ -236,15 +241,23 @@
/// Return logical index (architectural reg num) of i'th destination
reg.
/// Only the entries from 0 through numDestRegs()-1 are valid.
-const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
+const RegId (int i) const { return
(this->*_destRegIdxPtr)[i]; }
-void setDestRegIdx(int i, const RegId ) { _destRegIdx[i] = val; }
+void
+setDestRegIdx(int i, const RegId )
+{
+(this->*_destRegIdxPtr)[i] = val;
+}
/// Return logical index (architectural reg num) of i'th source reg.
/// Only the entries from 0 through numSrcRegs()-1 are valid.
-const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; }
+const RegId (int i) const { return
(this->*_srcRegIdxPtr)[i]; }
-void setSrcRegIdx(int i, const RegId ) { _srcRegIdx[i] = val; }
+void
+setSrcRegIdx(int i, const RegId )
+{
+(this->*_srcRegIdxPtr)[i] = val;
+}
/// Pointer to a statically allocated "null" instruction object.
static StaticInstPtr nullStaticInstPtr;
@@ -283,10 +296,15 @@
/// the fields that are meaningful for the particular
/// instruction.
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass
__opClass)
-: _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
- _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
- _numVecDestRegs(0), _numVecElemDestRegs(0),
_numVecPredDestRegs(0),
- machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
+: _srcRegIdxPtr(
+reinterpret_cast(::_srcRegIdx)),
+ _destRegIdxPtr(
+reinterpret_cast(::_destRegIdx)),
+ _opClass(__opClass),
+ _numSrcRegs(0), _numDestRegs(0), _numFPDestRegs(0),
+ _numIntDestRegs(0), _numCCDestRegs(0), _numVecDestRegs(0),
+ _numVecElemDestRegs(0), _numVecPredDestRegs(0),
machInst(_machInst),
+ mnemonic(_mnemonic), cachedDisassembly(0)
{ }
public:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/36876
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id747b0cf68d1a0b4809ebb66a32472187110d7d8
Gerrit-Change-Number: 36876
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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