[gem5-dev] Change in gem5/gem5[develop]: dev: Fixing EtherDevice stats initialization order

2021-01-20 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39395 )


Change subject: dev: Fixing EtherDevice stats initialization order
..

dev: Fixing EtherDevice stats initialization order

Previously, the stat `totalBandwidth` is initialized before
`txBandwidth` and `rxBandwidth`. However, `totalBandwith` is of
 type Stats::Formula and `totalBandwidth = txBandwidth + rxBandwidth`.
Therefore, `totalBandwidth` should be initialized after the other two.

This change fixes the variable and stats initialization order accordingly.

The bug was reported here:   
https://github.com/gem5/gem5/commit/3db48cbbc6e475592e6608b52a870d92ac2214aa#commitcomment-46094633.


Jira: https://gem5.atlassian.net/browse/GEM5-894

Change-Id: I2c7cc4120df672edf15b9a3ab6becc0bbebb778b
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39395
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/dev/net/etherdevice.cc
M src/dev/net/etherdevice.hh
2 files changed, 7 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/net/etherdevice.cc b/src/dev/net/etherdevice.cc
index 64ab438..e279a9c 100644
--- a/src/dev/net/etherdevice.cc
+++ b/src/dev/net/etherdevice.cc
@@ -37,6 +37,10 @@
   ADD_STAT(rxBytes, "Bytes Received"),
   ADD_STAT(txPackets, "Number of Packets Transmitted"),
   ADD_STAT(rxPackets, "Number of Packets Received"),
+  ADD_STAT(txBandwidth, "Transmit Bandwidth (bits/s)",
+   txBytes * Stats::constant(8) / simSeconds),
+  ADD_STAT(rxBandwidth, "Receive Bandwidth (bits/s)",
+   rxBytes * Stats::constant(8) / simSeconds),
   ADD_STAT(txIpChecksums, "Number of tx IP Checksums done by device"),
   ADD_STAT(rxIpChecksums, "Number of rx IP Checksums done by device"),
   ADD_STAT(txTcpChecksums, "Number of tx TCP Checksums done by  
device"),

@@ -53,10 +57,6 @@
   ADD_STAT(totBytes, "Total Bytes", txBytes + rxBytes),
   ADD_STAT(totPacketRate, "Total Tranmission Rate (packets/s)",
totPackets / simSeconds),
-  ADD_STAT(txBandwidth, "Transmit Bandwidth (bits/s)",
-   txBytes * Stats::constant(8) / simSeconds),
-  ADD_STAT(rxBandwidth, "Receive Bandwidth (bits/s)",
-   rxBytes * Stats::constant(8) / simSeconds),
   ADD_STAT(txPacketRate, "Packet Tranmission Rate (packets/s)",
txPackets / simSeconds),
   ADD_STAT(rxPacketRate, "Packet Reception Rate (packets/s)",
diff --git a/src/dev/net/etherdevice.hh b/src/dev/net/etherdevice.hh
index 0cc54d0..a853cd8 100644
--- a/src/dev/net/etherdevice.hh
+++ b/src/dev/net/etherdevice.hh
@@ -70,6 +70,9 @@
 Stats::Scalar txPackets;
 Stats::Scalar rxPackets;

+Stats::Formula txBandwidth;
+Stats::Formula rxBandwidth;
+
 Stats::Scalar txIpChecksums;
 Stats::Scalar rxIpChecksums;

@@ -90,9 +93,6 @@
 Stats::Formula totBytes;
 Stats::Formula totPacketRate;

-Stats::Formula txBandwidth;
-Stats::Formula rxBandwidth;
-
 Stats::Formula txPacketRate;
 Stats::Formula rxPacketRate;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2c7cc4120df672edf15b9a3ab6becc0bbebb778b
Gerrit-Change-Number: 39395
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jonathan Bohren 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: Fix unsigned underflow mishandling.

2021-01-20 Thread Philip Metzler (Gerrit) via gem5-dev 
Philip Metzler has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39496 )



Change subject: Fix unsigned underflow mishandling.
..

Fix unsigned underflow mishandling.

The second argument in the std::max call is treated as an unsigned value
as all variables are unsigned as well. This will result in an
unsigned underflow, and as such the std::max is a no-op and will result
in the underflowed value.

The `start` and `used` value get corrupted after that, and checks for
`empty` and other stuff downstream break.

Change-Id: I00017e22ba84e65f6b1c596f47d348f342fbc304
---
M src/base/circlebuf.hh
M src/base/circlebuf.test.cc
2 files changed, 22 insertions(+), 1 deletion(-)



diff --git a/src/base/circlebuf.hh b/src/base/circlebuf.hh
index bcfa91a..77a05d7 100644
--- a/src/base/circlebuf.hh
+++ b/src/base/circlebuf.hh
@@ -167,7 +167,9 @@
 }

 // How much existing data will be overwritten?
-const size_t overflow = std::max(0, used + len - maxSize);
+const size_t total_bytes = used + len;
+const size_t overflow = total_bytes > maxSize ?
+total_bytes - maxSize : 0;
 // The iterator of the next byte to add.
 auto next_it = buffer.begin() + (start + used) % maxSize;
 // How much there is to copy to the end of the buffer.
diff --git a/src/base/circlebuf.test.cc b/src/base/circlebuf.test.cc
index 6b81b61..2e1f6bd 100644
--- a/src/base/circlebuf.test.cc
+++ b/src/base/circlebuf.test.cc
@@ -130,3 +130,22 @@
 EXPECT_EQ(buf.size(), 0);
 EXPECT_THAT(subArr(foo, 12), ElementsAreArray(data, 12));
 }
+
+// Consume after produce empties queue
+TEST(CircleBufTest, ProduceConsumeEmpty)
+{
+CircleBuf buf(8);
+char foo[1];
+
+// buf is empty to begin with.
+EXPECT_TRUE(buf.empty());
+// Produce one element.
+buf.write(foo, 1);
+EXPECT_FALSE(buf.empty());
+
+// Read it back out.
+buf.read(foo, 1);
+
+// Now the buffer should be empty again.
+EXPECT_TRUE(buf.empty());
+}

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[gem5-dev] Change in gem5/gem5[develop]: sim-se: Handle simultaneous page faults in SE-mode multithreading

2021-01-20 Thread Jiayi Huang (Gerrit) via gem5-dev 
Jiayi Huang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39515 )



Change subject: sim-se: Handle simultaneous page faults in SE-mode  
multithreading

..

sim-se: Handle simultaneous page faults in SE-mode multithreading

When running multithreaded programs in SE-mode with DerivO3CPU model,
there are cases that two or more cores have page faults on the same page
in nearby ticks (can be at the same tick) when fetching instructions
(more likely) or accessing data. When these cores try come to the commit
stage in nearby ticks/cycles, they will try to handle the faults
(without clobbering). Then the first core will ask for a physical page
frame to map with the virtual page. In the previous version, the right
next core that tries to handle the fault will hit a panic condition in
the EmulationPageTable::map(...) as the page has been mapped and this
page fault is not to clobber the existing mapping.

In this changeset, if it is found that the page has been mapped and it
is not to clobber the existing mapping, it will return without further
mapping activities as the page fault has been handled previously.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-798

Change-Id: I9bb1163f9d1379c6fed9725101e4400fefdc8079
---
M src/sim/process.cc
1 file changed, 15 insertions(+), 0 deletions(-)



diff --git a/src/sim/process.cc b/src/sim/process.cc
index 7819820..409b48a 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -307,6 +307,21 @@
 void
 Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
 {
+// Check if the page has been mapped by other cores if not to clobber.
+// When running multithreaded programs in SE-mode with DerivO3CPU  
model,

+// there are cases where two or more cores have page faults on the same
+// page in nearby ticks. When the cores try to handle the faults at the
+// commit stage (also in nearby ticks/cycles), the first core will ask  
for

+// a physical page frame to map with the virtual page. Other cores can
+// return if the page has been mapped and `!clobber`.
+if (!clobber) {
+const EmulationPageTable::Entry *pte = pTable->lookup(vaddr);
+if (pte) {
+warn("Process::allocateMem: addr %#x already mapped\n", vaddr);
+return;
+}
+}
+
 int npages = divCeil(size, pTable->pageSize());
 Addr paddr = system->allocPhysPages(npages);
 pTable->map(vaddr, paddr, size,

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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: implement PSHUFB SSE instruction.

2021-01-20 Thread Tong Shen (Gerrit) via gem5-dev 
Tong Shen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39495 )



Change subject: arch-x86: implement PSHUFB SSE instruction.
..

arch-x86: implement PSHUFB SSE instruction.

Change-Id: I9398f9ecb26b6aabf4015e0e285fdc2f4c2487dd
---
M src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa
M src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py
M src/arch/x86/isa/microops/mediaop.isa
3 files changed, 72 insertions(+), 2 deletions(-)



diff --git a/src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa  
b/src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa

index 3165eb7..0f4330b 100644
--- a/src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa
+++ b/src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa
@@ -31,7 +31,7 @@
 'X86ISA::ThreeByte0F38Opcode': decode LEGACY_OP {
 format WarnUnimpl {
 1: decode OPCODE_OP {
-0x00: pshufb_Vdq_Wdq();
+0x00: Inst::PSHUFB(Vo, Wo);
 0x01: phaddw_Vdq_Wdq();
 0x02: phaddd_Vdq_Wdq();
 0x03: phaddsw_Vdq_Wdq();
diff --git  
a/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py  
b/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py

index 6651d87..7beb2dd 100644
--- a/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py
+++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py
@@ -84,4 +84,32 @@
 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
 shuffle xmml, ufp1, ufp1, size=2, ext=imm
 };
-'''
+
+def macroop PSHUFB_XMM_XMM {
+movfp ufp1, xmmlm, dataSize=8
+movfp ufp2, xmmhm, dataSize=8
+shuffleb ufp1, xmml, xmmh
+shuffleb ufp2, xmml, xmmh
+movfp xmml, ufp1, dataSize=8
+movfp xmmh, ufp2, dataSize=8
+};
+
+def macroop PSHUFB_XMM_M {
+ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8
+ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8
+shuffleb ufp1, xmml, xmmh
+shuffleb ufp2, xmml, xmmh
+movfp xmml, ufp1, dataSize=8
+movfp xmmh, ufp2, dataSize=8
+};
+
+def macroop PSHUFB_XMM_P {
+rdip t7
+ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8
+ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8
+shuffleb ufp1, xmml, xmmh
+shuffleb ufp2, xmml, xmmh
+movfp xmml, ufp1, dataSize=8
+movfp xmmh, ufp2, dataSize=8
+};
+'''
\ No newline at end of file
diff --git a/src/arch/x86/isa/microops/mediaop.isa  
b/src/arch/x86/isa/microops/mediaop.isa

index bf5fc67..124ea2d 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -368,6 +368,48 @@
 FpDestReg_uqw = result;
 '''

+class shuffleb(MediaOp):
+def __init__(self, dest, src1, src2):
+super(shuffleb, self).__init__(dest, src1, src2, 8)
+op_class = 'SimdMiscOp'
+code = '''
+const int sizeBits = 8;
+const int items = 8;
+const int options = 16;
+const int optionBits = 8;
+
+uint64_t result = 0;
+uint64_t sel = FpDestReg_uqw;
+
+for (int i = 0; i < items; i++) {
+uint64_t resBits;
+uint8_t lsel = sel & mask(optionBits);
+
+if ((lsel & 0x80) == 0) {
+if (lsel >= options / 2) {
+lsel -= options / 2;
+resBits = bits(FpSrcReg2_uqw,
+(lsel + 1) * sizeBits - 1,
+(lsel + 0) * sizeBits);
+} else {
+resBits = bits(FpSrcReg1_uqw,
+(lsel + 1) * sizeBits - 1,
+(lsel + 0) * sizeBits);
+}
+} else {
+resBits = 0;
+}
+
+sel >>= optionBits;
+
+int hiIndex = (i + 1) * sizeBits - 1;
+int loIndex = (i + 0) * sizeBits;
+result = insertBits(result, hiIndex, loIndex, resBits);
+}
+
+FpDestReg_uqw = result;
+'''
+
 class Unpack(MediaOp):
 op_class = 'SimdMiscOp'
 code = '''

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[gem5-dev] Jenkins build is back to normal : Nightly #194

2021-01-20 Thread jenkins-no-reply--- via gem5-dev 
See 
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[gem5-dev] Change in gem5/gem5[develop]: riscv: Get rid of some unused constants.

2021-01-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39317 )


Change subject: riscv: Get rid of some unused constants.
..

riscv: Get rid of some unused constants.

Change-Id: I464e86dc6bfcd333a0bee32e56d9dcaa6fdf682d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39317
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Ayaz Akram 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/registers.hh
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Ayaz Akram: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index ed8b916..84a1924 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -101,8 +101,6 @@
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

-const int SyscallPseudoReturnReg = 10;
-const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
 const int SyscallNumReg = 17;

 const std::vector IntRegNames = {

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Gerrit-Change-Number: 39317
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arm: Use the "reg" ABI for gem5 ops.

2021-01-20 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39316 )


Change subject: arm: Use the "reg" ABI for gem5 ops.
..

arm: Use the "reg" ABI for gem5 ops.

The generic PseudoInstABI just calls back into the ISA specific
getArgument function, and that adds a lot of handling for cases that
aren't used and, besides those, basically just boils down to the "reg"
ABI anyway.

Change-Id: I57e738631dbccbf89cba3a6ca62b1f954b39e959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39316
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/m5ops.isa
M src/arch/arm/tlb.cc
3 files changed, 14 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index 13b47c8..6af382a 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -105,6 +105,7 @@
 #include "arch/arm/htm.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/pauth_helpers.hh"
+#include "arch/arm/reg_abi.hh"
 #include "arch/arm/semihosting.hh"
 #include "arch/arm/utility.hh"
 #include "arch/generic/memhelpers.hh"
diff --git a/src/arch/arm/isa/insts/m5ops.isa  
b/src/arch/arm/isa/insts/m5ops.isa

index 9b32065..fafb44b 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -38,13 +38,14 @@
 let {{
 gem5OpCode = '''
 uint64_t ret;
-bool recognized = PseudoInst::pseudoInst(
-xc->tcBase(), bits(machInst, 23, 16), ret);
-if (!recognized)
+int func = bits(machInst, 23, 16);
+auto *tc = xc->tcBase();
+if (!PseudoInst::pseudoInst<%s>(tc, func, ret))
 fault = std::make_shared(machInst, true);
 '''
 gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op64", "PredOp",
- { "code": gem5OpCode + 'X0 = ret;',
+ { "code": gem5OpCode % "RegABI64" +
+   'X0 = ret;',
"predicate_test": predicateTest },
  [ "IsNonSpeculative", "IsUnverifiable" ]);
 header_output += BasicDeclare.subst(gem5OpIop)
@@ -52,7 +53,7 @@
 exec_output += PredOpExecute.subst(gem5OpIop)

 gem5OpIop = ArmInstObjParams("gem5op", "Gem5Op", "PredOp",
- { "code": gem5OpCode + \
+ { "code": gem5OpCode % "RegABI32" + \
'R0 = bits(ret, 31, 0);\n' + \
'R1 = bits(ret, 63, 32);',
"predicate_test": predicateTest },
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5d2ed90..91c7088 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -47,6 +47,7 @@
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/reg_abi.hh"
 #include "arch/arm/self_debug.hh"
 #include "arch/arm/stage2_lookup.hh"
 #include "arch/arm/stage2_mmu.hh"
@@ -146,9 +147,14 @@
 [func, mode](ThreadContext *tc, PacketPtr pkt) -> Cycles
 {
 uint64_t ret;
-PseudoInst::pseudoInst(tc, func, ret);
+if (inAArch64(tc))
+PseudoInst::pseudoInst(tc, func, ret);
+else
+PseudoInst::pseudoInst(tc, func, ret);
+
 if (mode == Read)
 pkt->setLE(ret);
+
 return Cycles(1);
 }
 );

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Gerrit-Change-Number: 39316
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect prefixes is m5.utils.convert

2021-01-20 Thread Andreas Sandberg (Gerrit) via gem5-dev 
Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39375 )


Change subject: python: Fix incorrect prefixes is m5.utils.convert
..

python: Fix incorrect prefixes is m5.utils.convert

The conversion functions incorrectly assumed that kibibytes are 'kiB'
rather than 'KiB' (correct).

Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39375
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/util/convert.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass

Objections:
  Gabe Black: I would prefer this is not merged as is



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index d3088f6..73335e6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -62,7 +62,7 @@
 'Gi': gibi,
 'G': giga,
 'M': mega,
-'ki': kibi,
+'Ki': kibi,
 'k': kilo,
 'Mi': mebi,
 'm': milli,
@@ -84,7 +84,7 @@
 'G' : gibi,
 'Mi': mebi,
 'M' : mebi,
-'ki': kibi,
+'Ki': kibi,
 'k' : kibi,
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Gerrit-Change-Number: 39375
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim, mem, dev, arch: Consistently use ISO prefixes

2021-01-20 Thread Andreas Sandberg (Gerrit) via gem5-dev 
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39475 )



Change subject: sim, mem, dev, arch: Consistently use ISO prefixes
..

sim, mem, dev, arch: Consistently use ISO prefixes

We currently use a the ambiguous JEDEC prefixes (e.g., MB) in a lot of
places instead of the unambiguous ISO/IEC prefixes (e.g., MiB). This
change replaces most the old prefixes with the new ISO/IEC prefixes in
the code base.

Change-Id: I0849b97d75e17fca2c782166185f41dd2cf6b0a5
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/mips/process.cc
M src/arch/x86/pagetable_walker.cc
M src/dev/arm/FlashDevice.py
M src/dev/arm/RealView.py
M src/dev/net/Ethernet.py
M src/dev/pci/CopyEngine.py
M src/dev/x86/Pc.py
M src/gpu-compute/GPU.py
M src/gpu-compute/LdsState.py
M src/learning_gem5/part2/HelloObject.py
M src/learning_gem5/part2/SimpleCache.py
M src/mem/AbstractMemory.py
M src/mem/DRAMInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/tags/Tags.py
M src/python/m5/params.py
M src/sim/Process.py
M src/sim/syscall_emul.hh
24 files changed, 138 insertions(+), 136 deletions(-)



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index e445590..8674edc 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -53,10 +53,10 @@
 files_root_dir = Param.String("",
 "Host root directory for files handled by Semihosting")

-mem_reserve = Param.MemorySize("32MB",
+mem_reserve = Param.MemorySize("32MiB",
 "Amount of memory to reserve at the start of the address map.  
This "

 "memory won't be used by the heap reported to an application.");
-stack_size = Param.MemorySize("32MB", "Application stack size");
+stack_size = Param.MemorySize("32MiB", "Application stack size");

 time = Param.Time('01/01/2009',
   "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e658b02..7f19adb 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -648,7 +648,7 @@
 MISCREG_TTBR0, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t0sz;
 currState->isUncacheable = currState->ttbcr.irgn0 == 0;
-if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GB
+if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GiB
 start_lookup_level = L2;
 } else if (currState->vaddr >= ttbr1_min) {
 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
@@ -673,7 +673,7 @@
 MISCREG_TTBR1, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t1sz;
 currState->isUncacheable = currState->ttbcr.irgn1 == 0;
-// Lower limit >= 3 GB
+// Lower limit >= 3 GiB
 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))
 start_lookup_level = L2;
 } else {
@@ -2379,16 +2379,16 @@
 pageSizes // see DDI 0487A D4-1661
 .init(10)
 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero);
-pageSizes.subname(0, "4K");
-pageSizes.subname(1, "16K");
-pageSizes.subname(2, "64K");
-pageSizes.subname(3, "1M");
-pageSizes.subname(4, "2M");
-pageSizes.subname(5, "16M");
-pageSizes.subname(6, "32M");
-pageSizes.subname(7, "512M");
-pageSizes.subname(8, "1G");
-pageSizes.subname(9, "4TB");
+pageSizes.subname(0, "4KiB");
+pageSizes.subname(1, "16KiB");
+pageSizes.subname(2, "64KiB");
+pageSizes.subname(3, "1MiB");
+pageSizes.subname(4, "2MiB");
+pageSizes.subname(5, "16MiB");
+pageSizes.subname(6, "32MiB");
+pageSizes.subname(7, "512MiB");
+pageSizes.subname(8, "1GiB");
+pageSizes.subname(9, "4TiB");

 requestOrigin
 .init(2,2) // Instruction/Data, requests/completed
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index dbb480e..f4ee552 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -132,7 +132,7 @@
 return (EntryType)(data & 0x3);
 }

-/** Is the page a Supersection (16MB)?*/
+/** Is the page a Supersection (16 MiB)?*/
 bool supersection() const
 {
 return bits(data, 18);
@@ -434,8 +434,8 @@
 {
 switch (bits(data, 1, 0)) {
   case 0x1:
-// In AArch64 blocks are not allowed at L0 for the 4 KB  
granule

-// and at L1 for 16/64 KB granules
+// In AArch64 blocks are not allowed at L0 for the
+// 4 KiB granule and at L1 for 16/64 KiB granules
 switch

[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature type in power/thermal models

2021-01-20 Thread Andreas Sandberg (Gerrit) via gem5-dev 
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39455 )



Change subject: sim: Use the Temperature type in power/thermal models
..

sim: Use the Temperature type in power/thermal models

The thermal models currently work on temperatures in Celsius stored in
plain doubles. Switch to using Temperature instead and internal
processing in Kelvin. There should be no impact on the result since
all thermal processes work on temperature deltas.

Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Signed-off-by: Andreas Sandberg 
---
M src/dev/arm/rv_ctrl.cc
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.hh
9 files changed, 39 insertions(+), 34 deletions(-)



diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 2d80bc2..8e4e6cf 100644
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -304,7 +304,7 @@
 // Temperature reported in uC
 ThermalModel * tm = system->getThermalModel();
 if (tm) {
-double t = tm->getTemp();
+double t = tm->getTemperature().toCelsius();
 if (t < 0)
 warn("Temperature below zero!\n");
 return fmax(0, t) * 100;
diff --git a/src/sim/power/mathexpr_powermodel.cc  
b/src/sim/power/mathexpr_powermodel.cc

index 4f3f927..c8a6cef 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -86,7 +86,7 @@

 // Automatic variables:
 if (name == "temp") {
-return _temp;
+return _temp.toCelsius();
 } else if (name == "voltage") {
 return clocked_object->voltage();
 } else if (name=="clock_period") {
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index 42515ac..74ab548 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2016-2018,2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp.toCelsius());
+pms->setTemperature(p.ambient_temp);
 }

 dynamicPower
@@ -86,7 +86,7 @@
 }

 void
-PowerModel::thermalUpdateCallback(const double & temp)
+PowerModel::thermalUpdateCallback(const Temperature )
 {
 for (auto & pms: states_pm)
 pms->setTemperature(temp);
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index e6f5431..8a11895 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, 2018 ARM Limited
+ * Copyright (c) 2016, 2018, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,6 +39,7 @@
 #define __SIM_POWER_POWER_MODEL_HH__

 #include "base/statistics.hh"
+#include "base/temperature.hh"
 #include "enums/PMType.hh"
 #include "params/PowerModel.hh"
 #include "params/PowerModelState.hh"
@@ -77,7 +78,7 @@
  *
  * @param temp Current temperature of the HW part (Celsius)
  */
-virtual void setTemperature(double temp) { _temp = temp; }
+virtual void setTemperature(Temperature temp) { _temp = temp; }

 void setClockedObject(ClockedObject * clkobj) {
 clocked_object = clkobj;
@@ -86,7 +87,7 @@
   protected:

 /** Current temperature */
-double _temp;
+Temperature _temp;

 /** The clocked object we belong to */
 ClockedObject * clocked_object;
@@ -125,18 +126,18 @@

 virtual void regProbePoints();

-void thermalUpdateCallback(const double & temp);
+void thermalUpdateCallback(const Temperature );

   protected:
 /** Listener class to catch thermal events */
-class ThermalProbeListener : public ProbeListenerArgBase
+class ThermalProbeListener : public ProbeListenerArgBase
 {
   public:
 ThermalProbeListener(PowerModel &_pm, ProbeManager *pm,
   const std::string )
 : ProbeListenerArgBase(pm, name), pm(_pm) {}

-void notify(const double )
+void notify(const Temperature )
 {
 pm.thermalUpdateCallback(temp);
 }
diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index b0868be..2d9076b 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -49,15 +49,15 @@
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
-: SimObject(p), _initTemperature(p.initial_temperature.toCelsius()),
+: SimObject(p),

[gem5-dev] Change in gem5/gem5[develop]: python: Require a unit in anyToFreuency and anyToLatency

2021-01-20 Thread Andreas Sandberg (Gerrit) via gem5-dev 
Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39435 )



Change subject: python: Require a unit in anyToFreuency and anyToLatency
..

python: Require a unit in anyToFreuency and anyToLatency

The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.

Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/util/convert.py
M tests/pyunit/util/test_convert.py
2 files changed, 32 insertions(+), 34 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index ce06ea4..12d3aa1 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -203,32 +203,40 @@
 return toMetricFloat(value, 'latency', 's')

 def anyToLatency(value):
-"""result is a clock period"""
-try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
-pass
+"""Convert a magnitude and unit to a clock period."""

-try:
-return toLatency(value)
-except ValueError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='latency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 's':
+return magnitude
+elif unit == 'Hz':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to clock period")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def anyToFrequency(value):
-"""result is a clock period"""
-try:
-return toFrequency(value)
-except ValueError:
-pass
+"""Convert a magnitude and unit to a clock frequency."""

-try:
-return 1 / toLatency(value)
-except ValueError as ZeroDivisionError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='frequency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 'Hz':
+return magnitude
+elif unit == 's':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to frequency")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def toNetworkBandwidth(value):
 return toMetricFloat(value, 'network bandwidth', 'bps')
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/test_convert.py

index 6d02b51..fcfedc4 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -163,28 +163,18 @@
 self.assertEqual(conv('1kHz'), 1e-3)

 self.assertRaises(ValueError, conv, '42k')
-
-@unittest.expectedFailure
-def test_anyToLatency_ambiguous(self):
-# This the behavior of anyToFrequency is currently ambiguous
-# (and surprising) for unitless quantities. The following
-# should be true to be consistent with the other conversion
-# functions, but that isn't currently the case.
-self.assertEqual(convert.anyToLatency('42'), 42.0)
-
+self.assertRaises(ValueError, conv, '42')

 def test_anyToFrequency(self):
 conv = convert.anyToFrequency

-# This is ambiguous and should probably not be allowed.
-self.assertEqual(conv('42'), 42.0)
-
 self.assertEqual(conv('42kHz'), 42e3)

 self.assertEqual(conv('0.1s'), 10.0)
 self.assertEqual(conv('1ms'), 1000.0)

 self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42')

 def test_toNetworkBandwidth(self):
 conv = convert.toNetworkBandwidth

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Gerrit-Change-Number: 39435
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Re-join debug flags headers

2021-01-20 Thread Gabe Black via gem5-dev 
Sorry for not responding to this for a while. I think this change is
probably a good idea. There is some cost to it, but even when students are
adding new debug flags, if they do that successfully (aka it builds), they
aren't likely to need to do that very many times. It's likely not something
they would need to tweak often, since they're likely to come up with a few
categories of DPRINTFs over time and add them once each. It *is* a cost and
it would be nice to avoid it, but I think in practice it's probably
relatively minor, and it would simplify the code and make it easier to
include all the headers you should directly without setting up accidental
transitive dependencies.

Gabe

On Mon, Jan 18, 2021 at 9:16 AM Jason Lowe-Power via gem5-dev <
gem5-dev@gem5.org> wrote:

> Thanks for bringing this up, Daniel!
>
> I don't have a strong opinion, personally. I see how this makes things a
> little easier for developers. No longer would we have to teach people that
> to add a new debug flag you both declare it in the SConscript file and
> include the named header file. Given that I've worked with gem5 for a long
> time, I don't see that as much overhead, though.
>
> This would increase the compile time (though, hopefully only rarely). And,
> we recently found from the gem5 survey that people don't care that much
> about the compile time (more info coming soon).
>
> I think the biggest downside would be for those that use gem5 in teaching.
> Students in architecture classes are the most likely to have underpowered
> computers building gem5, and they are also likely to be adding debug flags.
>
> Cheers,
> Jason
>
> On Fri, Jan 15, 2021 at 5:47 PM Daniel Carvalho via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> Hello all,
>>
>> I've uploaded a commit that re-joins the debug header files into a single
>> one: https://gem5-review.googlesource.com/c/public/gem5/+/39255. This
>> means that instead of having to include a different header for each and
>> every debug flag used in a file, only one is needed. For example, in
>> src/arch/arm/kvm/arm_cpu.cc
>>
>> #include "debug/Kvm.hh"
>> #include "debug/KvmContext.hh"
>> #include "debug/KvmInt.hh"
>>
>> would be replaced by
>>
>> #include "debug/flags.hh"
>>
>> Finally, since most of the code using these flags will use DPRINTF or a
>> similar macro, this include could be added to base/trace.hh, so that most
>> of the times it would be included transitively.
>>
>> The advantage of this change is that debugging becomes easier/faster:
>> this file would behave as a library of supported flags and very few
>> header files would suffice for all debugging needs. The disadvantage is
>> that every time a commit introduces or removes a debug flag debug/flags.hh
>> will be recompiled, which will cause an almost complete build. Luckily,
>> debug flags are not frequently modified.
>>
>> Performance-wise both approaches are similar.
>>
>> What are your opinions in this matter?
>>
>> Cheers,
>> Daniel
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm,arch-riscv,arch-x86: Add units to stats

2021-01-20 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39416 )



Change subject: arch-arm,arch-riscv,arch-x86: Add units to stats
..

arch-arm,arch-riscv,arch-x86: Add units to stats

Change-Id: I6bf506c223207306d71511491e024546b209030f
Signed-off-by: Hoa Nguyen 
---
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/riscv/tlb.cc
M src/arch/x86/tlb.cc
4 files changed, 84 insertions(+), 62 deletions(-)



diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e658b02..1daab68 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -2317,25 +2317,31 @@

 TableWalker::TableWalkerStats::TableWalkerStats(Stats::Group *parent)
 : Stats::Group(parent),
-ADD_STAT(walks, "Table walker walks requested"),
-ADD_STAT(walksShortDescriptor, "Table walker walks initiated with"
-" short descriptors"),
-ADD_STAT(walksLongDescriptor, "Table walker walks initiated with"
-" long descriptors"),
-ADD_STAT(walksShortTerminatedAtLevel, "Level at which table walker"
-" walks with short descriptors terminate"),
-ADD_STAT(walksLongTerminatedAtLevel, "Level at which table walker"
-" walks with long descriptors terminate"),
-ADD_STAT(squashedBefore, "Table walks squashed before starting"),
-ADD_STAT(squashedAfter, "Table walks squashed after completion"),
-ADD_STAT(walkWaitTime, "Table walker wait (enqueue to first request)"
-" latency"),
-ADD_STAT(walkServiceTime, "Table walker service (enqueue to  
completion)"

-" latency"),
-ADD_STAT(pendingWalks, "Table walker pending requests distribution"),
-ADD_STAT(pageSizes, "Table walker page sizes translated"),
-ADD_STAT(requestOrigin, "Table walker requests started/completed,"
-" data/inst")
+ADD_STAT_WITH_UNIT(walks, UNIT_COUNT, "Table walker walks requested"),
+ADD_STAT_WITH_UNIT(walksShortDescriptor, UNIT_COUNT,
+   "Table walker walks initiated with short  
descriptors"),

+ADD_STAT_WITH_UNIT(walksLongDescriptor, UNIT_COUNT,
+   "Table walker walks initiated with long  
descriptors"),

+ADD_STAT_WITH_UNIT(walksShortTerminatedAtLevel, UNIT_COUNT,
+   "Level at which table walker walks with short "
+   "descriptors terminate"),
+ADD_STAT_WITH_UNIT(walksLongTerminatedAtLevel, UNIT_COUNT,
+   "Level at which table walker walks with long "
+   "descriptors terminate"),
+ADD_STAT_WITH_UNIT(squashedBefore, UNIT_COUNT,
+   "Table walks squashed before starting"),
+ADD_STAT_WITH_UNIT(squashedAfter, UNIT_COUNT,
+   "Table walks squashed after completion"),
+ADD_STAT_WITH_UNIT(walkWaitTime, UNIT_TICK,
+   "Table walker wait (enqueue to first request)  
latency"),

+ADD_STAT_WITH_UNIT(walkServiceTime, UNIT_TICK,
+   "Table walker service (enqueue to completion)  
latency"),

+ADD_STAT_WITH_UNIT(pendingWalks, UNIT_TICK,
+   "Table walker pending requests distribution"),
+ADD_STAT_WITH_UNIT(pageSizes, UNIT_COUNT,
+   "Table walker page sizes translated"),
+ADD_STAT_WITH_UNIT(requestOrigin, UNIT_COUNT,
+   "Table walker requests started/completed,  
data/inst")

 {
 walksShortDescriptor
 .flags(Stats::nozero);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5d2ed90..3866688 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -502,34 +502,45 @@

 TLB::TlbStats::TlbStats(Stats::Group *parent)
   : Stats::Group(parent),
-ADD_STAT(instHits,"ITB inst hits"),
-ADD_STAT(instMisses, "ITB inst misses"),
-ADD_STAT(readHits, "DTB read hits"),
-ADD_STAT(readMisses, "DTB read misses"),
-ADD_STAT(writeHits, "DTB write hits"),
-ADD_STAT(writeMisses, "DTB write misses"),
-ADD_STAT(inserts, "Number of times an entry is inserted into the TLB"),
-ADD_STAT(flushTlb, "Number of times complete TLB was flushed"),
-ADD_STAT(flushTlbMva, "Number of times TLB was flushed by MVA"),
-ADD_STAT(flushTlbMvaAsid, "Number of times TLB was flushed by MVA &  
ASID"),

-ADD_STAT(flushTlbAsid, "Number of times TLB was flushed by ASID"),
-ADD_STAT(flushedEntries, "Number of entries that have been flushed"
-" from TLB"),
-ADD_STAT(alignFaults, "Number of TLB faults due to alignment"
-" restrictions"),
-ADD_STAT(prefetchFaults, "Number of TLB faults due to prefetch"),
-ADD_STAT(domainFaults, "Number of TLB faults due to domain  
restrictions"),

-ADD_STAT(permsFaults, "Number of TLB faults due to permissions"
-" restrictions"),
-ADD_STAT(readAccesses, "DTB read accesses", readHits + readMisses),
-ADD_STAT(writeAccesses, "DTB

[gem5-dev] Change in gem5/gem5[develop]: dev,dev-arm: Add units to stats in /src/dev

2021-01-20 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39415 )



Change subject: dev,dev-arm: Add units to stats in /src/dev
..

dev,dev-arm: Add units to stats in /src/dev

Change-Id: I9d2449ef173f2f467717a9d233aef8d9a2f43f26
Signed-off-by: Hoa Nguyen 
---
M src/dev/arm/flash_device.cc
M src/dev/arm/hdlcd.cc
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/ufs_device.cc
M src/dev/net/etherdevice.cc
M src/dev/net/sinic.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
9 files changed, 226 insertions(+), 128 deletions(-)



diff --git a/src/dev/arm/flash_device.cc b/src/dev/arm/flash_device.cc
index 533b3ed..138bdc2 100644
--- a/src/dev/arm/flash_device.cc
+++ b/src/dev/arm/flash_device.cc
@@ -458,12 +458,16 @@
 FlashDevice::
 FlashDeviceStats::FlashDeviceStats(Stats::Group *parent)
 : Stats::Group(parent, "FlashDevice"),
-ADD_STAT(totalGCActivations, "Number of Garbage collector  
activations"),

-ADD_STAT(writeAccess, "Histogram of write addresses"),
-ADD_STAT(readAccess, "Histogram of read addresses"),
-ADD_STAT(fileSystemAccess, "Histogram of file system accesses"),
-ADD_STAT(writeLatency, "Histogram of write latency"),
-ADD_STAT(readLatency, "Histogram of read latency")
+ADD_STAT_WITH_UNIT(totalGCActivations, UNIT_COUNT,
+   "Number of Garbage collector activations"),
+ADD_STAT_WITH_UNIT(writeAccess, UNIT_COUNT,
+   "Histogram of write addresses"),
+ADD_STAT_WITH_UNIT(readAccess, UNIT_COUNT,
+   "Histogram of read addresses"),
+ADD_STAT_WITH_UNIT(fileSystemAccess, UNIT_COUNT,
+   "Histogram of file system accesses"),
+ADD_STAT_WITH_UNIT(writeLatency, UNIT_TICK, "Histogram of write  
latency"),

+ADD_STAT_WITH_UNIT(readLatency, UNIT_TICK, "Histogram of read latency")
 {
 using namespace Stats;

diff --git a/src/dev/arm/hdlcd.cc b/src/dev/arm/hdlcd.cc
index c6ff6db..f3959ec 100644
--- a/src/dev/arm/hdlcd.cc
+++ b/src/dev/arm/hdlcd.cc
@@ -81,7 +81,7 @@
 HDLcd::
 HDLcdStats::HDLcdStats(Stats::Group *parent)
 : Stats::Group(parent, "HDLcd"),
-  ADD_STAT(underruns, "Number of buffer underruns")
+  ADD_STAT_WITH_UNIT(underruns, UNIT_COUNT, "Number of buffer  
underruns")

 {
 using namespace Stats;

diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index 3076f5e..01a45ef 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -746,12 +746,13 @@

 SMMUv3::SMMUv3Stats::SMMUv3Stats(Stats::Group *parent)
 : Stats::Group(parent),
-  ADD_STAT(steL1Fetches, "STE L1 fetches"),
-  ADD_STAT(steFetches, "STE fetches"),
-  ADD_STAT(cdL1Fetches, "CD L1 fetches"),
-  ADD_STAT(cdFetches, "CD fetches"),
-  ADD_STAT(translationTimeDist, "Time to translate address"),
-  ADD_STAT(ptwTimeDist, "Time to walk page tables")
+  ADD_STAT_WITH_UNIT(steL1Fetches, UNIT_COUNT, "STE L1 fetches"),
+  ADD_STAT_WITH_UNIT(steFetches, UNIT_COUNT, "STE fetches"),
+  ADD_STAT_WITH_UNIT(cdL1Fetches, UNIT_COUNT, "CD L1 fetches"),
+  ADD_STAT_WITH_UNIT(cdFetches, UNIT_COUNT, "CD fetches"),
+  ADD_STAT_WITH_UNIT(translationTimeDist, UNIT_TICK,
+ "Time to translate address"),
+  ADD_STAT_WITH_UNIT(ptwTimeDist, UNIT_TICK, "Time to walk page  
tables")

 {
 using namespace Stats;

diff --git a/src/dev/arm/smmu_v3_caches.cc b/src/dev/arm/smmu_v3_caches.cc
index b8f284d..747171e 100644
--- a/src/dev/arm/smmu_v3_caches.cc
+++ b/src/dev/arm/smmu_v3_caches.cc
@@ -84,14 +84,22 @@
 SMMUv3BaseCache::
 SMMUv3BaseCacheStats::SMMUv3BaseCacheStats(Stats::Group *parent)
 : Stats::Group(parent),
-  ADD_STAT(averageLookups, "Average number lookups per second"),
-  ADD_STAT(totalLookups, "Total number of lookups"),
-  ADD_STAT(averageMisses, "Average number misses per second"),
-  ADD_STAT(totalMisses, "Total number of misses"),
-  ADD_STAT(averageUpdates, "Average number updates per second"),
-  ADD_STAT(totalUpdates, "Total number of updates"),
-  ADD_STAT(averageHitRate, "Average hit rate"),
-  ADD_STAT(insertions, "Number of insertions (not replacements)")
+  ADD_STAT_WITH_UNIT(averageLookups,
+ UNIT_RATE(Stats::Units::Count,  
Stats::Units::Second),

+ "Average number lookups per second"),
+  ADD_STAT_WITH_UNIT(totalLookups, UNIT_COUNT,
+ "Total number of lookups"),
+  ADD_STAT_WITH_UNIT(averageMisses,
+ UNIT_RATE(Stats::Units::Count,  
Stats::Units::Second),

+ "Average number misses per second"),
+  ADD_STAT_WITH_UNIT(totalMisses, UNIT_COUNT, "Total number of  
misses"),

+  ADD_STAT_WITH_UNIT(averageUpdates,
+ UNIT_RATE(Stats::Units::Count,

[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: Add units to stats

2021-01-20 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39417 )



Change subject: learning-gem5: Add units to stats
..

learning-gem5: Add units to stats

Change-Id: Iaff6c19b0b87250d15f5afb0763680fafe782d52
Signed-off-by: Hoa Nguyen 
---
M src/learning_gem5/part2/simple_cache.cc
1 file changed, 7 insertions(+), 5 deletions(-)



diff --git a/src/learning_gem5/part2/simple_cache.cc  
b/src/learning_gem5/part2/simple_cache.cc

index 661cae5..f3c9d73 100644
--- a/src/learning_gem5/part2/simple_cache.cc
+++ b/src/learning_gem5/part2/simple_cache.cc
@@ -423,11 +423,13 @@

 SimpleCache::SimpleCacheStats::SimpleCacheStats(Stats::Group *parent)
   : Stats::Group(parent),
-  ADD_STAT(hits, "Number of hits"),
-  ADD_STAT(misses, "Number of misses"),
-  ADD_STAT(missLatency, "Ticks for misses to the cache"),
-  ADD_STAT(hitRatio, "The ratio of hits to the total"
- "accesses to the cache", hits / (hits + misses))
+  ADD_STAT_WITH_UNIT(hits, UNIT_COUNT, "Number of hits"),
+  ADD_STAT_WITH_UNIT(misses, UNIT_COUNT, "Number of misses"),
+  ADD_STAT_WITH_UNIT(missLatency, UNIT_TICK,
+ "Ticks for misses to the cache"),
+  ADD_STAT_WITH_UNIT(hitRatio, UNIT_RATIO,
+ "The ratio of hits to the total accesses to the "
+ "cache", hits / (hits + misses))
 {
 missLatency.init(16); // number of buckets
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39417
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaff6c19b0b87250d15f5afb0763680fafe782d52
Gerrit-Change-Number: 39417
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Don't serialise params in thermal models

2021-01-20 Thread Andreas Sandberg (Gerrit) via gem5-dev 
Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39221 )


Change subject: sim: Don't serialise params in thermal models
..

sim: Don't serialise params in thermal models

ThermalDomain and ThermalReference shouldn't serialise their params.

Change-Id: Idc4438b68c0db1fe312d37888c901f2ea87b1d60
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39221
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
4 files changed, 4 insertions(+), 81 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index e9f4d3c..a5eb33c 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -46,7 +46,6 @@
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_model.hh"
 #include "sim/probe/probe.hh"
-#include "sim/serialize.hh"
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
@@ -80,18 +79,6 @@
 ppThermalUpdate->notify(node->temp);
 }

-void
-ThermalDomain::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_initTemperature);
-}
-
-void
-ThermalDomain::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_initTemperature);
-}
-

 LinearEquation
 ThermalDomain::getEquation(ThermalNode * tn, unsigned n, double step) const
diff --git a/src/sim/power/thermal_domain.hh  
b/src/sim/power/thermal_domain.hh

index 421f340..9da753e 100644
--- a/src/sim/power/thermal_domain.hh
+++ b/src/sim/power/thermal_domain.hh
@@ -93,9 +93,6 @@
   */
 void setSubSystem(SubSystem * ss);

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
   private:
 double _initTemperature;
 ThermalNode * node;
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 9f970de..a37240b 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -45,7 +45,6 @@
 #include "sim/clocked_object.hh"
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_domain.hh"
-#include "sim/serialize.hh"
 #include "sim/sim_object.hh"

 /**
@@ -56,18 +55,6 @@
 {
 }

-void
-ThermalReference::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_temperature);
-}
-
-void
-ThermalReference::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_temperature);
-}
-
 LinearEquation
 ThermalReference::getEquation(ThermalNode * n, unsigned nnodes,
   double step) const {
@@ -83,18 +70,6 @@
 {
 }

-void
-ThermalResistor::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_resistance);
-}
-
-void
-ThermalResistor::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_resistance);
-}
-
 LinearEquation
 ThermalResistor::getEquation(ThermalNode * n, unsigned nnodes,
  double step) const
@@ -130,18 +105,6 @@
 {
 }

-void
-ThermalCapacitor::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_capacitance);
-}
-
-void
-ThermalCapacitor::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_capacitance);
-}
-
 LinearEquation
 ThermalCapacitor::getEquation(ThermalNode * n, unsigned nnodes,
   double step) const
@@ -181,18 +144,6 @@
 }

 void
-ThermalModel::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_step);
-}
-
-void
-ThermalModel::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_step);
-}
-
-void
 ThermalModel::doStep()
 {
 // Calculate new temperatures!
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 295e508..95d0c7a 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -62,9 +62,6 @@
 typedef ThermalResistorParams Params;
 ThermalResistor(const Params );

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 void setNodes(ThermalNode * n1, ThermalNode * n2) {
 node1 = n1;
 node2 = n2;
@@ -75,7 +72,7 @@

   private:
 /* Resistance value in K/W */
-double _resistance;
+const double _resistance;
 /* Nodes connected to the resistor */
 ThermalNode * node1, * node2;
 };
@@ -91,9 +88,6 @@
 typedef ThermalCapacitorParams Params;
 ThermalCapacitor(const Params );

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 LinearEquation getEquation(ThermalNode * tn, unsigned n,
double step) const override;

@@ -104,7 +98,7 @@

   private:
 /* Capacitance value in J/K */
-double _capacitance;
+

[gem5-dev] Change in gem5/gem5[develop]: sim: Thermal model style fixes

2021-01-20 Thread Andreas Sandberg (Gerrit) via gem5-dev 
Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39220 )


Change subject: sim: Thermal model style fixes
..

sim: Thermal model style fixes

Fix various style issues in the thermal model implementation.

Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39220
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
2 files changed, 23 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 408642c..9f970de 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -39,6 +39,7 @@

 #include "base/statistics.hh"
 #include "params/ThermalCapacitor.hh"
+#include "params/ThermalModel.hh"
 #include "params/ThermalReference.hh"
 #include "params/ThermalResistor.hh"
 #include "sim/clocked_object.hh"
@@ -253,24 +254,37 @@
 schedule(stepEvent, curTick() + SimClock::Int::s * _step);
 }

-void ThermalModel::addDomain(ThermalDomain * d) {
+void
+ThermalModel::addDomain(ThermalDomain * d)
+{
 domains.push_back(d);
 entities.push_back(d);
 }
-void ThermalModel::addReference(ThermalReference * r) {
+
+void
+ThermalModel::addReference(ThermalReference * r)
+{
 references.push_back(r);
 entities.push_back(r);
 }
-void ThermalModel::addCapacitor(ThermalCapacitor * c) {
+
+void
+ThermalModel::addCapacitor(ThermalCapacitor * c)
+{
 capacitors.push_back(c);
 entities.push_back(c);
 }
-void ThermalModel::addResistor(ThermalResistor * r) {
+
+void
+ThermalModel::addResistor(ThermalResistor * r)
+{
 resistors.push_back(r);
 entities.push_back(r);
 }

-double ThermalModel::getTemp() const {
+double
+ThermalModel::getTemp() const
+{
 // Just pick the highest temperature
 double temp = 0;
 for (auto & n : eq_nodes)
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 81c1de8..295e508 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -40,16 +40,16 @@

 #include 

-#include "params/ThermalCapacitor.hh"
-#include "params/ThermalModel.hh"
-#include "params/ThermalReference.hh"
-#include "params/ThermalResistor.hh"
 #include "sim/clocked_object.hh"
 #include "sim/power/thermal_domain.hh"
 #include "sim/power/thermal_entity.hh"
 #include "sim/power/thermal_node.hh"
 #include "sim/sim_object.hh"

+struct ThermalCapacitorParams;
+struct ThermalModelParams;
+struct ThermalReferenceParams;
+struct ThermalResistorParams;

 /**
  * A ThermalResistor is used to model a thermal resistance between two

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39220
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Gerrit-Change-Number: 39220
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use

2021-01-20 Thread Ayaz Akram (Gerrit) via gem5-dev 
Ayaz Akram has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38515 )


Change subject: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst  
use

..

arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use

This change adds assembly code for riscv pseudo instructions so
that they can be used with riscv benchmarks.

Change-Id: Ic979fd375e7750e92f52b900bf39e351f629fe2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38515
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M util/m5/README.md
A util/m5/src/abi/riscv/SConsopts
A util/m5/src/abi/riscv/m5op.S
A util/m5/src/abi/riscv/verify_inst.cc
4 files changed, 137 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/m5/README.md b/util/m5/README.md
index cbdff1d..9bae153 100644
--- a/util/m5/README.md
+++ b/util/m5/README.md
@@ -98,6 +98,7 @@
  thumb   | ARM thumb| instruction
  sparc   | 64 bit SPARC | instruction
  x86 | amd64/x86_64 | instruction, address
+ riscv   | 64 bit RISCV | instruction

 ## SCons

@@ -166,6 +167,7 @@
  thumb   | arm   | arm-linux-gnueabihf-
  sparc   | sparc64   | sparc64-linux-gnu-
  x86 | x86_64|
+ riscv   | riscv64   | riscv64-linux-gnu-

 Note that the default setting for the x86 cross compiler prefix is blank,
 meaning that the native/host compiler will be used. If building on a  
non-x86

@@ -254,6 +256,7 @@
  thumb   | instruction
  sparc   | instruction
  x86 | address
+ riscv   | instruction

 The default is usually to use a magic instruction, which for most ABIs is  
the

 only mechanism that's supported, and is what the m5 utility would
diff --git a/util/m5/src/abi/riscv/SConsopts  
b/util/m5/src/abi/riscv/SConsopts

new file mode 100644
index 000..e46ef74
--- /dev/null
+++ b/util/m5/src/abi/riscv/SConsopts
@@ -0,0 +1,32 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+env['ABI'] = 'riscv'
+get_abi_opt('CROSS_COMPILE', 'riscv64-linux-gnu-')
+get_abi_opt('QEMU_ARCH', 'riscv64')
+
+env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
diff --git a/util/m5/src/abi/riscv/m5op.S b/util/m5/src/abi/riscv/m5op.S
new file mode 100644
index 000..babe854
--- /dev/null
+++ b/util/m5/src/abi/riscv/m5op.S
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this