[gem5-dev] Change in gem5/gem5[develop]: base: Style fixes in cprintf related files.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39535 )
Change subject: base: Style fixes in cprintf related files.
..
base: Style fixes in cprintf related files.
Fix braces, capitalization, missing line breaks, and remove mostly
useless "using namespace std"s.
Change-Id: I1210dd3b918e7cba8e576cbbdf47aa986d9278e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39535
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/base/cprintf.cc
M src/base/cprintf.hh
M src/base/cprintf_formats.hh
3 files changed, 262 insertions(+), 205 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index e7336a8..03fa3cb 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -28,33 +28,32 @@
#include "base/cprintf.hh"
-#include
#include
#include
#include
#include "base/compiler.hh"
+#include "base/logging.hh"
-using namespace std;
-
-namespace cp {
+namespace cp
+{
Print::Print(std::ostream , const std::string )
: stream(stream), format(format.c_str()), ptr(format.c_str()),
cont(false)
{
-saved_flags = stream.flags();
-saved_fill = stream.fill();
-saved_precision = stream.precision();
-saved_width = stream.width();
+savedFlags = stream.flags();
+savedFill = stream.fill();
+savedPrecision = stream.precision();
+savedWidth = stream.width();
}
Print::Print(std::ostream , const char *format)
: stream(stream), format(format), ptr(format), cont(false)
{
-saved_flags = stream.flags();
-saved_fill = stream.fill();
-saved_precision = stream.precision();
-saved_width = stream.width();
+savedFlags = stream.flags();
+savedFill = stream.fill();
+savedPrecision = stream.precision();
+savedWidth = stream.width();
}
Print::~Print()
@@ -72,7 +71,7 @@
switch (*ptr) {
case '%':
if (ptr[1] != '%') {
-process_flag();
+processFlag();
return;
}
stream.put('%');
@@ -80,13 +79,13 @@
break;
case '\n':
-stream << endl;
+stream << std::endl;
++ptr;
break;
case '\r':
++ptr;
if (*ptr != '\n')
-stream << endl;
+stream << std::endl;
break;
default:
@@ -99,7 +98,7 @@
}
void
-Print::process_flag()
+Print::processFlag()
{
bool done = false;
bool end_number = false;
@@ -107,24 +106,25 @@
int number = 0;
stream.fill(' ');
-stream.flags((ios::fmtflags)0);
+stream.flags((std::ios::fmtflags)0);
while (!done) {
++ptr;
if (*ptr >= '0' && *ptr <= '9') {
if (end_number)
continue;
-} else if (number > 0)
+} else if (number > 0) {
end_number = true;
+}
switch (*ptr) {
case 's':
-fmt.format = Format::string;
+fmt.format = Format::String;
done = true;
break;
case 'c':
-fmt.format = Format::character;
+fmt.format = Format::Character;
done = true;
break;
@@ -132,9 +132,9 @@
continue;
case 'p':
-fmt.format = Format::integer;
-fmt.base = Format::hex;
-fmt.alternate_form = true;
+fmt.format = Format::Integer;
+fmt.base = Format::Hex;
+fmt.alternateForm = true;
done = true;
break;
@@ -142,21 +142,21 @@
fmt.uppercase = true;
M5_FALLTHROUGH;
case 'x':
-fmt.base = Format::hex;
-fmt.format = Format::integer;
+fmt.base = Format::Hex;
+fmt.format = Format::Integer;
done = true;
break;
case 'o':
-fmt.base = Format::oct;
-fmt.format = Format::integer;
+fmt.base = Format::Oct;
+fmt.format = Format::Integer;
done = true;
break;
case 'd':
case 'i':
case 'u':
-fmt.format = Format::integer;
+fmt.format = Format::Integer;
done = true;
break;
@@ -164,8 +164,8 @@
fmt.uppercase = true;
M5_FALLTHROUGH;
case 'g':
-fmt.format = Format::floating;
-fmt.float_format = Format::best;
+fmt.format = Format::Floating;
+fmt.floatFormat = Format::Best;
done = true;
break;
@@ -173,14 +173,14 @@
fmt.uppercase = true;
M5_FALLTHROUGH;
case 'e':
-
[gem5-dev] Change in gem5/gem5[develop]: mem: Unclear MemoryAccess debug message
Kelly Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/39616 ) Change subject: mem: Unclear MemoryAccess debug message .. mem: Unclear MemoryAccess debug message This commit removes two excessive printf() arguments that were making the output of the MemoryAccess debug flag unclear. Jira issue: https://gem5.atlassian.net/browse/GEM5-892 Change-Id: I0317b22082d8cc0025d9f0038fd3599496f40896 Reported-by: Jinzheng Tu --- M src/mem/abstract_mem.cc 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index 7e09832..91f76aa 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -352,7 +352,7 @@ DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x data " "%#x %c\n", label, sys->getRequestorName(pkt->req-> requestorId()), size, pkt->getAddr(), -size, pkt->getAddr(), pkt->getUintX(byte_order), +pkt->getUintX(byte_order), pkt->req->isUncacheable() ? 'U' : 'C'); return; } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39616 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0317b22082d8cc0025d9f0038fd3599496f40896 Gerrit-Change-Number: 39616 Gerrit-PatchSet: 1 Gerrit-Owner: Kelly Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Fix building of unittest/stattest.cc.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39564 ) Change subject: tests: Fix building of unittest/stattest.cc. .. tests: Fix building of unittest/stattest.cc. This file wasn't including eventq.hh which it happened to be getting transitively before. Change-Id: I8ce5572651ddd59160d84794bf5efc90c82d83e6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39564 Reviewed-by: Daniel Carvalho Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/unittest/stattest.cc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Daniel Carvalho: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc index 4030735..e58a5a6 100644 --- a/src/unittest/stattest.cc +++ b/src/unittest/stattest.cc @@ -37,6 +37,7 @@ #include "base/statistics.hh" #include "base/types.hh" #include "sim/core.hh" +#include "sim/eventq.hh" #include "sim/init.hh" #include "sim/stat_control.hh" -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39564 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8ce5572651ddd59160d84794bf5efc90c82d83e6 Gerrit-Change-Number: 39564 Gerrit-PatchSet: 4 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: implement POPCNT instruction.
Tong Shen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39615 )
Change subject: arch-x86: implement POPCNT instruction.
..
arch-x86: implement POPCNT instruction.
Change-Id: Id6ddc1245c81a17720885f9038d55d0811ef7f4d
---
M src/arch/x86/decoder_tables.cc
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
M src/arch/x86/isa/microops/regop.isa
4 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/src/arch/x86/decoder_tables.cc b/src/arch/x86/decoder_tables.cc
index 7ee5e01..db749cf 100644
--- a/src/arch/x86/decoder_tables.cc
+++ b/src/arch/x86/decoder_tables.cc
@@ -115,7 +115,7 @@
/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 9 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* A */ 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1,
-/* B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 1,
+/* B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1,
/* C */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* D */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* E */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
@@ -234,7 +234,7 @@
/* 8 */ ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 ,
-/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , ZW, 0 , BY, 0 , 0 , 0 , 0 , 0 ,
+/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 ,
/* C */ 0 , 0 , BY, 0 , BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index f70e7bd..1dfd228 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -755,7 +755,7 @@
0x17: decode OPCODE_OP_BOTTOM3 {
0x0: decode LEGACY_REP {
0x0: WarnUnimpl::jmpe_Jz();
-0x1: WarnUnimpl::popcnt_Gv_Ev();
+0x1: POPCNT(Gv,Ev);
}
//0x1: group10_UD2();
0x1: UD2();
diff --git
a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
index a755d25..7d80e5c 100644
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py
@@ -350,4 +350,19 @@
end:
fault "NoFault"
};
+
+def macroop POPCNT_R_R {
+popcnt reg, regm, reg
+};
+
+def macroop POPCNT_R_M {
+ld t1, seg, sib, disp
+popcnt reg, t1, reg
+};
+
+def macroop POPCNT_R_P {
+rdip t7
+ld t1, seg, riprel, disp
+popcnt reg, t1, reg
+};
'''
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index da1f9ae..4079ca5 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1765,4 +1765,22 @@
code = '''
DestReg = X86ISA::convX87TagsToXTags(FTW);
'''
+
+class Popcnt(RegOp):
+code = '''
+uint64_t result = 0;
+for (int i = 0; i < 64; i++) {
+if (bits(SrcReg1, i)) {
+result++;
+}
+}
+DestReg = result;
+'''
+flag_code = '''
+ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
+if (SrcReg1 == 0) {
+ccFlagBits = ccFlagBits | ZFBit;
+}
+cfofBits = cfofBits & ~(OFBit | CFBit);
+'''
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id6ddc1245c81a17720885f9038d55d0811ef7f4d
Gerrit-Change-Number: 39615
Gerrit-PatchSet: 1
Gerrit-Owner: Tong Shen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Consistently use ISO prefixes
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39576 )
Change subject: mem: Consistently use ISO prefixes
..
mem: Consistently use ISO prefixes
We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.
Here are some examples of commonly used in the industry:
* Storage vendors define 1 MB as 10**6 bytes
* Memory vendors define 1 MB as 2**20 bytes
* Network equipment treats 1Mbit/s as 10**6 bits/s
* Memory vendors define 1Mbit as 2**20 bits
In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.
The quantity 2MX is treated differently by gem5 depending on the unit
X:
* Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
* Interconnect and NoC bandwidths (B/s) use binary prefixes.
* Network bandwidths (bps) use decimal prefixes.
* Memory sizes and storage sizes (B) use binary prefixes.
Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.
Change-Id: I2d24682d207830f3b7b0ad2ff82b55e082cccb32
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39576
Reviewed-by: Richard Cooper
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
Tested-by: kokoro
---
M src/mem/AbstractMemory.py
M src/mem/DRAMInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/tags/Tags.py
7 files changed, 49 insertions(+), 48 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 4c21d52..e1941c3 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -44,9 +44,10 @@
abstract = True
cxx_header = "mem/abstract_mem.hh"
-# A default memory size of 128 MB (starting at 0) is used to
+# A default memory size of 128 MiB (starting at 0) is used to
# simplify the regressions
-range = Param.AddrRange('128MB', "Address range (potentially
interleaved)")
+range = Param.AddrRange('128MiB',
+"Address range (potentially interleaved)")
null = Param.Bool(False, "Do not store data, always return zero")
# All memories are passed to the global physical memory, and
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 85a6092..4f59498 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -259,7 +259,7 @@
# an 8x8 configuration.
class DDR3_1600_8x8(DRAMInterface):
# size of device in bytes
-device_size = '512MB'
+device_size = '512MiB'
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
@@ -268,7 +268,7 @@
burst_length = 8
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
-device_rowbuffer_size = '1kB'
+device_rowbuffer_size = '1KiB'
# 8x8 configuration, so 8 devices
devices_per_rank = 8
@@ -338,7 +338,7 @@
# [2] High performance AXI-4.0 based interconnect for extensible smart
memory
# cubes (E. Azarkhish et. al)
# Assumed for the HMC model is a 30 nm technology node.
-# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory
(4
+# The modelled HMC consists of 4 Gbit layers which sum up to 2GiB of
memory (4
# layers).
# Each layer has 16 vaults and each vault consists of 2 banks per layer.
# In order to be able to use the same controller used for 2D DRAM
generations
@@ -354,8 +354,8 @@
# of the HMC
class HMC_2500_1x32(DDR3_1600_8x8):
# size of device
-# two banks per device with each bank 4MB [2]
-device_size = '8MB'
+# two banks per device with each bank 4MiB [2]
+device_size = '8MiB'
# 1x32 configuration, 1 device with 32 TSVs [2]
device_bus_width = 32
@@ -458,11 +458,11 @@
# A single DDR4-2400 x64 channel (one command and address bus), with
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
# in an 16x4 configuration.
-# Total channel capacity is 32GB
-# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
+# Total channel capacity is 32GiB
+# 16 devices/rank * 2 ranks/channel * 1GiB/device = 32GiB/channel
class DDR4_2400_16x4(DRAMInterface):
# size of
[gem5-dev] Change in gem5/gem5[develop]: sim-se: Handle simultaneous page faults in SE-mode multithreading
Jiayi Huang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39515 )
Change subject: sim-se: Handle simultaneous page faults in SE-mode
multithreading
..
sim-se: Handle simultaneous page faults in SE-mode multithreading
When running multithreaded programs in SE-mode with DerivO3CPU model,
there are cases that two or more cores have page faults on the same page
in nearby ticks (can be at the same tick) when fetching instructions
(more likely) or accessing data. When these cores try come to the commit
stage in nearby ticks/cycles, they will try to handle the faults
(without clobbering). Then the first core will ask for a physical page
frame to map with the virtual page. In the previous version, the right
next core that tries to handle the fault will hit a panic condition in
the EmulationPageTable::map(...) as the page has been mapped and this
page fault is not to clobber the existing mapping.
In this changeset, if it is found that the page has been mapped and it
is not to clobber the existing mapping, it will return without further
mapping activities as the page fault has been handled previously.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-798
Change-Id: I9bb1163f9d1379c6fed9725101e4400fefdc8079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39515
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/process.cc
1 file changed, 15 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 7819820..409b48a 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -307,6 +307,21 @@
void
Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
+// Check if the page has been mapped by other cores if not to clobber.
+// When running multithreaded programs in SE-mode with DerivO3CPU
model,
+// there are cases where two or more cores have page faults on the same
+// page in nearby ticks. When the cores try to handle the faults at the
+// commit stage (also in nearby ticks/cycles), the first core will ask
for
+// a physical page frame to map with the virtual page. Other cores can
+// return if the page has been mapped and `!clobber`.
+if (!clobber) {
+const EmulationPageTable::Entry *pte = pTable->lookup(vaddr);
+if (pte) {
+warn("Process::allocateMem: addr %#x already mapped\n", vaddr);
+return;
+}
+}
+
int npages = divCeil(size, pTable->pageSize());
Addr paddr = system->allocPhysPages(npages);
pTable->map(vaddr, paddr, size,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9bb1163f9d1379c6fed9725101e4400fefdc8079
Gerrit-Change-Number: 39515
Gerrit-PatchSet: 2
Gerrit-Owner: Jiayi Huang
Gerrit-Reviewer: Brandon Potter
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jiayi Huang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove Python 2.7 compatibility code
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39584 ) Change subject: python: Remove Python 2.7 compatibility code .. python: Remove Python 2.7 compatibility code We don't support Python 2.7 anymore. Remove glue code like the six dependency and "from __future__" imports from gem5's standard library. Change-Id: I71834c325f86ff0329b222be87794ead96081f05 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39584 Tested-by: kokoro Reviewed-by: Gabe Black Maintainer: Jason Lowe-Power --- M src/python/importer.py M src/python/m5/SimObject.py M src/python/m5/__init__.py M src/python/m5/core.py M src/python/m5/debug.py M src/python/m5/event.py M src/python/m5/ext/__init__.py M src/python/m5/internal/params.py M src/python/m5/main.py M src/python/m5/objects/__init__.py M src/python/m5/options.py M src/python/m5/params.py M src/python/m5/proxy.py M src/python/m5/simulate.py M src/python/m5/stats/__init__.py M src/python/m5/ticks.py M src/python/m5/trace.py M src/python/m5/util/__init__.py M src/python/m5/util/attrdict.py M src/python/m5/util/code_formatter.py M src/python/m5/util/convert.py M src/python/m5/util/dot_writer.py M src/python/m5/util/fdthelper.py M src/python/m5/util/grammar.py M src/python/m5/util/jobfile.py M src/python/m5/util/multidict.py M src/python/m5/util/pybind.py M src/python/m5/util/terminal.py 28 files changed, 32 insertions(+), 133 deletions(-) Approvals: Gabe Black: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/importer.py b/src/python/importer.py index c29fb7b..b89b4a8 100644 --- a/src/python/importer.py +++ b/src/python/importer.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - # Simple importer that allows python to import data from a dict of # code objects. The keys are the module path, and the items are the # filename and bytecode of the file. diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index b47d98d..1697237 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -38,13 +38,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import -from six import add_metaclass -import six -if six.PY3: -long = int - import sys from types import FunctionType, MethodType, ModuleType from functools import wraps @@ -1178,8 +1171,7 @@ # The SimObject class is the root of the special hierarchy. Most of # the code in this class deals with the configuration hierarchy itself # (parent/child node relationships). -@add_metaclass(MetaSimObject) -class SimObject(object): +class SimObject(object, metaclass=MetaSimObject): # Specify metaclass. Any class inheriting from SimObject will # get this metaclass. type = 'SimObject' diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 309764d..254d9a6 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - # Import useful subpackages of M5, but *only* when run as an m5 # script. This is mostly to keep backward compatibility with existing # scripts while allowing new SCons code to operate properly. diff --git a/src/python/m5/core.py b/src/python/m5/core.py index 34d54bc..fcbf4aa 100644 --- a/src/python/m5/core.py +++ b/src/python/m5/core.py @@ -36,8 +36,5 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from _m5.core import setOutputDir from _m5.loader import setInterpDir diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py index 6b45b16..10d0980 100644 --- a/src/python/m5/debug.py +++ b/src/python/m5/debug.py @@ -24,8 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - from collections import Mapping import _m5.debug diff --git a/src/python/m5/event.py b/src/python/m5/event.py index 9b5532c..f0230cf 100644 --- a/src/python/m5/event.py +++ b/src/python/m5/event.py @@ -38,8 +38,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS
[gem5-dev] Change in gem5/gem5[develop]: scons: Remove Python 2.7 compatibility code
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39585 )
Change subject: scons: Remove Python 2.7 compatibility code
..
scons: Remove Python 2.7 compatibility code
Remove the dependency on six and most 'import x from __future__'. A
few instances of imports from the future have been left in place to
ensure that Python 2.7 users still get an error message when invoking
scons.
Change-Id: I366275a6040f0084e91198b5b5c2a648bffbf2d2
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39585
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
M SConstruct
M ext/libelf/SConscript
M ext/systemc/SConscript
M ext/systemc/src/sysc/kernel/SConscript.sc
M site_scons/gem5_scons/__init__.py
M site_scons/site_tools/git.py
M src/SConscript
M src/mem/ruby/SConscript
M src/systemc/tests/SConscript
9 files changed, 5 insertions(+), 26 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index b5505ff..4cf2f10 100755
--- a/SConstruct
+++ b/SConstruct
@@ -75,8 +75,6 @@
#
###
-from __future__ import print_function
-
# Global Python includes
import atexit
import itertools
diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript
index 3bf5b30..e2cc847 100644
--- a/ext/libelf/SConscript
+++ b/ext/libelf/SConscript
@@ -28,8 +28,6 @@
#
# Authors: Nathan Binkert
-from __future__ import print_function
-
import os, subprocess
Import('main')
diff --git a/ext/systemc/SConscript b/ext/systemc/SConscript
index cb0c61d..0b6fb0c 100644
--- a/ext/systemc/SConscript
+++ b/ext/systemc/SConscript
@@ -23,8 +23,6 @@
# Authors: Christian Menard
# Matthias Jung
-from __future__ import print_function
-
import os
from m5.util.terminal import get_termcap
diff --git a/ext/systemc/src/sysc/kernel/SConscript.sc
b/ext/systemc/src/sysc/kernel/SConscript.sc
index ac79c2f..0e21f74 100644
--- a/ext/systemc/src/sysc/kernel/SConscript.sc
+++ b/ext/systemc/src/sysc/kernel/SConscript.sc
@@ -23,8 +23,6 @@
# Authors: Christian Menard
# Matthias Jung
-from __future__ import print_function
-
Import('systemc', 'SystemCSource')
SystemCSource(
diff --git a/site_scons/gem5_scons/__init__.py
b/site_scons/gem5_scons/__init__.py
index 4208cf1..708002f 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -38,8 +38,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import os
import sys
import textwrap
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index 87738b8..a77cffb 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -38,13 +38,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
import os
import sys
import gem5_scons.util
from m5.util import readCommand
-from six.moves import input
git_style_message = """
You're missing the gem5 style or commit message hook. These hooks help
diff --git a/src/SConscript b/src/SConscript
index b55f485..dc57260 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -37,8 +37,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import array
import bisect
import distutils.spawn
@@ -46,7 +44,6 @@
import imp
import os
import re
-import six
import sys
import zlib
@@ -144,8 +141,7 @@
super(SourceMeta, cls).__init__(name, bases, dict)
cls.all = SourceList()
-@six.add_metaclass(SourceMeta)
-class SourceFile(object):
+class SourceFile(object, metaclass=SourceMeta):
'''Base object that encapsulates the notion of a source file.
This includes, the source node, target node, various manipulations
of those. A source file also specifies a set of tags which
@@ -157,14 +153,14 @@
def __init__(self, source, tags=None, add_tags=None, append=None):
if tags is None:
tags='gem5 lib'
-if isinstance(tags, six.string_types):
+if isinstance(tags, str):
tags = set([tags])
if not isinstance(tags, set):
tags = set(tags)
self.tags = tags
if add_tags:
-if isinstance(add_tags, six.string_types):
+if isinstance(add_tags, str):
add_tags = set([add_tags])
if not isinstance(add_tags, set):
add_tags = set(add_tags)
@@ -266,7 +262,7 @@
cpp_code(symbol_declaration + ' = {')
[gem5-dev] Change in gem5/gem5[develop]: dev: Consistently use ISO prefixes
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39578 )
Change subject: dev: Consistently use ISO prefixes
..
dev: Consistently use ISO prefixes
We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.
Here are some examples of commonly used in the industry:
* Storage vendors define 1 MB as 10**6 bytes
* Memory vendors define 1 MB as 2**20 bytes
* Network equipment treats 1Mbit/s as 10**6 bits/s
* Memory vendors define 1Mbit as 2**20 bits
In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.
The quantity 2MX is treated differently by gem5 depending on the unit
X:
* Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
* Interconnect and NoC bandwidths (B/s) use binary prefixes.
* Network bandwidths (bps) use decimal prefixes.
* Memory sizes and storage sizes (B) use binary prefixes.
Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.
Change-Id: I6ab03934af850494d95a37dcda5c2000794b4d3a
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39578
Reviewed-by: Richard Cooper
Reviewed-by: Daniel Carvalho
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/dev/net/Ethernet.py
M src/dev/pci/CopyEngine.py
M src/dev/x86/Pc.py
3 files changed, 20 insertions(+), 19 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, but someone else must approve
Gabe Black: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index dd878e2..e5c5562 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -92,10 +92,11 @@
type = 'EtherSwitch'
cxx_header = "dev/net/etherswitch.hh"
dump = Param.EtherDump(NULL, "dump object")
-fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed
in bits "
- "per second")
+fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed
in "
+ "bits per second")
interface = VectorEtherInt("Ethernet Interface")
-output_buffer_size = Param.MemorySize('1MB', "size of output port
buffers")
+output_buffer_size = Param.MemorySize('1MiB',
+ "size of output port buffers")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
time_to_live = Param.Latency('10ms', "time to live of MAC address
maping")
@@ -139,8 +140,8 @@
cxx_header = "dev/net/i8254xGBe.hh"
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
-rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
-tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
+rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
+tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO")
rx_desc_cache_size = Param.Int(64,
"Number of enteries in the rx descriptor cache")
tx_desc_cache_size = Param.Int(64,
@@ -152,7 +153,7 @@
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
-BAR0 = PciMemBar(size='128kB')
+BAR0 = PciMemBar(size='128KiB')
MaximumLatency = 0x00
MinimumGrant = 0xff
InterruptLine = 0x1e
@@ -195,8 +196,8 @@
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")
-rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
-tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
+rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo")
+tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo")
rx_filter = Param.Bool(True, "Enable Receive Filter")
intr_delay = Param.Latency('10us', "Interrupt propagation delay")
@@ -218,7 +219,7 @@
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
-BARs = (PciIoBar(size='256B'), PciMemBar(size='4kB'))
+BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB'))
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
@@ -232,12 +233,12 @@
cxx_header = "dev/net/sinic.hh"
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
-
[gem5-dev] Change in gem5/gem5[develop]: sim,base: make checkpointMapIn warn if an unknown key is found
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37575 )
Change subject: sim,base: make checkpointMapIn warn if an unknown key is
found
..
sim,base: make checkpointMapIn warn if an unknown key is found
The warning happens when a key is present in the checkpoint but not in the
values that gem5 source code knows about.
To do this, we must expose iteration over IniFile section keys. To not
have to make those classes public, a visitor method is implemented.
Change-Id: I23340a953f3e604642b97690a7328b10fdd740a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37575
Reviewed-by: Daniel Carvalho
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/base/inifile.cc
M src/base/inifile.hh
M src/sim/serialize.cc
M src/sim/serialize.hh
4 files changed, 54 insertions(+), 1 deletion(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/inifile.cc b/src/base/inifile.cc
index 1fbebb4..b2eeafc 100644
--- a/src/base/inifile.cc
+++ b/src/base/inifile.cc
@@ -345,3 +345,25 @@
i->second->dump(i->first);
}
}
+
+IniFile::Section::EntryTable::const_iterator
+IniFile::Section::begin() const
+{
+return table.begin();
+}
+
+IniFile::Section::EntryTable::const_iterator
+IniFile::Section::end() const
+{
+return table.end();
+}
+
+void
+IniFile::visitSection(const std::string ,
+IniFile::VisitSectionCallback cb)
+{
+const auto& section = *table.at(sectionName);
+for (const auto& pair : section) {
+cb(pair.first, pair.second->getValue());
+}
+}
diff --git a/src/base/inifile.hh b/src/base/inifile.hh
index 095d132..ae6dc45 100644
--- a/src/base/inifile.hh
+++ b/src/base/inifile.hh
@@ -30,6 +30,7 @@
#define __INIFILE_HH__
#include
+#include
#include
#include
#include
@@ -132,6 +133,9 @@
/// Print the contents of this section to cout (for debugging).
void dump(const std::string );
+
+EntryTable::const_iterator begin() const;
+EntryTable::const_iterator end() const;
};
/// SectionTable type. Map of strings to Section object pointers.
@@ -203,6 +207,13 @@
/// Dump contents to cout. For debugging.
void dump();
+
+/// Visitor callback that receives key/value pairs.
+using VisitSectionCallback = std::function;
+
+/// Iterate over key/value pairs of the given section.
+void visitSection(const std::string , VisitSectionCallback
cb);
};
#endif // __INIFILE_HH__
diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index e502d9a..a563332 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -338,6 +338,13 @@
}
void
+CheckpointIn::visitSection(const std::string ,
+IniFile::VisitSectionCallback cb)
+{
+db->visitSection(section, cb);
+}
+
+void
objParamIn(CheckpointIn , const string , SimObject * )
{
const string (Serializable::currentSection());
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 9e25d09..80fac66 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -55,6 +55,7 @@
#include
#include
+#include "base/inifile.hh"
#include "base/logging.hh"
#include "sim/serialize_handlers.hh"
@@ -94,6 +95,8 @@
bool entryExists(const std::string , const std::string );
bool sectionExists(const std::string );
+void visitSection(const std::string ,
+IniFile::VisitSectionCallback cb);
/** @}*/ //end of api_checkout group
// The following static functions have to do with checkpoint
@@ -555,6 +558,16 @@
param[name_to_index[key]] = value;
}
}
+cp.visitSection(
+Serializable::currentSection(),
+[name_to_index](const std::string& key, const std::string& val)
+{
+if (!name_to_index.count(key)) {
+warn("unknown entry found in checkpoint: %s %s %s\n",
+Serializable::currentSection(), key, val);
+}
+}
+);
}
//
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I23340a953f3e604642b97690a7328b10fdd740a8
Gerrit-Change-Number: 37575
Gerrit-PatchSet: 10
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2 compatibility code in Arm configs
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39581 )
Change subject: configs: Remove Python 2 compatibility code in Arm configs
..
configs: Remove Python 2 compatibility code in Arm configs
Remove uses of six and imports from __future__ and use native Python 3
functionality instead.
Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39581
Reviewed-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/dist_bigLITTLE.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/arm/workloads.py
8 files changed, 1 insertion(+), 31 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/arm/baremetal.py
b/configs/example/arm/baremetal.py
index 04f60a1..011883b 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -39,9 +39,6 @@
at: http://www.arm.com/ResearchEnablement/SystemModeling
"""
-from __future__ import print_function
-from __future__ import absolute_import
-
import os
import m5
from m5.util import addToPath
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index e3cee1e..52613c6 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -35,20 +35,12 @@
# System components used by the bigLITTLE.py configuration script
-from __future__ import print_function
-from __future__ import absolute_import
-
-import six
-
import m5
from m5.objects import *
m5.util.addToPath('../../')
from common.Caches import *
from common import ObjectList
-if six.PY3:
-long = int
-
have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
@@ -320,7 +312,7 @@
self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
-assert long(mem_range.size()) >= long(Addr(mem_size))
+assert int(mem_range.size()) >= int(Addr(mem_size))
self.mem_ranges = [
AddrRange(start=mem_range.start, size=mem_size) ]
diff --git a/configs/example/arm/dist_bigLITTLE.py
b/configs/example/arm/dist_bigLITTLE.py
index 1d82666..6d35e53 100644
--- a/configs/example/arm/dist_bigLITTLE.py
+++ b/configs/example/arm/dist_bigLITTLE.py
@@ -36,9 +36,6 @@
# This configuration file extends the example ARM big.LITTLE(tm)
# configuration to enabe dist-gem5 siulations of big.LITTLE systems.
-from __future__ import print_function
-from __future__ import absolute_import
-
import argparse
import os
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 090e071..85213ee 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -36,10 +36,6 @@
# This is an example configuration script for full system simulation of
# a generic ARM bigLITTLE system.
-
-from __future__ import print_function
-from __future__ import absolute_import
-
import argparse
import os
import sys
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index 72c6292..1c7b6b7 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -36,9 +36,6 @@
# This configuration file extends the example ARM big.LITTLE(tm)
# with example power models.
-from __future__ import print_function
-from __future__ import absolute_import
-
import argparse
import os
diff --git a/configs/example/arm/starter_fs.py
b/configs/example/arm/starter_fs.py
index 8dee137..9d0f0d2 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -38,9 +38,6 @@
at: http://www.arm.com/ResearchEnablement/SystemModeling
"""
-from __future__ import print_function
-from __future__ import absolute_import
-
import os
import m5
from m5.util import addToPath
diff --git a/configs/example/arm/starter_se.py
b/configs/example/arm/starter_se.py
index 8b1dbd2..23da8e7 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -38,9 +38,6 @@
at: http://www.arm.com/ResearchEnablement/SystemModeling
"""
-from __future__ import print_function
-from __future__ import absolute_import
-
import os
import m5
from m5.util import addToPath
diff --git a/configs/example/arm/workloads.py
b/configs/example/arm/workloads.py
index ce48cdd..1fb9d00 100644
--- a/configs/example/arm/workloads.py
+++
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove Python 2 compatibility code
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39580 )
Change subject: arch-arm, dev-arm: Remove Python 2 compatibility code
..
arch-arm, dev-arm: Remove Python 2 compatibility code
Remove uses of six and imports from __future__ and use native Python 3
functionality instead.
Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39580
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/css/MHU.py
5 files changed, 7 insertions(+), 7 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7ab4b6e..f7d9cd5 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -108,7 +108,7 @@
# root instead of appended.
def generateMemNode(mem_range):
-node = FdtNode("memory@%x" % long(mem_range.start))
+node = FdtNode("memory@%x" % int(mem_range.start))
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(FdtPropertyWords("reg",
state.addrCells(mem_range.start) +
diff --git a/src/dev/Device.py b/src/dev/Device.py
index af49504..46e992c 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -51,7 +51,7 @@
def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
-node = FdtNode("%s@%x" % (name, long(pio_addr)))
+node = FdtNode("%s@%x" % (name, int(pio_addr)))
node.append(FdtPropertyWords("reg",
state.addrCells(pio_addr) +
state.sizeCells(size) ))
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8fa0edd..81d1f07 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -211,7 +211,7 @@
idreg = Param.UInt32(0x, "ID Register, SYS_ID")
def generateDeviceTree(self, state):
-node = FdtNode("sysreg@%x" % long(self.pio_addr))
+node = FdtNode("sysreg@%x" % int(self.pio_addr))
node.appendCompatible("arm,vexpress-sysreg")
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@
def generateDeviceTree(self, state):
phandle = state.phandle(self)
-node = FdtNode("osc@" + format(long(phandle), 'x'))
+node = FdtNode("osc@" + format(int(phandle), 'x'))
node.appendCompatible("arm,vexpress-osc")
node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
[0x1, int(self.device)]))
@@ -595,7 +595,7 @@
super(MmioSRAM, self).__init__(**kwargs)
def generateDeviceTree(self, state):
-node = FdtNode("sram@%x" % long(self.range.start))
+node = FdtNode("sram@%x" % int(self.range.start))
node.appendCompatible(["mmio-sram"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.range.start) +
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f444d64..85c10ad 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -187,7 +187,7 @@
def generateDeviceTree(self, state):
reg_addr = self.reg_map.start
reg_size = self.reg_map.size()
-node = FdtNode("smmuv3@%x" % long(reg_addr))
+node = FdtNode("smmuv3@%x" % int(reg_addr))
node.appendCompatible("arm,smmu-v3")
node.append(FdtPropertyWords("reg",
state.addrCells(reg_addr) +
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index 878ca22..f5bb7e5 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -89,7 +89,7 @@
scp = Param.Scp(Parent.any, "System Control Processor")
def generateDeviceTree(self, state):
-node = FdtNode("mailbox@%x" % long(self.pio_addr))
+node = FdtNode("mailbox@%x" % int(self.pio_addr))
node.appendCompatible(["arm,mhu", "arm,primecell"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39580
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Gerrit-Change-Number: 39580
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
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[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39582 ) Change subject: configs: Weed out old port terminology in Arm examples .. configs: Weed out old port terminology in Arm examples Stop using the deprecated port names in Arm example scripts. Change-Id: I11fea3e0df945ac64075b647766570604b70cad8 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39582 Reviewed-by: Gabe Black Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M configs/common/MemConfig.py M configs/example/arm/devices.py M configs/example/arm/fs_bigLITTLE.py M configs/example/arm/starter_se.py 4 files changed, 20 insertions(+), 19 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 63301ab..94b1655 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -151,7 +151,7 @@ system.external_memory = m5.objects.ExternalSlave( port_type="tlm_slave", port_data=opt_tlm_memory, -port=system.membus.master, +port=system.membus.mem_side_ports, addr_ranges=system.mem_ranges) system.workload.addr_check = False return @@ -269,12 +269,12 @@ for i in range(len(mem_ctrls)): if opt_mem_type == "HMC_2500_1x32": # Connect the controllers to the membus -mem_ctrls[i].port = xbar[i/4].master +mem_ctrls[i].port = xbar[i/4].mem_side_ports # Set memory device size. There is an independent controller # for each vault. All vaults are same size. mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size else: # Connect the controllers to the membus -mem_ctrls[i].port = xbar.master +mem_ctrls[i].port = xbar.mem_side_ports subsystem.mem_ctrls = mem_ctrls diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py index 52613c6..9ef4d70 100644 --- a/configs/example/arm/devices.py +++ b/configs/example/arm/devices.py @@ -151,7 +151,7 @@ self.l2 = self._l2_type() for cpu in self.cpus: cpu.connectAllPorts(self.toL2Bus) -self.toL2Bus.master = self.l2.cpu_side +self.toL2Bus.mem_side_ports = self.l2.cpu_side def addPMUs(self, ints, events=[]): """ @@ -181,7 +181,7 @@ def connectMemSide(self, bus): try: -self.l2.mem_side = bus.slave +self.l2.mem_side = bus.cpu_side_ports except AttributeError: for cpu in self.cpus: cpu.connectAllPorts(bus) @@ -223,8 +223,9 @@ ]) gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m) -gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, gem5=system.iobus.slave) -gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master) +gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, +gem5=system.iobus.cpu_side_ports) +gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports) gic_g2t.addr_ranges = gic.get_addr_ranges() gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm) gic.amba_s = gic_t2a.amba @@ -255,7 +256,7 @@ self.cpus = [ cpu ] a2t = AmbaToTlmBridge64(amba=cpu.amba) -t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave) +t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.cpu_side_ports) system.gic_hub.a2t = a2t system.gic_hub.t2g = t2g @@ -330,21 +331,21 @@ self.realview.attachPciDevice(dev, self.iobus) def connect(self): -self.iobridge.master = self.iobus.slave -self.iobridge.slave = self.membus.master +self.iobridge.mem_side_port = self.iobus.cpu_side_ports +self.iobridge.cpu_side_port = self.membus.mem_side_ports if self._caches: -self.iocache.mem_side = self.membus.slave -self.iocache.cpu_side = self.iobus.master +self.iocache.mem_side = self.membus.cpu_side_ports +self.iocache.cpu_side = self.iobus.mem_side_ports else: -self.dmabridge.master = self.membus.slave -self.dmabridge.slave = self.iobus.master +self.dmabridge.mem_side_port = self.membus.cpu_side_ports +self.dmabridge.cpu_side_port = self.iobus.mem_side_ports if hasattr(self.realview.gic, 'cpu_addr'): self.gic_cpu_addr = self.realview.gic.cpu_addr self.realview.attachOnChipIO(self.membus, self.iobridge) self.realview.attachIO(self.iobus) -
