[gem5-dev] Change in gem5/gem5[develop]: python: Mesh topology with user-defined layout

2021-01-31 Thread Daecheol You (Gerrit) via gem5-dev 
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40279 )



Change subject: python: Mesh topology with user-defined layout
..

python: Mesh topology with user-defined layout

There is a limitation on mesh configuration
with Mesh_XY since it requires an evenly divisible number of cache
and directory controllers. Mesh_layout enables to configure
mesh router nodes with the user-defined layout file.
A user can describe an attached controller list for each router node
manually

Change-Id: Iea99a01d6f100c36d4a08a8677cb64912d6117d0
---
M configs/network/Network.py
A configs/topologies/Mesh_layout.py
A configs/topologies/layout_example.txt
3 files changed, 345 insertions(+), 0 deletions(-)



diff --git a/configs/network/Network.py b/configs/network/Network.py
index 8690912..f63e27d 100644
--- a/configs/network/Network.py
+++ b/configs/network/Network.py
@@ -38,6 +38,8 @@
   help="check configs/topologies for complete set")
 parser.add_option("--mesh-rows", type="int", default=0,
   help="the number of rows in the mesh topology")
+parser.add_option("--layout-path", type="string",
+  help="Mesh layout file path")
 parser.add_option("--network", type="choice", default="simple",
   choices=['simple', 'garnet'],
   help="""'simple'|'garnet' (garnet2.0 will be
diff --git a/configs/topologies/Mesh_layout.py  
b/configs/topologies/Mesh_layout.py

new file mode 100644
index 000..773543d
--- /dev/null
+++ b/configs/topologies/Mesh_layout.py
@@ -0,0 +1,303 @@
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+#   2016 Georgia Institute of Technology
+#   2021 Samsung Electronics Co., Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from __future__ import print_function
+from __future__ import absolute_import
+
+from collections import defaultdict
+from collections import deque
+
+import re
+
+from m5.params import *
+from m5.objects import *
+
+from common import FileSystemConfig
+
+from topologies.BaseTopology import SimpleTopology
+
+# Create a mesh as descirbed in a layout file.
+# The layout file descirbes the number of rows and columns,
+# and external controllers (caches and directoryies) attached to each node.
+# Please, see configs/topologies/layout_example.txt for further explanation
+
+# Same as Mesh_XY, XY routing is enforced (using link weights)
+# to guarantee deadlock freedom.
+
+class Mesh_layout(SimpleTopology):
+description='Mesh_layout'
+
+def __init__(self, controllers):
+self.nodes = controllers
+self.sep = ':'
+
+# Parse each token in a layout file
+
+def parse_layout(self, path):
+with open(path, 'r') as f:
+while True:
+stream = f.readline()
+if not stream:
+break
+elif stream[0] == '#':
+continue
+
+pos = 0
+while True:
+i = stream.find(self.sep, pos)
+# no token in the stream
+if i < 0:
+break
+token = stream[pos:i].strip()
+yield token
+pos = i + 1
+
+# Make a mesh as described in a layout file
+
+def makeTopology(self, options, network, IntLink, ExtLink, Router):
+nodes

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: create base class for EVS CPU

2021-01-31 Thread Earl Ou (Gerrit) via gem5-dev 
Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40277 )



Change subject: fastmodel: create base class for EVS CPU
..

fastmodel: create base class for EVS CPU

Previously we use attribute and event for communication between gem5
SimObject to systemC fastmodel sc_module. Creating a base class allows us
to perform casting once and get all the interface required. Also,
instead of warning on attribute not found, we should make simulator
panic if the sc_module does not provide the interface we need.

Change-Id: I91e1036cb792d556dfc4010e7a0f138b1519b079
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.cc
M src/arch/arm/fastmodel/iris/cpu.hh
8 files changed, 71 insertions(+), 132 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index d2b9676..897be24 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,16 +104,9 @@
 for (int i = 0; i < p.cores.size(); i++)
 p.cores[i]->setCluster(this, i);

-sc_core::sc_attr_base *base;
-
-base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName);
-auto *gem5_cluster_attr =
-dynamic_cast *>(base);
-panic_if(base && !gem5_cluster_attr,
- "The EVS gem5 CPU cluster attribute was not of type "
- "sc_attribute.");
-if (gem5_cluster_attr)
-gem5_cluster_attr->value = this;
+Iris::BaseCpuEvs* e = dynamic_cast(evs);
+panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
+e->setCluster(this);

 set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC);
 set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index 360a5dd..b4153cc 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -39,19 +39,23 @@

 template 
 void
-ScxEvsCortexA76::clockChangeHandler()
+ScxEvsCortexA76::setClkFrq(uint64_t clk_frq)
 {
-clockRateControl->set_mul_div(SimClock::Int::s, clockPeriod.value);
+clockRateControl->set_mul_div(clk_frq, 1);
+}
+
+template 
+void
+ScxEvsCortexA76::setCluster(SimObject* cluster)
+{
+gem5CpuCluster = dynamic_cast(cluster);
+panic_if(!gem5CpuCluster, "Cluster should be of type  
CortexA76Cluster");

 }

 template 
 ScxEvsCortexA76::ScxEvsCortexA76(
 const sc_core::sc_module_name _name, const Params ) :
 Base(mod_name), amba(Base::amba, p.name + ".amba", -1),
-clockChanged(Iris::ClockEventName.c_str()),
-clockPeriod(Iris::PeriodAttributeName.c_str()),
-gem5CpuCluster(Iris::Gem5CpuClusterAttributeName.c_str()),
-sendFunctional(Iris::SendFunctionalAttributeName.c_str()),
 params(p)
 {
 for (int i = 0; i < CoreCount; i++) {
@@ -82,15 +86,6 @@
 }

 clockRateControl.bind(this->clock_rate_s);
-
-this->add_attribute(gem5CpuCluster);
-this->add_attribute(clockPeriod);
-SC_METHOD(clockChangeHandler);
-this->dont_initialize();
-this->sensitive << clockChanged;
-
-sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); };
-this->add_attribute(sendFunctional);
 }

 template 
@@ -109,12 +104,10 @@
 {
 Base::before_end_of_elaboration();

-auto *cluster = gem5CpuCluster.value;
-
-auto set_on_change = [cluster](
+auto set_on_change = [this](
 SignalReceiver , ArmInterruptPinGen *gen, int num)
 {
-auto *pin = gen->get(cluster->getCore(num)->getContext(0));
+auto *pin = gen->get(gem5CpuCluster->getCore(num)->getContext(0));
 auto handler = [pin](bool status)
 {
 status ? pin->raise() : pin->clear();
@@ -123,15 +116,15 @@
 };

 for (int i = 0; i < CoreCount; i++) {
-set_on_change(*cnthpirq[i], cluster->params().cnthpirq, i);
-set_on_change(*cnthvirq[i], cluster->params().cnthvirq, i);
-set_on_change(*cntpsirq[i], cluster->params().cntpsirq, i);
-set_on_change(*cntvirq[i], cluster->params().cntvirq, i);
-set_on_change(*commirq[i], cluster->params().commirq, i);
-set_on_change(*ctidbgirq[i], cluster->params().ctidbgirq, i);
-set_on_change(*pmuirq[i], cluster->params().pmuirq, i);
-set_on_change(*vcpumntirq[i], cluster->params().vcpumntirq, i);
-set_on_change(*cntpnsirq[i], cluster->params().cntpnsirq, i);
+set_on_change(*cnthpirq[i], gem5CpuCluster->params().cnthpirq, i);
+set_on_change(*cnthvirq[i], gem5CpuCluster->params().cnthvirq, i);
+set_on_change(*cntpsirq[i],

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: remove incorrect cntfrq update

2021-01-31 Thread Earl Ou (Gerrit) via gem5-dev 
Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40276 )



Change subject: fastmodel: remove incorrect cntfrq update
..

fastmodel: remove incorrect cntfrq update

The register cntfrq should be set to system counter frequency.
However, the current fastmodel implementation accidentally set it to
core frequency. This CL removes the wrong implementation, and real
cntfrq setting is performed in the base class's initStat.

Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
1 file changed, 0 insertions(+), 13 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

index 68ff1a8..724b04d 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -66,19 +66,6 @@
 Base(p, scx::scx_get_iris_connection_interface()), _params(p)
 {}

-void
-clockPeriodUpdated() override
-{
-Base::clockPeriodUpdated();
-
-// FIXME(b/139447397): this is a workaround since CNTFRQ_EL0  
should not

-// be modified after clock is changed in real hardwares. Remove or
-// modify this after a more reasonable solution is found.
-for (auto *tc : threadContexts) {
-tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,  
frequency());

-}
-}
-
 void initState() override;

 template 

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c62822a4fbbcc0c499f79f6003dabb0c133f997
Gerrit-Change-Number: 40276
Gerrit-PatchSet: 1
Gerrit-Owner: Earl Ou 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add interface to update system counter freq

2021-01-31 Thread Earl Ou (Gerrit) via gem5-dev 
Earl Ou has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40278 )



Change subject: fastmodel: add interface to update system counter freq
..

fastmodel: add interface to update system counter freq

This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.

Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
M src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
M src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
M src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
M src/arch/arm/fastmodel/iris/cpu.hh
9 files changed, 49 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py

index 0b0fa8d..bbfe18a 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -340,6 +340,7 @@
 "signal).")
 ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\
 "(Timing Annotation), expressed in simulation ticks")
+sys_counter_frq = Param.UInt64(0x180, "The system counter  
frequency")
 tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing  
Annotation), "\

 "expressed in simulation ticks")
 treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index 897be24..7fdc6c2 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -39,8 +39,12 @@
 void
 CortexA76::initState()
 {
+warn_if(params().cntfrq != cluster->params().sys_counter_frq,
+"CNTFRQ configured freq does not match the system counter  
freq\n");

 for (auto *tc : threadContexts)
 tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0,  
params().cntfrq);

+
+evs_base_cpu->setSysCounterFrq(cluster->params().sys_counter_frq);
 }

 void
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc

index b4153cc..c1fe23a 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -46,6 +46,13 @@

 template 
 void
+ScxEvsCortexA76::setSysCounterFrq(uint64_t sys_counter_frq)
+{
+periphClockRateControl->set_mul_div(sys_counter_frq, 1);
+}
+
+template 
+void
 ScxEvsCortexA76::setCluster(SimObject* cluster)
 {
 gem5CpuCluster = dynamic_cast(cluster);
@@ -86,6 +93,7 @@
 }

 clockRateControl.bind(this->clock_rate_s);
+periphClockRateControl.bind(this->periph_clock_rate_s);
 }

 template 
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh

index 64d605a..c8e20fd 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -63,6 +63,7 @@
 SC_HAS_PROCESS(ScxEvsCortexA76);

 ClockRateControlInitiatorSocket clockRateControl;
+ClockRateControlInitiatorSocket periphClockRateControl;

 typedef sc_gem5::TlmTargetBaseWrapper<
 64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@

 void setClkFrq(uint64_t clk_frq) override;

+void setSysCounterFrq(uint64_t sys_counter_frq) override;
+
 void setCluster(SimObject* cluster) override;
 };

diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa  
b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa

index 1968931..04dae41 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -35,7 +35,7 @@
 // Clocks.
 clock1Hz : MasterClock();
 clockDiv : ClockDivider();
-clockDivPeriph : ClockDivider(mul=0x0180);
+clockDivPeriph : ClockDivider();
 }

 connection
@@ -77,6 +77,13 @@
 clockDiv.rate.set64(mul, div);
 }
 }
+slave port periph_clock_rate_s
+{
+behavior set_mul_div(uint64_t mul, uint64_t div)
+{
+clockDivPeriph.rate.set64(mul, div);
+}
+}
 slave port redistributor[1];

 // External ports for CPU-to-GIC signals
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa  
b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa

index e0f7a93..0279140 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -35,7 +35,7 @@
 // Clocks.
 clock1Hz : MasterClock();
 clockDiv : ClockDivider();
-clockDivPeriph : ClockDivider(mul=0x0180);
+clockDivPeriph : ClockDivider();
 }

 connection
@@ -77,6

[gem5-dev] Change in gem5/gem5[develop]: systemc: set Gem5ToTlmBridge blockingRrequest with TLM_UPDATE returning

2021-01-31 Thread Yu-hsin Wang (Gerrit) via gem5-dev 
Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39815 )


Change subject: systemc: set Gem5ToTlmBridge blockingRrequest with  
TLM_UPDATE returning

..

systemc: set Gem5ToTlmBridge blockingRrequest with TLM_UPDATE returning

In Gem5ToTlmBridge::pec, the function expects blockingRequest should be
set no matter the tlm peer returns TLM_UPDATE or TLM_ACCEPTED.
However, current implementation only sets blockingRequest when the tlm
peer returns TLM_ACCEPTED. We should also set blockingRequest when the
tlm peer returns TLM_UPDATE.

Change-Id: I87bba3201cd68d52ded93c9c200f4fa4a40bdf5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39815
Reviewed-by: Earl Ou 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/systemc/tlm_bridge/gem5_to_tlm.cc
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Earl Ou: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.cc  
b/src/systemc/tlm_bridge/gem5_to_tlm.cc

index 9d10876..b80a083 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.cc
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.cc
@@ -364,6 +364,8 @@
 } else if (status == tlm::TLM_UPDATED) {
 // The Timing annotation must be honored:
 sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
+// Accepted but is now blocking until END_REQ (exclusion rule).
+blockingRequest = trans;
 auto cb = [this, trans, phase]() { pec(*trans, phase); };
 system->schedule(new EventFunctionWrapper(cb, "pec", true),
  curTick() + delay.value());

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I87bba3201cd68d52ded93c9c200f4fa4a40bdf5b
Gerrit-Change-Number: 39815
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jui-min Lee 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Added packet distribution stats

2021-01-31 Thread Daecheol You (Gerrit) via gem5-dev 
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40275 )



Change subject: mem-garnet: Added packet distribution stats
..

mem-garnet: Added packet distribution stats

Trace data and control traffic between all source-destination pairs.
This is for making realistic synthetic traffic based on the real
application execution.

Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
JIRA: https://gem5.atlassian.net/browse/GEM5-861
---
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/NetworkInterface.cc
3 files changed, 60 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.cc  
b/src/mem/ruby/network/garnet/GarnetNetwork.cc

index 91015ff..9d4d0f0 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.cc
@@ -500,6 +500,25 @@
 .name(name() + ".avg_vc_load")
 .flags(Stats::pdf | Stats::total | Stats::nozero | Stats::oneline)
 ;
+
+// Traffic distribution
+for (int source = 0; source < m_routers.size(); ++source) {
+m_data_traffic_distribution.push_back(std::vector*>());
+m_ctrl_traffic_distribution.push_back(std::vector*>());

+
+for (int dest = 0; dest < m_routers.size(); ++dest) {
+Stats::Scalar *data_packets = new Stats::Scalar();
+Stats::Scalar *ctrl_packets = new Stats::Scalar();
+
+data_packets->name(name() + ".data_traffic_distribution."  
+ "n" +
+std::to_string(source) + "." + "n" +  
std::to_string(dest));

+m_data_traffic_distribution[source].push_back(data_packets);
+
+ctrl_packets->name(name() + ".ctrl_traffic_distribution."  
+ "n" +
+std::to_string(source) + "." + "n" +  
std::to_string(dest));

+m_ctrl_traffic_distribution[source].push_back(ctrl_packets);
+}
+}
 }

 void
@@ -554,6 +573,39 @@
 out << "[GarnetNetwork]";
 }

+void
+GarnetNetwork::update_traffic_distribution(RouteInfo route,
+   MessageSizeType type)
+{
+int src_node = route.src_router;
+int dest_node = route.dest_router;
+std::vector dest = route.net_dest.getAllDest();
+
+/*
+ * All multicast messages were converted into unicast messages
+ * at flitisizeMessage()
+ */
+assert(dest.size() == 1);
+
+bool is_data_msg = false;
+switch(type) {
+case MessageSizeType_Data:
+case MessageSizeType_Response_Data:
+case MessageSizeType_ResponseLocal_Data:
+case MessageSizeType_ResponseL2hit_Data:
+case MessageSizeType_Writeback_Data:
+is_data_msg = true;
+break;
+default:
+break;
+}
+
+if (is_data_msg)
+(*m_data_traffic_distribution[src_node][dest_node])++;
+else
+(*m_ctrl_traffic_distribution[src_node][dest_node])++;
+}
+
 uint32_t
 GarnetNetwork::functionalWrite(Packet *pkt)
 {
diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.hh  
b/src/mem/ruby/network/garnet/GarnetNetwork.hh

index 63c1a2c..7f39f80 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.hh
@@ -142,6 +142,9 @@
 m_total_hops += hops;
 }

+void update_traffic_distribution(RouteInfo route,
+ MessageSizeType type);
+
   protected:
 // Configuration
 int m_num_rows;
@@ -185,6 +188,9 @@
 Stats::Scalar  m_total_hops;
 Stats::Formula m_avg_hops;

+std::vector> m_data_traffic_distribution;
+std::vector> m_ctrl_traffic_distribution;
+
   private:
 GarnetNetwork(const GarnetNetwork& obj);
 GarnetNetwork& operator=(const GarnetNetwork& obj);
diff --git a/src/mem/ruby/network/garnet/NetworkInterface.cc  
b/src/mem/ruby/network/garnet/NetworkInterface.cc

index dc37159..d69bdc9 100644
--- a/src/mem/ruby/network/garnet/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/NetworkInterface.cc
@@ -426,6 +426,8 @@
 route.hops_traversed = -1;

 m_net_ptr->increment_injected_packets(vnet);
+m_net_ptr->update_traffic_distribution(route,
+new_net_msg_ptr->getMessageSize());
 for (int i = 0; i < num_flits; i++) {
 m_net_ptr->increment_injected_flits(vnet);
 flit *fl = new flit(i, vc, vnet, route, num_flits, new_msg_ptr,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40275
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
Gerrit-Change-Number: 40275
Gerrit-PatchSet: 1
Gerrit-Owner: Daecheol You 
Gerrit-MessageType: newchange
___
gem5-dev

[gem5-dev] Re: Build failed in Jenkins: Nightly #205

2021-01-31 Thread Matt Sinclair via gem5-dev 
(Reposting since prior message bounced)

As noted by Gabe last night on the review board, this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/40216, should fix the
failure.

Matt

On Sun, Jan 31, 2021 at 3:08 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/Nightly/205/display/redirect?page=changes>
>
> Changes:
>
> [kyleroarty1716] dev-hsa: enable interruptible hsa signal support
>
>
> --
> [...truncated 44.38 KB...]
>  [ CXX] GCN3_X86/mem/cache/prefetch/slim_ampm.cc -> .o
>  [SO PARAM] STeMSPrefetcher -> GCN3_X86/params/STeMSPrefetcher.hh
>  [ CXX]
> GCN3_X86/mem/cache/prefetch/spatio_temporal_memory_streaming.cc -> .o
>  [SO PARAM] StridePrefetcher -> GCN3_X86/params/StridePrefetcher.hh
>  [SO PARAM] StridePrefetcherHashedSetAssociative ->
> GCN3_X86/params/StridePrefetcherHashedSetAssociative.hh
>  [SO PARAM] SetAssociative -> GCN3_X86/params/SetAssociative.hh
>  [ CXX] GCN3_X86/mem/cache/prefetch/stride.cc -> .o
>  [SO PARAM] TaggedPrefetcher -> GCN3_X86/params/TaggedPrefetcher.hh
>  [ CXX] GCN3_X86/mem/cache/prefetch/tagged.cc -> .o
>  [ TRACING]  -> GCN3_X86/debug/TraceCPUData.hh
>  [ TRACING]  -> GCN3_X86/debug/TraceCPUInst.hh
>  [SO PARAM] TraceCPU -> GCN3_X86/params/TraceCPU.hh
>  [  PROTOC] GCN3_X86/proto/inst_dep_record.proto -> GCN3_X86/proto/
> inst_dep_record.pb.cc, GCN3_X86/proto/inst_dep_record.pb.h
>  [  PROTOC] GCN3_X86/proto/packet.proto -> GCN3_X86/proto/packet.pb.cc,
> GCN3_X86/proto/packet.pb.h
>  [ CXX] GCN3_X86/cpu/trace/trace_cpu.cc -> .o
>  [ TRACING]  -> GCN3_X86/debug/RubyQueue.hh
>  [SO PARAM] RubyNetwork -> GCN3_X86/params/RubyNetwork.hh
>  [MAKE INC] GCN3_X86/mem/ruby/common/DataBlock.hh -> protocol/DataBlock.hh
>  [MAKE INC] GCN3_X86/mem/ruby/common/MachineID.hh -> protocol/MachineID.hh
>  [MAKE INC] GCN3_X86/mem/ruby/slicc_interface/Message.hh ->
> protocol/Message.hh
>  [SO PARAM] RubyController -> GCN3_X86/params/RubyController.hh
>  [SO PARAM] RubySystem -> GCN3_X86/params/RubySystem.hh
>  [SO PARAM] RubySequencer -> GCN3_X86/params/RubySequencer.hh
>  [ TRACING]  -> GCN3_X86/debug/RubySlicc.hh
>  [SO PARAM] MessageBuffer -> GCN3_X86/params/MessageBuffer.hh
>  [MAKE INC] GCN3_X86/mem/ruby/slicc_interface/RubyRequest.hh ->
> protocol/RubyRequest.hh
>  [SO PARAM] RubyCache -> GCN3_X86/params/RubyCache.hh
>  [SO PARAM] RubyPort -> GCN3_X86/params/RubyPort.hh
>  [SO PARAM] BasicExtLink -> GCN3_X86/params/BasicExtLink.hh
>  [SO PARAM] BasicIntLink -> GCN3_X86/params/BasicIntLink.hh
>  [SO PARAM] BasicLink -> GCN3_X86/params/BasicLink.hh
>  [SO PARAM] BasicRouter -> GCN3_X86/params/BasicRouter.hh
>  [SO PARAM] RubyDirectoryMemory -> GCN3_X86/params/RubyDirectoryMemory.hh
>  [SO PARAM] SimpleMemory -> GCN3_X86/params/SimpleMemory.hh
>  [ENUMDECL] MessageRandomization -> GCN3_X86/enums/MessageRandomization.hh
>  [ CXX] GCN3_X86/mem/ruby/slicc_interface/AbstractController.cc -> .o
>  [ TRACING]  -> GCN3_X86/debug/RubyCache.hh
>  [ CXX] GCN3_X86/mem/ruby/slicc_interface/AbstractCacheEntry.cc -> .o
>  [LINK]  -> GCN3_X86/mem/cache/prefetch/lib.o.partial
>  [ CXX] GCN3_X86/mem/ruby/slicc_interface/RubyRequest.cc -> .o
>  [ CXX] GCN3_X86/unittest/unittest.cc -> .o
>  [ CXX] GCN3_X86/mem/ruby/network/BasicLink.cc -> .o
>  [LINK]  -> GCN3_X86/unittest/lib.o.partial
>  [ CXX] GCN3_X86/mem/ruby/network/BasicRouter.cc -> .o
>  [ CXX] GCN3_X86/mem/ruby/network/MessageBuffer.cc -> .o
>  [ CXX] GCN3_X86/mem/ruby/network/Network.cc -> .o
>  [LINK]  -> GCN3_X86/cpu/trace/lib.o.partial
>  [ TRACING]  -> GCN3_X86/debug/RubyNetwork.hh
>  [ CXX] GCN3_X86/mem/ruby/network/Topology.cc -> .o
>  [LINK]  -> GCN3_X86/mem/ruby/slicc_interface/lib.o.partial
>  [ CXX] GCN3_X86/systemc/tlm_core/2/generic_payload/gp.cc -> .o
>  [ CXX] GCN3_X86/systemc/tlm_core/2/generic_payload/phase.cc -> .o
>  [LINK]  -> GCN3_X86/systemc/tlm_core/2/generic_payload/lib.o.partial
>  [ TRACING]  -> GCN3_X86/debug/RubyStats.hh
>  [ CXX] GCN3_X86/mem/ruby/structures/DirectoryMemory.cc -> .o
>  [ TRACING]  -> GCN3_X86/debug/HtmMem.hh
>  [ TRACING]  -> GCN3_X86/debug/RubyCacheTrace.hh
>  [ TRACING]  -> GCN3_X86/debug/RubyResourceStalls.hh
>  [ CXX] GCN3_X86/mem/ruby/structures/CacheMemory.cc -> .o
>  [SO PARAM] RubyWireBuffer -> GCN3_X86/params/RubyWireBuffer.hh
>  [ CXX] GCN3_X86/mem/ruby/structures/WireBuffer.cc -> .o
>  [ CXX] GCN3_X86/mem/ruby/structures/PersistentTable.cc -> .o
>  [LINK]  -> GCN3_X86/mem/ruby/network/lib.o.partial
>  [ TRACING]  -> GCN3_X86/debug/RubyPrefetcher.hh
>  [SO PARAM] RubyPrefetcher -> GCN3_X86/params/RubyPrefetcher.hh
>  [ CXX] GCN3_X86/mem/ruby/structures/RubyPrefetcher.cc -> .o
>  [ CXX] GCN3_X86/mem/ruby/structures/TimerTable.cc -> .o
>  [ CXX] GCN3_X86/mem/ruby/structures/BankedArray.cc -> .o
>  [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/address_manager.cc -> .o
>

[gem5-dev] Re: Change in gem5/gem5[develop]: ext: Update pybind11 to version 6.2.

2021-01-31 Thread Gabe Black via gem5-dev 
This has a typo, it's actually version 2.6.2

On Sun, Jan 31, 2021 at 6:54 AM Gabe Black (Gerrit) via gem5-dev <
gem5-dev@gem5.org> wrote:

> Gabe Black has uploaded this change for *review*.
>
> View Change 
>
> ext: Update pybind11 to version 6.2.
>
> This should help reduce warning spew when building with newer compilers.
> The pybind11::module type has been renamed pybind11::module_ to avoid
> conflicts with c++20 modules, according to the pybind11 changelog, so
> this CL also updates gem5 source to use the new type. There is
> supposedly an alias pybind11::module which is for compatibility, but we
> still get linker errors without changing to pybind11::module_.
>
> Change-Id: I0acb36215b33e3a713866baec43f5af630c356ee
> ---
> M ext/pybind11/.appveyor.yml
> A ext/pybind11/.clang-format
> A ext/pybind11/.clang-tidy
> A ext/pybind11/.cmake-format.yaml
> A ext/pybind11/.github/CONTRIBUTING.md
> A ext/pybind11/.github/ISSUE_TEMPLATE/bug-report.md
> A ext/pybind11/.github/ISSUE_TEMPLATE/config.yml
> A ext/pybind11/.github/ISSUE_TEMPLATE/feature-request.md
> A ext/pybind11/.github/ISSUE_TEMPLATE/question.md
> A ext/pybind11/.github/dependabot.yml
> A ext/pybind11/.github/labeler.yml
> A ext/pybind11/.github/labeler_merged.yml
> A ext/pybind11/.github/pull_request_template.md
> A ext/pybind11/.github/workflows/ci.yml
> A ext/pybind11/.github/workflows/configure.yml
> A ext/pybind11/.github/workflows/format.yml
> A ext/pybind11/.github/workflows/labeler.yml
> A ext/pybind11/.github/workflows/pip.yml
> M ext/pybind11/.gitignore
> D ext/pybind11/.gitmodules
> A ext/pybind11/.pre-commit-config.yaml
> D ext/pybind11/.travis.yml
> M ext/pybind11/CMakeLists.txt
> D ext/pybind11/CONTRIBUTING.md
> D ext/pybind11/ISSUE_TEMPLATE.md
> M ext/pybind11/LICENSE
> M ext/pybind11/MANIFEST.in
> D ext/pybind11/README.md
> A ext/pybind11/README.rst
> M ext/pybind11/docs/Doxyfile
> M ext/pybind11/docs/advanced/cast/custom.rst
> M ext/pybind11/docs/advanced/cast/eigen.rst
> M ext/pybind11/docs/advanced/cast/index.rst
> M ext/pybind11/docs/advanced/cast/stl.rst
> M ext/pybind11/docs/advanced/classes.rst
> M ext/pybind11/docs/advanced/embedding.rst
> M ext/pybind11/docs/advanced/exceptions.rst
> M ext/pybind11/docs/advanced/functions.rst
> M ext/pybind11/docs/advanced/misc.rst
> M ext/pybind11/docs/advanced/pycpp/numpy.rst
> M ext/pybind11/docs/advanced/pycpp/object.rst
> M ext/pybind11/docs/advanced/pycpp/utilities.rst
> M ext/pybind11/docs/basics.rst
> M ext/pybind11/docs/benchmark.py
> M ext/pybind11/docs/benchmark.rst
> M ext/pybind11/docs/changelog.rst
> M ext/pybind11/docs/classes.rst
> A ext/pybind11/docs/cmake/index.rst
> M ext/pybind11/docs/compiling.rst
> M ext/pybind11/docs/conf.py
> M ext/pybind11/docs/faq.rst
> M ext/pybind11/docs/index.rst
> A ext/pybind11/docs/installing.rst
> D ext/pybind11/docs/intro.rst
> M ext/pybind11/docs/limitations.rst
> M ext/pybind11/docs/reference.rst
> M ext/pybind11/docs/release.rst
> M ext/pybind11/docs/requirements.txt
> M ext/pybind11/docs/upgrade.rst
> M ext/pybind11/include/pybind11/attr.h
> M ext/pybind11/include/pybind11/buffer_info.h
> M ext/pybind11/include/pybind11/cast.h
> M ext/pybind11/include/pybind11/chrono.h
> M ext/pybind11/include/pybind11/complex.h
> M ext/pybind11/include/pybind11/detail/class.h
> M ext/pybind11/include/pybind11/detail/common.h
> M ext/pybind11/include/pybind11/detail/descr.h
> M ext/pybind11/include/pybind11/detail/init.h
> M ext/pybind11/include/pybind11/detail/internals.h
> M ext/pybind11/include/pybind11/detail/typeid.h
> M ext/pybind11/include/pybind11/eigen.h
> M ext/pybind11/include/pybind11/embed.h
> M ext/pybind11/include/pybind11/eval.h
> M ext/pybind11/include/pybind11/functional.h
> M ext/pybind11/include/pybind11/iostream.h
> M ext/pybind11/include/pybind11/numpy.h
> M ext/pybind11/include/pybind11/operators.h
> M ext/pybind11/include/pybind11/options.h
> M ext/pybind11/include/pybind11/pybind11.h
> M ext/pybind11/include/pybind11/pytypes.h
> M ext/pybind11/include/pybind11/stl.h
> M ext/pybind11/include/pybind11/stl_bind.h
> M ext/pybind11/pybind11/__init__.py
> M ext/pybind11/pybind11/__main__.py
> M ext/pybind11/pybind11/_version.py
> A ext/pybind11/pybind11/_version.pyi
> A ext/pybind11/pybind11/commands.py
> A ext/pybind11/pybind11/py.typed
> A ext/pybind11/pybind11/setup_helpers.py
> A ext/pybind11/pybind11/setup_helpers.pyi
> A ext/pybind11/pyproject.toml
> M ext/pybind11/setup.cfg
> M ext/pybind11/setup.py
> M ext/pybind11/tests/CMakeLists.txt
> M ext/pybind11/tests/conftest.py
> M ext/pybind11/tests/constructor_stats.h
> A ext/pybind11/tests/env.py
> A ext/pybind11/tests/extra_python_package/pytest.ini
> A ext/pybind11/tests/extra_python_package/test_files.py
> A ext/pybind11/tests/extra_setuptools/pytest.ini
> A ext/pybind11/tests/extra_setuptools/test_setuphelper.py
> M ext/pybind11/tests/local_bindings.h
> M ext/pybind11/tests/pybind11_tests.cpp
> M

[gem5-dev] Change in gem5/gem5[develop]: ext: Update pybind11 to version 6.2.

2021-01-31 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40255 )



Change subject: ext: Update pybind11 to version 6.2.
..

ext: Update pybind11 to version 6.2.

This should help reduce warning spew when building with newer compilers.
The pybind11::module type has been renamed pybind11::module_ to avoid
conflicts with c++20 modules, according to the pybind11 changelog, so
this CL also updates gem5 source to use the new type. There is
supposedly an alias pybind11::module which is for compatibility, but we
still get linker errors without changing to pybind11::module_.

Change-Id: I0acb36215b33e3a713866baec43f5af630c356ee
---
M ext/pybind11/.appveyor.yml
A ext/pybind11/.clang-format
A ext/pybind11/.clang-tidy
A ext/pybind11/.cmake-format.yaml
A ext/pybind11/.github/CONTRIBUTING.md
A ext/pybind11/.github/ISSUE_TEMPLATE/bug-report.md
A ext/pybind11/.github/ISSUE_TEMPLATE/config.yml
A ext/pybind11/.github/ISSUE_TEMPLATE/feature-request.md
A ext/pybind11/.github/ISSUE_TEMPLATE/question.md
A ext/pybind11/.github/dependabot.yml
A ext/pybind11/.github/labeler.yml
A ext/pybind11/.github/labeler_merged.yml
A ext/pybind11/.github/pull_request_template.md
A ext/pybind11/.github/workflows/ci.yml
A ext/pybind11/.github/workflows/configure.yml
A ext/pybind11/.github/workflows/format.yml
A ext/pybind11/.github/workflows/labeler.yml
A ext/pybind11/.github/workflows/pip.yml
M ext/pybind11/.gitignore
D ext/pybind11/.gitmodules
A ext/pybind11/.pre-commit-config.yaml
D ext/pybind11/.travis.yml
M ext/pybind11/CMakeLists.txt
D ext/pybind11/CONTRIBUTING.md
D ext/pybind11/ISSUE_TEMPLATE.md
M ext/pybind11/LICENSE
M ext/pybind11/MANIFEST.in
D ext/pybind11/README.md
A ext/pybind11/README.rst
M ext/pybind11/docs/Doxyfile
M ext/pybind11/docs/advanced/cast/custom.rst
M ext/pybind11/docs/advanced/cast/eigen.rst
M ext/pybind11/docs/advanced/cast/index.rst
M ext/pybind11/docs/advanced/cast/stl.rst
M ext/pybind11/docs/advanced/classes.rst
M ext/pybind11/docs/advanced/embedding.rst
M ext/pybind11/docs/advanced/exceptions.rst
M ext/pybind11/docs/advanced/functions.rst
M ext/pybind11/docs/advanced/misc.rst
M ext/pybind11/docs/advanced/pycpp/numpy.rst
M ext/pybind11/docs/advanced/pycpp/object.rst
M ext/pybind11/docs/advanced/pycpp/utilities.rst
M ext/pybind11/docs/basics.rst
M ext/pybind11/docs/benchmark.py
M ext/pybind11/docs/benchmark.rst
M ext/pybind11/docs/changelog.rst
M ext/pybind11/docs/classes.rst
A ext/pybind11/docs/cmake/index.rst
M ext/pybind11/docs/compiling.rst
M ext/pybind11/docs/conf.py
M ext/pybind11/docs/faq.rst
M ext/pybind11/docs/index.rst
A ext/pybind11/docs/installing.rst
D ext/pybind11/docs/intro.rst
M ext/pybind11/docs/limitations.rst
M ext/pybind11/docs/reference.rst
M ext/pybind11/docs/release.rst
M ext/pybind11/docs/requirements.txt
M ext/pybind11/docs/upgrade.rst
M ext/pybind11/include/pybind11/attr.h
M ext/pybind11/include/pybind11/buffer_info.h
M ext/pybind11/include/pybind11/cast.h
M ext/pybind11/include/pybind11/chrono.h
M ext/pybind11/include/pybind11/complex.h
M ext/pybind11/include/pybind11/detail/class.h
M ext/pybind11/include/pybind11/detail/common.h
M ext/pybind11/include/pybind11/detail/descr.h
M ext/pybind11/include/pybind11/detail/init.h
M ext/pybind11/include/pybind11/detail/internals.h
M ext/pybind11/include/pybind11/detail/typeid.h
M ext/pybind11/include/pybind11/eigen.h
M ext/pybind11/include/pybind11/embed.h
M ext/pybind11/include/pybind11/eval.h
M ext/pybind11/include/pybind11/functional.h
M ext/pybind11/include/pybind11/iostream.h
M ext/pybind11/include/pybind11/numpy.h
M ext/pybind11/include/pybind11/operators.h
M ext/pybind11/include/pybind11/options.h
M ext/pybind11/include/pybind11/pybind11.h
M ext/pybind11/include/pybind11/pytypes.h
M ext/pybind11/include/pybind11/stl.h
M ext/pybind11/include/pybind11/stl_bind.h
M ext/pybind11/pybind11/__init__.py
M ext/pybind11/pybind11/__main__.py
M ext/pybind11/pybind11/_version.py
A ext/pybind11/pybind11/_version.pyi
A ext/pybind11/pybind11/commands.py
A ext/pybind11/pybind11/py.typed
A ext/pybind11/pybind11/setup_helpers.py
A ext/pybind11/pybind11/setup_helpers.pyi
A ext/pybind11/pyproject.toml
M ext/pybind11/setup.cfg
M ext/pybind11/setup.py
M ext/pybind11/tests/CMakeLists.txt
M ext/pybind11/tests/conftest.py
M ext/pybind11/tests/constructor_stats.h
A ext/pybind11/tests/env.py
A ext/pybind11/tests/extra_python_package/pytest.ini
A ext/pybind11/tests/extra_python_package/test_files.py
A ext/pybind11/tests/extra_setuptools/pytest.ini
A ext/pybind11/tests/extra_setuptools/test_setuphelper.py
M ext/pybind11/tests/local_bindings.h
M ext/pybind11/tests/pybind11_tests.cpp
M ext/pybind11/tests/pybind11_tests.h
M ext/pybind11/tests/pytest.ini
A ext/pybind11/tests/requirements.txt
M ext/pybind11/tests/test_async.cpp
M ext/pybind11/tests/test_async.py
M ext/pybind11/tests/test_buffers.cpp
M ext/pybind11/tests/test_buffers.py
M

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix style in arch/x86/types.hh.

2021-01-31 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40103 )


Change subject: arch-x86: Fix style in arch/x86/types.hh.
..

arch-x86: Fix style in arch/x86/types.hh.

Change-Id: I5e32eea9b843d4f68adf5430516d0636317c8a57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40103
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
---
M src/arch/x86/types.hh
1 file changed, 298 insertions(+), 295 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 890a9e5..9b0b034 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -48,336 +48,339 @@

 namespace X86ISA
 {
-//This really determines how many bytes are passed to the decoder.
-typedef uint64_t MachInst;

-enum Prefixes {
-NoOverride,
-ESOverride,
-CSOverride,
-SSOverride,
-DSOverride,
-FSOverride,
-GSOverride,
-RexPrefix,
-OperandSizeOverride,
-AddressSizeOverride,
-Lock,
-Rep,
-Repne,
-Vex2Prefix,
-Vex3Prefix,
-XopPrefix,
-};
+//This really determines how many bytes are passed to the decoder.
+typedef uint64_t MachInst;

-BitUnion8(LegacyPrefixVector)
-Bitfield<7, 4> decodeVal;
-Bitfield<7> repne;
-Bitfield<6> rep;
-Bitfield<5> lock;
-Bitfield<4> op;
-Bitfield<3> addr;
-//There can be only one segment override, so they share the
-//first 3 bits in the legacyPrefixes bitfield.
-Bitfield<2,0> seg;
-EndBitUnion(LegacyPrefixVector)
+enum Prefixes {
+NoOverride,
+ESOverride,
+CSOverride,
+SSOverride,
+DSOverride,
+FSOverride,
+GSOverride,
+RexPrefix,
+OperandSizeOverride,
+AddressSizeOverride,
+Lock,
+Rep,
+Repne,
+Vex2Prefix,
+Vex3Prefix,
+XopPrefix,
+};

-BitUnion8(ModRM)
-Bitfield<7,6> mod;
-Bitfield<5,3> reg;
-Bitfield<2,0> rm;
-EndBitUnion(ModRM)
+BitUnion8(LegacyPrefixVector)
+Bitfield<7, 4> decodeVal;
+Bitfield<7> repne;
+Bitfield<6> rep;
+Bitfield<5> lock;
+Bitfield<4> op;
+Bitfield<3> addr;
+//There can be only one segment override, so they share the
+//first 3 bits in the legacyPrefixes bitfield.
+Bitfield<2,0> seg;
+EndBitUnion(LegacyPrefixVector)

-BitUnion8(Sib)
-Bitfield<7,6> scale;
-Bitfield<5,3> index;
-Bitfield<2,0> base;
-EndBitUnion(Sib)
+BitUnion8(ModRM)
+Bitfield<7,6> mod;
+Bitfield<5,3> reg;
+Bitfield<2,0> rm;
+EndBitUnion(ModRM)

-BitUnion8(Rex)
-//This bit doesn't mean anything according to the ISA, but in
-//this implementation, it being set means an REX prefix was  
present.

-Bitfield<6> present;
-Bitfield<3> w;
-Bitfield<2> r;
-Bitfield<1> x;
-Bitfield<0> b;
-EndBitUnion(Rex)
+BitUnion8(Sib)
+Bitfield<7,6> scale;
+Bitfield<5,3> index;
+Bitfield<2,0> base;
+EndBitUnion(Sib)

-BitUnion8(Vex2Of3)
-// Inverted bits from the REX prefix.
-Bitfield<7> r;
-Bitfield<6> x;
-Bitfield<5> b;
-// Selector for what would be two or three byte opcode types.
-Bitfield<4, 0> m;
-EndBitUnion(Vex2Of3)
+BitUnion8(Rex)
+//This bit doesn't mean anything according to the ISA, but in
+//this implementation, it being set means an REX prefix was present.
+Bitfield<6> present;
+Bitfield<3> w;
+Bitfield<2> r;
+Bitfield<1> x;
+Bitfield<0> b;
+EndBitUnion(Rex)

-BitUnion8(Vex3Of3)
-// Bit from the REX prefix.
-Bitfield<7> w;
-// Inverted extra register index.
-Bitfield<6, 3>  v;
-// Vector length specifier.
-Bitfield<2> l;
-// Implied 66, F2, or F3 opcode prefix.
-Bitfield<1, 0> p;
-EndBitUnion(Vex3Of3)
+BitUnion8(Vex2Of3)
+// Inverted bits from the REX prefix.
+Bitfield<7> r;
+Bitfield<6> x;
+Bitfield<5> b;
+// Selector for what would be two or three byte opcode types.
+Bitfield<4, 0> m;
+EndBitUnion(Vex2Of3)

-BitUnion8(Vex2Of2)
-// Inverted bit from the REX prefix.
-Bitfield<7> r;
-// Inverted extra register index.
-Bitfield<6, 3>  v;
-// Vector length specifier
-Bitfield<2> l;
-// Implied 66, F2, or F3 opcode prefix.
-Bitfield<1, 0> p;
-EndBitUnion(Vex2Of2)
+BitUnion8(Vex3Of3)
+// Bit from the REX prefix.
+Bitfield<7> w;
+// Inverted extra register index.
+Bitfield<6, 3>  v;
+// Vector length specifier.
+Bitfield<2> l;
+// Implied 66, F2, or F3 opcode prefix.
+Bitfield<1, 0> p;
+EndBitUnion(Vex3Of3)

-

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Add missing include to hsa_driver.hh

2021-01-31 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40216 )


Change subject: dev-hsa: Add missing include to hsa_driver.hh
..

dev-hsa: Add missing include to hsa_driver.hh

Due to using ThreadContext::Suspended in hsa_driver.hh as of
965ad12b9a4ae4035b0f63e7ab083ac87258a071, we now need to include
cpu/thread_context.hh. This change fixes that.

Change-Id: I2c6882f2a29ca1638dd34cda42874b95cafbe548
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40216
Reviewed-by: Matt Sinclair 
Reviewed-by: Gabe Black 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/hsa/hsa_driver.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/hsa/hsa_driver.hh b/src/dev/hsa/hsa_driver.hh
index fc8131e..616ec94 100644
--- a/src/dev/hsa/hsa_driver.hh
+++ b/src/dev/hsa/hsa_driver.hh
@@ -54,12 +54,12 @@
 #include 

 #include "base/types.hh"
+#include "cpu/thread_context.hh"
 #include "sim/emul_driver.hh"

 struct HSADriverParams;
 class HSADevice;
 class PortProxy;
-class ThreadContext;

 class HSADriver : public EmulatedDriver
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2c6882f2a29ca1638dd34cda42874b95cafbe548
Gerrit-Change-Number: 40216
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Stop using switching header files in ISA specific files.

2021-01-31 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40104 )


Change subject: arch: Stop using switching header files in ISA specific  
files.

..

arch: Stop using switching header files in ISA specific files.

We know what ISA we want, we don't need to use the indirection.

Change-Id: I57eb2737bb4d9abb562b857ad2c3238c641199d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40104
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
---
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/mips/locked_mem.hh
M src/arch/null/registers.hh
M src/arch/power/decoder.hh
M src/arch/riscv/locked_mem.hh
M src/arch/sparc/decoder.hh
7 files changed, 7 insertions(+), 7 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/tme64ruby.cc  
b/src/arch/arm/insts/tme64ruby.cc

index f8d9481..5e22deb 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -38,9 +38,9 @@
 #include "arch/arm/faults.hh"
 #include "arch/arm/htm.hh"
 #include "arch/arm/insts/tme64.hh"
+#include "arch/arm/locked_mem.hh"
 #include "arch/arm/registers.hh"
 #include "arch/generic/memhelpers.hh"
-#include "arch/locked_mem.hh"
 #include "debug/ArmTme.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index f674c7e..e827c22 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -44,7 +44,7 @@
 #include 

 #include "arch/arm/interrupts.hh"
-#include "arch/registers.hh"
+#include "arch/arm/registers.hh"
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
 #include "debug/KvmContext.hh"
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 153a991..73180af 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -47,7 +47,7 @@
  * ISA-specific helper functions for locked memory accesses.
  */

-#include "arch/registers.hh"
+#include "arch/mips/registers.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index db02afc..3e96472 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -40,7 +40,7 @@

 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/types.hh"
+#include "arch/null/types.hh"
 #include "base/types.hh"

 namespace NullISA {
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index 2951e4d..c76ffd9 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -31,7 +31,7 @@

 #include "arch/generic/decode_cache.hh"
 #include "arch/generic/decoder.hh"
-#include "arch/types.hh"
+#include "arch/power/types.hh"
 #include "cpu/static_inst.hh"

 namespace PowerISA
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index 10d1839..3a95780 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -49,7 +49,7 @@
 #include 
 #include 

-#include "arch/registers.hh"
+#include "arch/riscv/registers.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 5b30a82..e8267fe 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -32,7 +32,7 @@
 #include "arch/generic/decode_cache.hh"
 #include "arch/generic/decoder.hh"
 #include "arch/sparc/registers.hh"
-#include "arch/types.hh"
+#include "arch/sparc/types.hh"
 #include "cpu/static_inst.hh"

 namespace SparcISA

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I57eb2737bb4d9abb562b857ad2c3238c641199d2
Gerrit-Change-Number: 40104
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch: Correct style in the ISA base class.

2021-01-31 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40105 )


Change subject: arch: Correct style in the ISA base class.
..

arch: Correct style in the ISA base class.

Change-Id: I1732f519bf3eab1dff8b9a9a30fc8e5e132d067d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40105
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
---
M src/arch/generic/isa.hh
1 file changed, 1 insertion(+), 4 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index df07763..c1b8734 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -52,10 +52,7 @@
 ThreadContext *tc = nullptr;

   public:
-virtual void
-takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
-{}
-
+virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext  
*old_tc) {}

 virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
 };


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1732f519bf3eab1dff8b9a9a30fc8e5e132d067d
Gerrit-Change-Number: 40105
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: Nightly #205

2021-01-31 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[kyleroarty1716] dev-hsa: enable interruptible hsa signal support


--
[...truncated 44.38 KB...]
 [ CXX] GCN3_X86/mem/cache/prefetch/slim_ampm.cc -> .o
 [SO PARAM] STeMSPrefetcher -> GCN3_X86/params/STeMSPrefetcher.hh
 [ CXX] GCN3_X86/mem/cache/prefetch/spatio_temporal_memory_streaming.cc -> 
.o
 [SO PARAM] StridePrefetcher -> GCN3_X86/params/StridePrefetcher.hh
 [SO PARAM] StridePrefetcherHashedSetAssociative -> 
GCN3_X86/params/StridePrefetcherHashedSetAssociative.hh
 [SO PARAM] SetAssociative -> GCN3_X86/params/SetAssociative.hh
 [ CXX] GCN3_X86/mem/cache/prefetch/stride.cc -> .o
 [SO PARAM] TaggedPrefetcher -> GCN3_X86/params/TaggedPrefetcher.hh
 [ CXX] GCN3_X86/mem/cache/prefetch/tagged.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/TraceCPUData.hh
 [ TRACING]  -> GCN3_X86/debug/TraceCPUInst.hh
 [SO PARAM] TraceCPU -> GCN3_X86/params/TraceCPU.hh
 [  PROTOC] GCN3_X86/proto/inst_dep_record.proto -> 
GCN3_X86/proto/inst_dep_record.pb.cc, GCN3_X86/proto/inst_dep_record.pb.h
 [  PROTOC] GCN3_X86/proto/packet.proto -> GCN3_X86/proto/packet.pb.cc, 
GCN3_X86/proto/packet.pb.h
 [ CXX] GCN3_X86/cpu/trace/trace_cpu.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/RubyQueue.hh
 [SO PARAM] RubyNetwork -> GCN3_X86/params/RubyNetwork.hh
 [MAKE INC] GCN3_X86/mem/ruby/common/DataBlock.hh -> protocol/DataBlock.hh
 [MAKE INC] GCN3_X86/mem/ruby/common/MachineID.hh -> protocol/MachineID.hh
 [MAKE INC] GCN3_X86/mem/ruby/slicc_interface/Message.hh -> protocol/Message.hh
 [SO PARAM] RubyController -> GCN3_X86/params/RubyController.hh
 [SO PARAM] RubySystem -> GCN3_X86/params/RubySystem.hh
 [SO PARAM] RubySequencer -> GCN3_X86/params/RubySequencer.hh
 [ TRACING]  -> GCN3_X86/debug/RubySlicc.hh
 [SO PARAM] MessageBuffer -> GCN3_X86/params/MessageBuffer.hh
 [MAKE INC] GCN3_X86/mem/ruby/slicc_interface/RubyRequest.hh -> 
protocol/RubyRequest.hh
 [SO PARAM] RubyCache -> GCN3_X86/params/RubyCache.hh
 [SO PARAM] RubyPort -> GCN3_X86/params/RubyPort.hh
 [SO PARAM] BasicExtLink -> GCN3_X86/params/BasicExtLink.hh
 [SO PARAM] BasicIntLink -> GCN3_X86/params/BasicIntLink.hh
 [SO PARAM] BasicLink -> GCN3_X86/params/BasicLink.hh
 [SO PARAM] BasicRouter -> GCN3_X86/params/BasicRouter.hh
 [SO PARAM] RubyDirectoryMemory -> GCN3_X86/params/RubyDirectoryMemory.hh
 [SO PARAM] SimpleMemory -> GCN3_X86/params/SimpleMemory.hh
 [ENUMDECL] MessageRandomization -> GCN3_X86/enums/MessageRandomization.hh
 [ CXX] GCN3_X86/mem/ruby/slicc_interface/AbstractController.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/RubyCache.hh
 [ CXX] GCN3_X86/mem/ruby/slicc_interface/AbstractCacheEntry.cc -> .o
 [LINK]  -> GCN3_X86/mem/cache/prefetch/lib.o.partial
 [ CXX] GCN3_X86/mem/ruby/slicc_interface/RubyRequest.cc -> .o
 [ CXX] GCN3_X86/unittest/unittest.cc -> .o
 [ CXX] GCN3_X86/mem/ruby/network/BasicLink.cc -> .o
 [LINK]  -> GCN3_X86/unittest/lib.o.partial
 [ CXX] GCN3_X86/mem/ruby/network/BasicRouter.cc -> .o
 [ CXX] GCN3_X86/mem/ruby/network/MessageBuffer.cc -> .o
 [ CXX] GCN3_X86/mem/ruby/network/Network.cc -> .o
 [LINK]  -> GCN3_X86/cpu/trace/lib.o.partial
 [ TRACING]  -> GCN3_X86/debug/RubyNetwork.hh
 [ CXX] GCN3_X86/mem/ruby/network/Topology.cc -> .o
 [LINK]  -> GCN3_X86/mem/ruby/slicc_interface/lib.o.partial
 [ CXX] GCN3_X86/systemc/tlm_core/2/generic_payload/gp.cc -> .o
 [ CXX] GCN3_X86/systemc/tlm_core/2/generic_payload/phase.cc -> .o
 [LINK]  -> GCN3_X86/systemc/tlm_core/2/generic_payload/lib.o.partial
 [ TRACING]  -> GCN3_X86/debug/RubyStats.hh
 [ CXX] GCN3_X86/mem/ruby/structures/DirectoryMemory.cc -> .o
 [ TRACING]  -> GCN3_X86/debug/HtmMem.hh
 [ TRACING]  -> GCN3_X86/debug/RubyCacheTrace.hh
 [ TRACING]  -> GCN3_X86/debug/RubyResourceStalls.hh
 [ CXX] GCN3_X86/mem/ruby/structures/CacheMemory.cc -> .o
 [SO PARAM] RubyWireBuffer -> GCN3_X86/params/RubyWireBuffer.hh
 [ CXX] GCN3_X86/mem/ruby/structures/WireBuffer.cc -> .o
 [ CXX] GCN3_X86/mem/ruby/structures/PersistentTable.cc -> .o
 [LINK]  -> GCN3_X86/mem/ruby/network/lib.o.partial
 [ TRACING]  -> GCN3_X86/debug/RubyPrefetcher.hh
 [SO PARAM] RubyPrefetcher -> GCN3_X86/params/RubyPrefetcher.hh
 [ CXX] GCN3_X86/mem/ruby/structures/RubyPrefetcher.cc -> .o
 [ CXX] GCN3_X86/mem/ruby/structures/TimerTable.cc -> .o
 [ CXX] GCN3_X86/mem/ruby/structures/BankedArray.cc -> .o
 [ CXX] GCN3_X86/cpu/testers/gpu_ruby_test/address_manager.cc -> .o
 [SO PARAM] ProtocolTester -> GCN3_X86/params/ProtocolTester.hh
 [ TRACING]  -> GCN3_X86/debug/GPUMem.hh
 [ENUMDECL] StorageClassType -> GCN3_X86/enums/StorageClassType.hh
 [ CFG ISA]  -> GCN3_X86/config/the_gpu_isa.hh
 [ENUMDECL] PrefetchType -> GCN3_X86/enums/PrefetchType.hh
 [GENERATE] gcn3 -> GCN3_X86/arch/gpu_isa.hh
 [SO PARAM] ComputeUnit -> GCN3_X86/params/ComputeUnit.hh
 [GENERATE] gcn3 -> GCN3_X86/arch/gpu_decoder.hh
 [SO PARAM] PoolManager ->

[gem5-dev] Jenkins build is back to normal : Nightly #204

2021-01-31 Thread jenkins-no-reply--- via gem5-dev 
See 
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