date:20210322

[gem5-dev] Re: de-templating the O3 CPU

2021-03-22 Thread Gabe Black via gem5-dev

Thanks, Giacomo. Also thank you for making a clear effort to get some of my
other patches reviewed in the last few weeks. It's noticed and appreciated!
:-)

Gabe

On Mon, Mar 22, 2021 at 8:02 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Gabe,
>
> That's probably because making a release has caught everyone's attention.
> I am definitely gonna have a look at it in about a week time, I promise 😊
>
> Kind Regards
>
> Giacomo
>
>
> > -Original Message-
> > From: Gabe Black 
> > Sent: 22 March 2021 03:20
> > To: Jason Lowe-Power 
> > Cc: gem5 Developer List ; Giacomo Travaglini
> > 
> > Subject: Re: [gem5-dev] Re: de-templating the O3 CPU
> >
> > People seemed pretty enthusiastic for this series of CLs, but I haven't
> been
> > able to get reviews for it...
> >
> > https://gem5-review.googlesource.com/c/public/gem5/+/42094
> >
> >
> > On Wed, Mar 3, 2021 at 9:15 AM Gabe Black  >  > wrote:
> >
> >
> > Series of 28 CLs, ends here:
> >
> >
> >
> > https://gem5-review.googlesource.com/c/public/gem5/+/42120
> >
> >
> > On Mon, Mar 1, 2021 at 8:50 AM Jason Lowe-Power
> > mailto:ja...@lowepower.com> > wrote:
> >
> >
> > Hey Gabe,
> >
> > I love this idea! It would be nice if you could document the
> > code as you go, too. It could serve as a good learning tool in the
> future.
> >
> > Cheers,
> > Jason
> >
> >
> > On Mon, Mar 1, 2021 at 7:56 AM Giacomo Travaglini via gem5-
> > dev mailto:gem5-dev@gem5.org> > wrote:
> >
> >
> > +2, +1, Merged
> >
> > 😊
> >
> > Giacomo
> >
> > > -Original Message-
> > > From: Gabe Black via gem5-dev  > d...@gem5.org  >
> > > Sent: 27 February 2021 10:13
> > > To: gem5 Developer List  >  >
> > > Cc: Gabe Black  >  >
> > > Subject: [gem5-dev] de-templating the O3 CPU
> > >
> > > Hi folks. The O3 CPU uses templates pretty heavily,
> > I think nominally to make it
> > > possible to switch in different parts of the CPU to
> > change how, for example, a
> > > pipeline stage is implemented.
> > >
> > > Realistically, the different parts of the CPU are
> > probably too interdependent
> > > for that to actually work, and all the templates and
> > indirection make the code a
> > > lot more complicated than it really needs to be.
> > >
> > > Also, there is a pseudo-generic dynamic instruction
> > base class in
> > > cpu/base_dyn_inst.hh which could, again
> > theoretically, be used as a base class
> > > for other CPUs to reuse. Unfortunately that too is
> > probably too tied to its only
> > > consumer, the O3 CPU, to be realistically reusable.
> > >
> > > I would like to merge the base dynamic instruction
> > class into the O3 version,
> > > and then de-templatize the whole O3 CPU. I think
> > that will make the code a lot
> > > easier to work on, and I think our ability to maintain
> > and update O3 is
> > > something we need to improve in at least the
> > medium term.
> > >
> > > Any thoughts? Objections? Votes of support?
> > >
> > > Gabe
> > IMPORTANT NOTICE: The contents of this email and
> > any attachments are confidential and may also be privileged. If you are
> not
> > the intended recipient, please notify the sender immediately and do not
> > disclose the contents to any other person, use it for any purpose, or
> store or
> > copy the information in any medium. Thank you.
> >
> > ___
> > gem5-dev mailing list -- gem5-dev@gem5.org
> > 
> > To unsubscribe send an email to gem5-dev-
> > le...@gem5.org 
> >
> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
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>
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,kern,sim: Eliminate the utility.hh switching header.

2021-03-22 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39337 )


Change subject: arch,cpu,kern,sim: Eliminate the utility.hh switching  
header.

..

arch,cpu,kern,sim: Eliminate the utility.hh switching header.

This header is no longer used. Remove the places where it's included,
and stop generating it. Also eliminate the now empty SPARC and Power
versions of the header.

Change-Id: I6ee66d39bc0218d1d9b9b7db3b350134ef03251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39337
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/arch/SConscript
M src/arch/power/isa/includes.isa
M src/arch/power/pagetable.hh
M src/arch/power/tlb.cc
M src/arch/power/tlb.hh
D src/arch/power/utility.hh
M src/arch/sparc/linux/linux.hh
D src/arch/sparc/utility.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/exetrace.cc
M src/cpu/kvm/base.cc
M src/cpu/minor/cpu.cc
M src/cpu/minor/fetch2.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/simple/atomic.cc
M src/cpu/simple/timing.cc
M src/cpu/simple_thread.cc
M src/kern/freebsd/events.cc
M src/kern/linux/events.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
M src/sim/system.cc
26 files changed, 0 insertions(+), 91 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/SConscript b/src/arch/SConscript
index a4825e5..226b50d 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -64,7 +64,6 @@
 registers.hh
 remote_gdb.hh
 types.hh
-utility.hh
 '''),
 env.subst('${TARGET_ISA}'))

diff --git a/src/arch/power/isa/includes.isa  
b/src/arch/power/isa/includes.isa

index c219d97..55b51cf 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -56,7 +56,6 @@
 #include "arch/power/decoder.hh"
 #include "arch/power/faults.hh"
 #include "arch/power/isa_traits.hh"
-#include "arch/power/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/cprintf.hh"
 #include "cpu/thread_context.hh"
@@ -71,7 +70,6 @@
 #include "arch/power/faults.hh"
 #include "arch/power/isa_traits.hh"
 #include "arch/power/miscregs.hh"
-#include "arch/power/utility.hh"
 #include "base/condcodes.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index 1f0ec4c..f193987 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -33,7 +33,6 @@
 #define __ARCH_POWER_PAGETABLE_H__

 #include "arch/power/isa_traits.hh"
-#include "arch/power/utility.hh"
 #include "sim/serialize.hh"

 namespace PowerISA
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index dca8d7b..410b12c 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -36,7 +36,6 @@

 #include "arch/power/faults.hh"
 #include "arch/power/pagetable.hh"
-#include "arch/power/utility.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index a9653e6..7dcc3c0 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -37,7 +37,6 @@
 #include "arch/generic/tlb.hh"
 #include "arch/power/isa_traits.hh"
 #include "arch/power/pagetable.hh"
-#include "arch/power/utility.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/PowerTLB.hh"
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
deleted file mode 100644
index dfe3d06..000
--- a/src/arch/power/utility.hh
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CO

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.

2021-03-22 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39336 )


Change subject: arch,cpu: Move TheISA::copyRegs to  
TheISA::ISA::copyRegsFrom.

..

arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.

This eliminates the last externally used function in arch/utility.hh.

Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39336
Maintainer: Gabe Black 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/linux/linux.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/utility.cc
M src/arch/power/SConscript
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/pagetable.hh
D src/arch/power/utility.cc
M src/arch/power/utility.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/linux/linux.hh
M src/arch/riscv/utility.hh
M src/arch/sparc/SConscript
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/linux/linux.hh
D src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/x86/isa.cc
M src/arch/x86/isa.hh
M src/arch/x86/linux/linux.hh
M src/arch/x86/utility.cc
M src/arch/x86/utility.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
32 files changed, 331 insertions(+), 423 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 2f674cd..b1d8d3f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -487,6 +487,49 @@
 setupThreadContext();
 }

+static void
+copyVecRegs(ThreadContext *src, ThreadContext *dest)
+{
+auto src_mode = src->getIsaPtr()->vecRegRenameMode(src);
+
+// The way vector registers are copied (VecReg vs VecElem) is relevant
+// in the O3 model only.
+if (src_mode == Enums::Full) {
+for (auto idx = 0; idx < NumVecRegs; idx++)
+dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
+} else {
+for (auto idx = 0; idx < NumVecRegs; idx++)
+for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg;  
elem_idx++)

+dest->setVecElemFlat(
+idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
+}
+}
+
+void
+ISA::copyRegsFrom(ThreadContext *src)
+{
+for (int i = 0; i < NUM_INTREGS; i++)
+tc->setIntRegFlat(i, src->readIntRegFlat(i));
+
+for (int i = 0; i < NUM_CCREGS; i++)
+tc->setCCReg(i, src->readCCReg(i));
+
+for (int i = 0; i < NUM_MISCREGS; i++)
+tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+
+copyVecRegs(src, tc);
+
+// setMiscReg "with effect" will set the misc register mapping  
correctly.

+// e.g. updateRegMap(val)
+tc->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
+
+// Copy over the PC State
+tc->pcState(src->pcState());
+
+// Invalidate the tlb misc register cache
+static_cast(tc->getMMUPtr())->invalidateMiscReg();
+}
+
 RegVal
 ISA::readMiscRegNoEffect(int misc_reg) const
 {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 9bfcf84..646fc25 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -905,6 +905,8 @@
 CPSR cpsr = miscRegs[MISCREG_CPSR];
 return ArmISA::inUserMode(cpsr);
 }
+
+void copyRegsFrom(ThreadContext *src) override;
 };
 }

diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index ce73c39..2eb47a0 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -57,7 +57,7 @@
   ThreadContext *ptc, ThreadContext *ctc,
   uint64_t stack, uint64_t tls)
 {
-ArmISA::copyRegs(ptc, ctc);
+ctc->getIsaPtr()->copyRegsFrom(ptc);

 if (flags & TGT_CLONE_SETTLS) {
 /* TPIDR_EL0 is architecturally mapped to TPIDRURW, so
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index f5c792f..6f63bf2 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -55,49 +55,6 @@
 namespace ArmISA
 {

-static void
-copyVecRegs(ThreadContext *src, ThreadContext *dest)
-{
-auto src_mode = src->getIsaPtr()->vecRegRenameMode(src);
-
-// The way vector registers are copied (VecReg vs VecElem) is relevant
-// in the O3 model only.
-if (src_mode == Enums::Full) {
-for (auto idx = 0; idx < NumVecRegs; idx++)
-dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
-} else {
-for (auto idx = 0; idx < NumVecRegs; idx++)
-for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg;  
elem_idx++)

-dest->setVecElemFlat(
-idx, elem_idx, src->readVecEle

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Collapse away TheISA::advancePC.

2021-03-22 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39335 )


Change subject: arch,cpu: Collapse away TheISA::advancePC.
..

arch,cpu: Collapse away TheISA::advancePC.

In most ISAs except MIPS and Power, this was implemented as
inst->advancePC(). It works just fine to call this function all the
time, but the idea had originally been that for ISAs which could simply
advance the PC using the PC itself, they could save the virtual function
call. Since the only ISAs which could skip the call were MIPS and Power,
and neither is at the point where that level of performance tuning
matters, this function can be collapsed with little downside.

If this turns out to be a performance bottleneck in the future, the way
the PC is managed could be revisited to see if we can factor out this
trip to the instruction object in the first place.

Change-Id: I533d1ad316e5c936466c529b7f1238a9ab87bd1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39335
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Alex Dutu 
---
M src/arch/arm/utility.hh
M src/arch/mips/utility.hh
M src/arch/power/utility.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/utility.hh
M src/arch/sparc/utility.hh
M src/arch/x86/utility.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/fetch2.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/simple/base.cc
16 files changed, 13 insertions(+), 54 deletions(-)

Approvals:
  Alex Dutu: Looks good to me, but someone else must approve
  Giacomo Travaglini: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 5b3b849..3c8acb2 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -375,12 +375,6 @@

 bool SPAlignmentCheckEnabled(ThreadContext* tc);

-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
-inst->advancePC(pc);
-}
-
 Addr truncPage(Addr addr);
 Addr roundPage(Addr addr);

diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 1804680..f86e93a 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -72,14 +72,6 @@
 return (addr + PageBytes - 1) & ~(PageBytes - 1);
 }

-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
-pc.advance();
-}
-
 };


diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 03df7fb..13183f1 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -39,12 +39,6 @@

 void copyRegs(ThreadContext *src, ThreadContext *dest);

-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
-pc.advance();
-}
-
 } // namespace PowerISA


diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 8c273f2..4b25810 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -141,7 +141,7 @@
 pcState.set(addr);
 } else {
 invokeSE(tc, inst);
-advancePC(pcState, inst);
+inst->advancePC(pcState);
 }
 tc->pcState(pcState);
 }
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 3bbbd71..f033b2b 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -142,12 +142,6 @@
 }
 }

-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
-inst->advancePC(pc);
-}
-
 } // namespace RiscvISA

 #endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index f179c17..87626b7 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -43,12 +43,6 @@

 void copyRegs(ThreadContext *src, ThreadContext *dest);

-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
-inst->advancePC(pc);
-}
-
 } // namespace SparcISA

 #endif
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 9cd4e94..a572637 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -46,12 +46,6 @@
 {
 void copyRegs(ThreadContext *src, ThreadContext *dest);

-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
-inst->advancePC(pc);
-}
-
 /**
  * Reconstruct the rflags register from the internal gem5 register
  * state.
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index a5a842a..87049f0 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -590,7 +590,7 @@
 mispredicted()
 {
 TheISA::PCState tempPC = pc;
-TheISA::advancePC(tempPC, staticInst);
+staticInst->advancePC(tempPC);
 return !(tempPC == predPC);
 }

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 7dc62e0..66d1859 100644
--- a

[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: tests: Remove references to resolved Jira Issues in asmtests

2021-03-22 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/43445 )



Change subject: tests: Remove references to resolved Jira Issues in asmtests
..

tests: Remove references to resolved Jira Issues in asmtests

A comment in tests/gem5/asmtest/tests.py refers to failing tests due
to issues outlined in https://gem5.atlassian.net/browse/GEM5-494 and
https://gem5.atlassian.net/browse/GEM5-497. Though, theses tests now
pass, and these issues have been resolved. This patch updates this
comment to no longer refer to these Jira issues.

Change-Id: Ic1b477e1570765f33a41c5e852bf80a09c172545
---
M tests/gem5/asmtest/tests.py
1 file changed, 1 insertion(+), 4 deletions(-)



diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index f267b91..6f2c711 100755
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -90,11 +90,8 @@
 cpu_types =  
('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU')


 # The following lists the RISCV binaries. Those commented out presently  
result

-# in a test failure. They are outlined in the following Jira Issues:
-#
-# https://gem5.atlassian.net/browse/GEM5-494
+# in a test failure. This is outlined in the following Jira issue:
 # https://gem5.atlassian.net/browse/GEM5-496
-# https://gem5.atlassian.net/browse/GEM5-497
 binaries = (
 'rv64samt-ps-sysclone_d',
 'rv64samt-ps-sysfutex1_d',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: Ic1b477e1570765f33a41c5e852bf80a09c172545
Gerrit-Change-Number: 43445
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: scons: Remove -Werror for the gem5 21.0 release

2021-03-22 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/43425 )



Change subject: scons: Remove -Werror for the gem5 21.0 release
..

scons: Remove -Werror for the gem5 21.0 release

While gem5 compiles on all our supported compilers, removing the -Werror
flag on the stable branch ensures that, as new compilers are released
with stricter warnings, gem5 remains compilable.

Change-Id: Ic7bb17e770684211330c09143bd8a26720becb9a
---
M SConstruct
1 file changed, 0 insertions(+), 6 deletions(-)



diff --git a/SConstruct b/SConstruct
index fb3421c..bcfd58f 100755
--- a/SConstruct
+++ b/SConstruct
@@ -322,12 +322,6 @@
 if GetOption('gold_linker'):
 main.Append(LINKFLAGS='-fuse-ld=gold')

-# Treat warnings as errors but white list some warnings that we
-# want to allow (e.g., deprecation warnings).
-main.Append(CCFLAGS=['-Werror',
- '-Wno-error=deprecated-declarations',
- '-Wno-error=deprecated',
-])
 else:
 error('\n'.join((
   "Don't know what compiler options to use for your compiler.",

--
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Gerrit-Change-Id: Ic7bb17e770684211330c09143bd8a26720becb9a
Gerrit-Change-Number: 43425
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Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: misc: Update version number to v21.0.0.0

2021-03-22 Thread Bobby R. Bruce (Gerrit) via gem5-dev

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/43405 )



Change subject: misc: Update version number to v21.0.0.0
..

misc: Update version number to v21.0.0.0

Change-Id: Ica7f7bfdcb1655e38defdf0b32a630e90adb7ce8
---
M src/Doxyfile
M src/base/version.cc
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/Doxyfile b/src/Doxyfile
index d453314..b83a8b1 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,7 +31,7 @@
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.

-PROJECT_NUMBER = DEVELOP-FOR-V20.2
+PROJECT_NUMBER = v21.0.0.0

 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.
diff --git a/src/base/version.cc b/src/base/version.cc
index cfa98f9..b46ca39 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -29,4 +29,4 @@
 /**
  * @ingroup api_base_utils
  */
-const char *gem5Version = "[DEVELOP-FOR-V20.2]";
+const char *gem5Version = "21.0.0.0";

--
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Gerrit-Change-Number: 43405
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Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Re: de-templating the O3 CPU

2021-03-22 Thread Giacomo Travaglini via gem5-dev

Hi Gabe,

That's probably because making a release has caught everyone's attention.
I am definitely gonna have a look at it in about a week time, I promise 😊

Kind Regards

Giacomo


> -Original Message-
> From: Gabe Black 
> Sent: 22 March 2021 03:20
> To: Jason Lowe-Power 
> Cc: gem5 Developer List ; Giacomo Travaglini
> 
> Subject: Re: [gem5-dev] Re: de-templating the O3 CPU
>
> People seemed pretty enthusiastic for this series of CLs, but I haven't been
> able to get reviews for it...
>
> https://gem5-review.googlesource.com/c/public/gem5/+/42094
>
>
> On Wed, Mar 3, 2021 at 9:15 AM Gabe Black   > wrote:
>
>
> Series of 28 CLs, ends here:
>
>
>
> https://gem5-review.googlesource.com/c/public/gem5/+/42120
>
>
> On Mon, Mar 1, 2021 at 8:50 AM Jason Lowe-Power
> mailto:ja...@lowepower.com> > wrote:
>
>
> Hey Gabe,
>
> I love this idea! It would be nice if you could document the
> code as you go, too. It could serve as a good learning tool in the future.
>
> Cheers,
> Jason
>
>
> On Mon, Mar 1, 2021 at 7:56 AM Giacomo Travaglini via gem5-
> dev mailto:gem5-dev@gem5.org> > wrote:
>
>
> +2, +1, Merged
>
> 😊
>
> Giacomo
>
> > -Original Message-
> > From: Gabe Black via gem5-dev  d...@gem5.org  >
> > Sent: 27 February 2021 10:13
> > To: gem5 Developer List   >
> > Cc: Gabe Black   >
> > Subject: [gem5-dev] de-templating the O3 CPU
> >
> > Hi folks. The O3 CPU uses templates pretty heavily,
> I think nominally to make it
> > possible to switch in different parts of the CPU to
> change how, for example, a
> > pipeline stage is implemented.
> >
> > Realistically, the different parts of the CPU are
> probably too interdependent
> > for that to actually work, and all the templates and
> indirection make the code a
> > lot more complicated than it really needs to be.
> >
> > Also, there is a pseudo-generic dynamic instruction
> base class in
> > cpu/base_dyn_inst.hh which could, again
> theoretically, be used as a base class
> > for other CPUs to reuse. Unfortunately that too is
> probably too tied to its only
> > consumer, the O3 CPU, to be realistically reusable.
> >
> > I would like to merge the base dynamic instruction
> class into the O3 version,
> > and then de-templatize the whole O3 CPU. I think
> that will make the code a lot
> > easier to work on, and I think our ability to maintain
> and update O3 is
> > something we need to improve in at least the
> medium term.
> >
> > Any thoughts? Objections? Votes of support?
> >
> > Gabe
> IMPORTANT NOTICE: The contents of this email and
> any attachments are confidential and may also be privileged. If you are not
> the intended recipient, please notify the sender immediately and do not
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>
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[gem5-dev] Change in gem5/gem5[develop]: dev,cpu,configs: Get rid of the IntrControl device.

2021-03-22 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/43347 )



Change subject: dev,cpu,configs: Get rid of the IntrControl device.
..

dev,cpu,configs: Get rid of the IntrControl device.

This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
---
M configs/common/FSConfig.py
M configs/example/arm/devices.py
M configs/example/riscv/fs_linux.py
D src/cpu/IntrControl.py
M src/cpu/SConscript
D src/cpu/intr_control.cc
D src/cpu/intr_control.hh
D src/cpu/intr_control_noisa.cc
M src/dev/Platform.py
M src/dev/arm/RealView.py
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
M src/dev/arm/gic_v2m.hh
M src/dev/arm/gic_v3.cc
M src/dev/arm/realview.cc
M src/dev/arm/realview.hh
M src/dev/arm/vgic.cc
M src/dev/arm/vgic.hh
M src/dev/mips/Malta.py
M src/dev/mips/malta.cc
M src/dev/mips/malta.hh
M src/dev/mips/malta_cchip.cc
M src/dev/platform.cc
M src/dev/platform.hh
M src/dev/riscv/Clint.py
M src/dev/riscv/HiFive.py
M src/dev/riscv/Plic.py
M src/dev/riscv/clint.cc
M src/dev/riscv/clint.hh
M src/dev/riscv/hifive.cc
M src/dev/riscv/hifive.hh
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
M src/dev/sparc/T1000.py
M src/dev/sparc/iob.cc
M src/dev/sparc/iob.hh
M src/dev/sparc/t1000.cc
M src/dev/storage/ide_ctrl.cc
M src/dev/x86/pc.cc
M src/dev/x86/pc.hh
40 files changed, 88 insertions(+), 356 deletions(-)



diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6665225..22b1ee1 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -122,7 +122,6 @@
AddrRange(Addr('2GB'), size ='256MB')]
 self.bridge.master = self.iobus.slave
 self.bridge.slave = self.membus.master
-self.intrctrl = IntrControl()
 self.disk0 = CowMmDisk()
 self.disk0.childImage(mdesc.disks()[0])
 self.disk0.pio = self.iobus.master
@@ -332,7 +331,6 @@
 dev, self.iobus,
 dma_ports=self._dma_ports if ruby else None)

-self.intrctrl = IntrControl()
 self.terminal = Terminal()
 self.vncserver = VncServer()

@@ -379,7 +377,6 @@
 self.malta.ethernet.dma = self.iobus.slave
 self.simple_disk = SimpleDisk(disk=RawDiskImage(
 image_file = mdesc.disks()[0], read_only = True))
-self.intrctrl = IntrControl()
 self.mem_mode = mem_mode
 self.terminal = Terminal()
 self.console = binary('mips/console')
@@ -488,8 +485,6 @@
 else:
 connectX86ClassicSystem(self, numCPUs)

-self.intrctrl = IntrControl()
-
 # Disks
 disks = makeCowDisks(mdesc.disks())
 self.pc.south_bridge.ide.disks = disks
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 26f7aa4..5ac783d 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -298,7 +298,6 @@

 self.membus = MemBus()

-self.intrctrl = IntrControl()
 self.terminal = Terminal()
 self.vncserver = VncServer()

diff --git a/configs/example/riscv/fs_linux.py  
b/configs/example/riscv/fs_linux.py

index 3d40061..da4fe41 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -99,8 +99,6 @@

 system.system_port = system.membus.slave

-system.intrctrl = IntrControl()
-
 # HiFive platform
 system.platform = HiFive()

diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py
deleted file mode 100644
index d38f8d1..000
--- a/src/cpu/IntrControl.py
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCU

[gem5-dev] Re: de-templating the O3 CPU

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu,kern,sim: Eliminate the utility.hh switching header.

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.

[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Collapse away TheISA::advancePC.

[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: tests: Remove references to resolved Jira Issues in asmtests

[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: scons: Remove -Werror for the gem5 21.0 release

[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: misc: Update version number to v21.0.0.0

[gem5-dev] Re: de-templating the O3 CPU

[gem5-dev] Change in gem5/gem5[develop]: dev,cpu,configs: Get rid of the IntrControl device.

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