[gem5-dev] Change in gem5/gem5[develop]: scons: Rerun configuration tests with "config=force"
Hanhwi Jang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44265 )
Change subject: scons: Rerun configuration tests with "config=force"
..
scons: Rerun configuration tests with "config=force"
Scons uses cached results for configuration tests, which leads to
compilation issues by the stale result use.
This patch allows users to rerun configuration tests using the
"config=force" option without deleting cache manually.
Change-Id: I61244c1daf963272a4b5a3d0e72101afefa82491
---
M SConstruct
M ext/systemc/SConscript
M src/base/SConsopts
M src/base/stats/SConsopts
M src/cpu/kvm/SConsopts
M src/dev/net/SConsopts
M src/proto/SConsopts
M src/sim/SConsopts
8 files changed, 88 insertions(+), 84 deletions(-)
diff --git a/SConstruct b/SConstruct
index b99ecdb..c5aa384 100755
--- a/SConstruct
+++ b/SConstruct
@@ -291,49 +291,53 @@
# Platform-specific configuration. Note again that we assume that all
# builds under a given build root run on the same host platform.
+# From this point, we use 'penv' instead of 'main' to isolate
+# the platform-specific environment updates.
+# main env. is updated at the end of this section with conf.Finish()
conf = gem5_scons.Configure(main)
+penv = conf.env
-CXX_version = readCommand([main['CXX'], '--version'], exception=False)
+CXX_version = readCommand([penv['CXX'], '--version'], exception=False)
-main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
-main['CLANG'] = CXX_version and CXX_version.find('clang') >= 0
-if main['GCC'] + main['CLANG'] > 1:
+penv['GCC'] = CXX_version and CXX_version.find('g++') >= 0
+penv['CLANG'] = CXX_version and CXX_version.find('clang') >= 0
+if penv['GCC'] + penv['CLANG'] > 1:
error('Two compilers enabled at once?')
# Set up default C++ compiler flags
-if main['GCC'] or main['CLANG']:
+if penv['GCC'] or penv['CLANG']:
# As gcc and clang share many flags, do the common parts here
-main.Append(CCFLAGS=['-pipe'])
-main.Append(CCFLAGS=['-fno-strict-aliasing'])
+penv.Append(CCFLAGS=['-pipe'])
+penv.Append(CCFLAGS=['-fno-strict-aliasing'])
# Enable -Wall and -Wextra and then disable the few warnings that
# we consistently violate
-main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
+penv.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
'-Wno-sign-compare', '-Wno-unused-parameter'])
# We always compile using C++14
-main.Append(CXXFLAGS=['-std=c++14'])
+penv.Append(CXXFLAGS=['-std=c++14'])
if sys.platform.startswith('freebsd'):
-main.Append(CCFLAGS=['-I/usr/local/include'])
-main.Append(CXXFLAGS=['-I/usr/local/include'])
+penv.Append(CCFLAGS=['-I/usr/local/include'])
+penv.Append(CXXFLAGS=['-I/usr/local/include'])
# On FreeBSD we need libthr.
-main.Append(LIBS=['thr'])
+penv.Append(LIBS=['thr'])
conf.CheckLinkFlag('-Wl,--as-needed')
if GetOption('gold_linker'):
-main.Append(LINKFLAGS='-fuse-ld=gold')
+penv.Append(LINKFLAGS='-fuse-ld=gold')
# Treat warnings as errors but white list some warnings that we
# want to allow (e.g., deprecation warnings).
-main.Append(CCFLAGS=['-Werror',
+penv.Append(CCFLAGS=['-Werror',
'-Wno-error=deprecated-declarations',
'-Wno-error=deprecated',
])
else:
error('\n'.join((
"Don't know what compiler options to use for your compiler.",
- "compiler: " + main['CXX'],
+ "compiler: " + penv['CXX'],
"version: " + CXX_version.replace('\n', '') if
CXX_version else 'COMMAND NOT FOUND!',
"If you're trying to use a compiler other than GCC",
@@ -344,10 +348,10 @@
"above you will need to ease fix SConstruct and ",
"src/SConscript to support that compiler.")))
-if main['GCC']:
-if compareVersions(main['CXXVERSION'], "5") < 0:
+if penv['GCC']:
+if compareVersions(penv['CXXVERSION'], "5") < 0:
error('gcc version 5 or newer required.\n'
- 'Installed version:', main['CXXVERSION'])
+ 'Installed version:', penv['CXXVERSION'])
# If not disabled, set the Link-Time Optimization (LTO) flags.
if not GetOption('no_lto'):
@@ -355,7 +359,7 @@
# the environment variable "MAKE", but we currently make no
attempt to
# plumb that variable through.
parallelism = ''
-if main.Detect('make'):
+if penv.Detect('make'):
parallelism = '=%d' % GetOption('num_jobs')
else:
warning('"make" not found, link time optimization will be '
@@ -363,32 +367,32 @@
for var in 'LTO_CCFLAGS', 'LTO_LDFLAGS':
# Use the same amount of jobs for LTO as we are running scons
with.
-main[var] = ['-flto%s' % parallelism]
+
[gem5-dev] Change in gem5/gem5[develop]: misc,mem-ruby: Fixing unused variable error for fast builds
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44086 )
Change subject: misc,mem-ruby: Fixing unused variable error for fast builds
..
misc,mem-ruby: Fixing unused variable error for fast builds
This fixes the broken compiler tests for .fast builds:
https://www.mail-archive.com/gem5-dev@gem5.org/msg38412.html
Change-Id: Ibc377a57ce6455ca709003f326b0ca8d4c01377b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44086
Reviewed-by: Gabe Black
Reviewed-by: Tiago Mück
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
M src/mem/ruby/protocol/chi/CHI-cache-ports.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 10 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Tiago Mück: Looks good to me, but someone else must approve
Gabe Black: Looks good to me, but someone else must approve
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
index ea5eaff..b1a7d99 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -1844,10 +1844,10 @@
action(UpdateDataState_FromWUDataResp, desc="") {
assert(is_valid(tbe));
- int offset := addressOffset(tbe.accAddr, tbe.addr);
if (tbe.expected_req_resp.hasReceivedData()) {
-assert(tbe.dataBlkValid.test(offset));
-assert(tbe.dataBlkValid.test(offset + tbe.accSize - 1));
+assert(tbe.dataBlkValid.test(addressOffset(tbe.accAddr, tbe.addr)));
+assert(tbe.dataBlkValid.test(addressOffset(tbe.accAddr, tbe.addr)
+ + tbe.accSize - 1));
peek(datInPort, CHIDataMsg) {
assert(in_msg.type == CHIDataType:NCBWrData);
tbe.dataDirty := true;
@@ -2682,7 +2682,9 @@
assert(is_valid(victim_entry));
TBE victim_tbe := getCurrentActiveTBE(victim_addr);
-if (is_invalid(victim_tbe)) {
+// The `is_valid(victim_entry)` condition here is to avoid an unused
+// variable error when compiling to gem5.fast.
+if (is_invalid(victim_tbe) && is_valid(victim_entry)) {
DPRINTF(RubySlicc, "Eviction for %#x victim: %#x state=%s\n",
address, victim_addr, victim_entry.state);
enqueue(replTriggerOutPort, ReplacementMsg, 0) {
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-ports.sm
b/src/mem/ruby/protocol/chi/CHI-cache-ports.sm
index 6a4fe5b..efba9bc 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-ports.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-ports.sm
@@ -96,8 +96,8 @@
if (datInPort.isReady(clockEdge())) {
printResources();
peek(datInPort, CHIDataMsg) {
- int received := in_msg.bitMask.count();
- assert((received <= data_channel_size) && (received > 0));
+ assert((in_msg.bitMask.count() <= data_channel_size)
+ && (in_msg.bitMask.count() > 0));
trigger(dataToEvent(in_msg.type), in_msg.addr,
getCacheEntry(in_msg.addr),
getCurrentActiveTBE(in_msg.addr));
}
diff --git a/src/mem/ruby/protocol/chi/CHI-mem.sm
b/src/mem/ruby/protocol/chi/CHI-mem.sm
index 954a449..08f8b8e 100644
--- a/src/mem/ruby/protocol/chi/CHI-mem.sm
+++ b/src/mem/ruby/protocol/chi/CHI-mem.sm
@@ -365,8 +365,8 @@
if (datInPort.isReady(clockEdge())) {
printResources();
peek(datInPort, CHIDataMsg) {
-int received := in_msg.bitMask.count();
-assert((received <= data_channel_size) && (received > 0));
+assert((in_msg.bitMask.count() <= data_channel_size)
+&& (in_msg.bitMask.count() > 0));
trigger(dataToEvent(in_msg.type), in_msg.addr, TBEs[in_msg.addr]);
}
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44086
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc377a57ce6455ca709003f326b0ca8d4c01377b
Gerrit-Change-Number: 44086
Gerrit-PatchSet: 5
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Fix Temperature class
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/44167 ) Change subject: sim: Fix Temperature class .. sim: Fix Temperature class * Adding __str__ method: To fix its printing on config.ini (Replacing with the Temperature value * Replacing "fromKelvin" with from_kelvin (that's how pybind exports it) * Fixing config_value to allow JSON serialization (JIRA: https://gem5.atlassian.net/browse/GEM5-951) Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2 Signed-off-by: Giacomo Travaglini --- M src/python/m5/params.py 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/python/m5/params.py b/src/python/m5/params.py index c2c0534..8e42eb9 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -1706,12 +1706,15 @@ self.__init__(value) return value +def __str__(self): +return str(self.value) + def getValue(self): from _m5.core import Temperature -return Temperature.fromKelvin(self.value) +return Temperature.from_kelvin(self.value) def config_value(self): -return self +return self.value @classmethod def cxx_predecls(cls, code): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44167 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2 Gerrit-Change-Number: 44167 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Align gem5 to FVP Base PCI
Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/44165 ) Change subject: dev-arm: Align gem5 to FVP Base PCI .. dev-arm: Align gem5 to FVP Base PCI The VExpress_GEM5_Foundation platform was reserving a region of the memory map (@ 0x4 ) for PCI. The Armv8-A FVP Foundation platform is not PCI capable at the moment, so any PCI logic is really gem5 specific. With this patch we are aligning gem5 to the FVP Base Platform, which supports PCI and it is reserving 256GiB of memory starting at 0x40 (256GiB). Fast Models - Reference Manual - Version 11.8 At the moment we are still supporting a single DRAM range, starting at 2GiB. So DRAM could overlap with the PCI memory region though it is unlikely to happen in near future as it would require a DRAM size > 254 GiB. JIRA: https://gem5.atlassian.net/browse/GEM5-898 Change-Id: I506fd6696cdddc39d057602581cb16b30db3f7c7 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44165 Maintainer: Bobby R. Bruce Maintainer: Andreas Sandberg Tested-by: kokoro Reviewed-by: Andreas Sandberg --- M src/dev/arm/RealView.py 1 file changed, 8 insertions(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved; Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index a7080d8..229943c 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1374,12 +1374,19 @@ Reference for memory and interrupt map: Armv8-A Foundation Platform - User Guide - Version 11.8 Document ID: 100961_1180_00_en + +We are adding PCI capabilities to the Armv8-A FVP Foundation +Platform. We are enabling it by using the PCI memory map +of the Armv8-A FVP Base Platform: +Fast Models - Reference Manual - Version 11.8 +Document ID: 100964_1108_00_en """ _off_chip_ranges = [ # CS1-CS5 AddrRange(0x0c00, 0x2000), # External AXI interface (PCI) AddrRange(0x4000, 0x8000), +AddrRange(0x40, 0x8), ] sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True) @@ -1393,7 +1400,7 @@ pci_host = GenericArmPciHost( conf_base=0x4000, conf_size='256MiB', conf_device_bits=12, pci_pio_base=0x5000, -pci_mem_base=0x4, +pci_mem_base=0x40, int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4) def _on_chip_devices(self): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44165 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I506fd6696cdddc39d057602581cb16b30db3f7c7 Gerrit-Change-Number: 44165 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: Increased the upper bound of cpu issue width
Han-sheng Liu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44225 )
Change subject: Increased the upper bound of cpu issue width
..
Increased the upper bound of cpu issue width
The upper bound was 8, but issue width increased to 12 since Cortex A77.
(https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a77)
This CL increased the upper bound to 12.
Bug: 175759373
Test: gem5/main/config/example/se.py
Change-Id: I9d084b940628a2bcfa676d386d3d1a82ba9b03f2
---
M src/cpu/o3/impl.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/o3/impl.hh b/src/cpu/o3/impl.hh
index f180e94..49d6edf 100644
--- a/src/cpu/o3/impl.hh
+++ b/src/cpu/o3/impl.hh
@@ -71,7 +71,7 @@
typedef O3CPU CPUType;
enum {
- MaxWidth = 8,
+ MaxWidth = 12,
MaxThreads = 4
};
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44225
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d084b940628a2bcfa676d386d3d1a82ba9b03f2
Gerrit-Change-Number: 44225
Gerrit-PatchSet: 1
Gerrit-Owner: Han-sheng Liu
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs: Add --kvm-userspace-gic to fs_bigLITTLE.py
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44006 )
Change subject: configs: Add --kvm-userspace-gic to fs_bigLITTLE.py
..
configs: Add --kvm-userspace-gic to fs_bigLITTLE.py
This will allow a user to select gem5 simulation of the GIC via
command line; Necessary option when the simulated GIC != than the
host GIC
Signed-off-by: Giacomo Travaglini
Change-Id: I30e151b774ddfa7f4e91054a375254e15007af3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44006
Reviewed-by: Jason Lowe-Power
Reviewed-by: Richard Cooper
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 14 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index c7edb29..c590fe5 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -197,6 +197,9 @@
help="Custom Linux kernel command")
parser.add_argument("--bootloader", action="append",
help="executable file that runs before the
--kernel")
+parser.add_argument("--kvm-userspace-gic", action="store_true",
+default=False,
+help="Use the gem5 GIC in a KVM simulation")
parser.add_argument("-P", "--param", action="append", default=[],
help="Set a SimObject parameter relative to the root node. "
"An extended Python multi range slicing syntax can be used "
@@ -281,7 +284,7 @@
# Create a KVM VM and do KVM-specific configuration
if issubclass(big_model, KvmCluster):
-_build_kvm(system, all_cpus)
+_build_kvm(options, system, all_cpus)
# Linux device tree
if options.dtb is not None:
@@ -305,9 +308,18 @@
return root
-def _build_kvm(system, cpus):
+def _build_kvm(options, system, cpus):
system.kvm_vm = KvmVM()
+if options.kvm_userspace_gic:
+# We will use the simulated GIC.
+# In order to make it work we need to remove the system interface
+# of the generic timer from the DTB and we need to inform the
+# MuxingKvmGic class to use the gem5 GIC instead of relying on the
+# host interrupt controller
+GenericTimer.generateDeviceTree = SimObject.generateDeviceTree
+system.realview.gic.simulate_gic = True
+
# Assign KVM CPUs to their own event queues / threads. This
# has to be done after creating caches and other child objects
# since these mustn't inherit the CPU event queue.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44006
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30e151b774ddfa7f4e91054a375254e15007af3f
Gerrit-Change-Number: 44006
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
