[gem5-dev] Change in gem5/gem5[develop]: ruby: fix typo in VIPER TCC triggerQueue

2021-04-27 Thread Matt Sinclair (Gerrit) via gem5-dev 
Matt Sinclair has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44905 )


Change subject: ruby: fix typo in VIPER TCC triggerQueue
..

ruby: fix typo in VIPER TCC triggerQueue

The GPU VIPER TCC protocol accidentally used "TiggerMsg" instead
of "TriggerMsg" for the triggerQueue_in port.  This was a benign
bug beacuse the msg type is not used in the in_port implementation
but still makes the SLICC harder to understand, so fixing it is
worthwhile.

Change-Id: I88cbc72bac93bcc58a66f057a32f7bddf821cac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44905
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Matthew Poremba 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm  
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm

index e21ba99..6c07416 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -252,7 +252,7 @@


 // ** IN_PORTS **
-  in_port(triggerQueue_in, TiggerMsg, triggerQueue) {
+  in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 if (triggerQueue_in.isReady(clockEdge())) {
   peek(triggerQueue_in, TriggerMsg) {
 TBE tbe := TBEs.lookup(in_msg.addr);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I88cbc72bac93bcc58a66f057a32f7bddf821cac9
Gerrit-Change-Number: 44905
Gerrit-PatchSet: 2
Gerrit-Owner: Matt Sinclair 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Kyle Roarty 
Gerrit-MessageType: merged
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[gem5-dev] ISA object and ISA specific CPU components

2021-04-27 Thread Gabe Black via gem5-dev 
Hi folks. I can write up a more detailed document once there has been some
discussion about this, but I've been thinking about how the ISA object
works, and how the various ISA specific components of a CPU (decoder, TLBs,
interrupt object, ISA object itself) are hooked into each other.

As of today, each context of execution has its own copy of the decoder, the
TLBs, the interrupt object (the local APIC in x86, basically ISA specific
interrupt handling logic), and the ISA object (home of MiscRegs, some other
stuff).

My initial idea behind creating the ISA object was that it could be a home
for settings which affect the ISA itself, like what optional features were
enabled, what specific version of the ISA was in effect, etc. It made sense
to build that into the thing handling MiscRegs, since the value of and
behavior of those registers.

All of these objects could, at least in theory, have configuration
parameters associated with them (size of the TLB, ISA parameters for
supported features, etc), and are generally represented by SimObjects which
are separately configured, and then plugged into the CPU in python.

One problem with having the ISA object hold ISA specific configuration
comes from the fact that it's set up per thread, and there isn't a
centralized collection point for settings that should be common across
several threads. ARM currently solves this problem by creating a custom
System class, I believe the only one still in use in gem5 now, which holds
those settings and then distributes them to the ISA objects (I believe?).
This also creates a problem where there needs to be a custom System object,
and it needs to communicate with the ISA objects and keep each other in
sync.


What I think might make more sense is to adjust the role of the ISA object
a bit and expand it to be a single object which is assigned to a System. It
could then absorb all the ISA specific properties which are now part of the
ARM custom System class. Then, every time a ThreadContext is registered
with the System, the ISA object would have a chance to register its own
objects with it, including adding thread specific information like an
interrupts object, a decoder, a local object to handle MiscReg accesses,
etc., which could, as necessary, have ties back to the common ISA object.

There would need to be a balance here between things which come from the
ISA object and things which do need to come from each CPU in the system,
like a way to set different TLB sizes for differently spec-ed cores for
instance. Maybe the ISA has some settings for those objects, and it sets
them post-facto when setting up a thread?

Additionally, the new ISA regClassInfo array which describes what register
types there are and their properties could then be common to all threads
instead of duplicated in each ISA instance, and could be installed in the
ThreadContext by the ISA object, instead of having to be fetched from the
ISA object by everybody else as needed.

You can probably tell that I haven't thought this out completely, but I
wanted to throw this out there for people to see and respond to, so please
see it and respond to it :-).

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86

2021-04-27 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44885 )


Change subject: arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86
..

arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86

Unused variable errors occurred when compiling gem5.fast with GCC. This
patch fixes this.

Change-Id: Iaca1fb8194c2381c0a4ba5d0ea1fb5b8f2a11829
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44885
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Matt Sinclair 
Reviewed-by: Matthew Poremba 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/dev/hsa/hsa_packet_processor.cc
M src/gpu-compute/gpu_compute_driver.cc
2 files changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Matt Sinclair: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index cd6ef5a..eeb64da 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -133,8 +133,7 @@
   "%s: write of size %d to reg-offset %d (0x%x)\n",
   __FUNCTION__, pkt->getSize(), daddr, daddr);

-int doorbellSize = gpu_device->driver()->doorbellSize();
-assert(doorbellSize == pkt->getSize());
+assert(gpu_device->driver()->doorbellSize() == pkt->getSize());

 uint64_t doorbell_reg(0);
 if (pkt->getSize() == 8)
diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 8c79be3..ac42752 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -582,7 +582,7 @@

 assert(isdGPU);
 assert((args->va_addr % TheISA::PageBytes) == 0);
-Addr mmap_offset = 0;
+M5_VAR_USED Addr mmap_offset = 0;

 Request::CacheCoherenceFlags mtype = defaultMtype;
 Addr pa_addr = 0;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaca1fb8194c2381c0a4ba5d0ea1fb5b8f2a11829
Gerrit-Change-Number: 44885
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Initial configuration for full-system GPU

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44907 )



Change subject: configs: Initial configuration for full-system GPU
..

configs: Initial configuration for full-system GPU

This is an initial configuration capable of booting Linux and
registering a PCI device which registers as an AMD Vega 10 (Frontier
Edition) GPU. It it loosely based on the the example/fs.py and gem5 book
full system example scripts. The top-level file is meant to be modular
such that convenience scripts can be created to set arguments
automatically and then call the main run function.

This will evolve over time as more full-system GPU components are added
and the network topology needed for disjoint address spaces is created
for the VIPER protocol.

Change-Id: I7002213ca8de5eb73919e49fb11840a688744012
---
A configs/gpufs/amd/AmdGPUOptions.py
A configs/gpufs/runfs.py
A configs/gpufs/system/amdgpu.py
A configs/gpufs/system/system.py
4 files changed, 565 insertions(+), 0 deletions(-)



diff --git a/configs/gpufs/amd/AmdGPUOptions.py  
b/configs/gpufs/amd/AmdGPUOptions.py

new file mode 100644
index 000..272c417
--- /dev/null
+++ b/configs/gpufs/amd/AmdGPUOptions.py
@@ -0,0 +1,127 @@
+# Copyright (c) 2021 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are  
met:

+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright  
notice,

+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS  
IS"

+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE

+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

+# POSSIBILITY OF SUCH DAMAGE.
+
+def addAmdGPUOptions(parser):
+parser.add_argument("-u", "--num-compute-units", type=int, default=4,
+help="number of GPU compute units"),
+parser.add_argument("--num-cp", type=int, default=0,
+help="Number of GPU Command Processors (CP)")
+
+# not super important now, but to avoid putting the number 4  
everywhere,

+# make it an option/knob
+parser.add_argument("--cu-per-sqc", type=int, default=4,
+help="number of CUs sharing an SQC"
+" (icache, and thus icache TLB)")
+parser.add_argument("--cu-per-scalar-cache", type=int, default=4,
+help="Number of CUs sharing a scalar cache")
+parser.add_argument("--simds-per-cu", type=int, default=4,
+help="SIMD units per CU")
+parser.add_argument("--cu-per-sa", type=int, default=4,
+help="Number of CUs per shader array. This must be  
a"

+" multiple of options.cu-per-sqc and "
+" options.cu-per-scalar")
+parser.add_argument("--sa-per-complex", type=int, default=1,
+help="Number of shader arrays per complex")
+parser.add_argument("--num-gpu-complexes", type=int, default=1,
+help="Number of GPU complexes")
+parser.add_argument("--wf-size", type=int, default=64,
+help="Wavefront size(in workitems)")
+parser.add_argument("--sp-bypass-path-length", type=int, default=4,
+help="Number of stages of bypass path in vector  
ALU "

+"for Single Precision ops")
+parser.add_argument("--dp-bypass-path-length", type=int, default=4,
+help="Number of stages of bypass path in vector  
ALU "

+"for Double Precision ops")
+#issue period per SIMD unit: number of cycles before issuing another  
vector

+parser.add_argument("--issue-period",

[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Add initial AMDGPU device

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44909 )



Change subject: dev-amdgpu: Add initial AMDGPU device
..

dev-amdgpu: Add initial AMDGPU device

The initial device contains enough code for the gpufs configuration
scripts to register an amdgpu device that identifies as a Vega 10
(Frontier Edition) device when PCI devices are listed by Linux. It also
contains stubs necessary for adding the MMIO interface to handle driver
initialization.

Using the configuration Linux boots and the device is successfully seen
in lspci. The driver can also begin loading an successfully sends
initial MMIOs and attempts to read the ROM.

Change-Id: I7ad87026876f31f44668e700d5adb639c2c053c1
---
A src/dev/amdgpu/AMDGPU.py
A src/dev/amdgpu/SConscript
A src/dev/amdgpu/amdgpu_device.cc
A src/dev/amdgpu/amdgpu_device.hh
4 files changed, 463 insertions(+), 0 deletions(-)



diff --git a/src/dev/amdgpu/AMDGPU.py b/src/dev/amdgpu/AMDGPU.py
new file mode 100644
index 000..951c833
--- /dev/null
+++ b/src/dev/amdgpu/AMDGPU.py
@@ -0,0 +1,75 @@
+# Copyright (c) 2021 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are  
met:

+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright  
notice,

+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+# contributors may be used to endorse or promote products derived from this
+# software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS  
IS"

+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE

+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF  
THE

+# POSSIBILITY OF SUCH DAMAGE.
+
+from m5.params import *
+from m5.objects.PciDevice import PciDevice
+from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar
+
+class AMDGPUDevice(PciDevice):
+type = 'AMDGPUDevice'
+cxx_header = "dev/amdgpu/amdgpu_device.hh"
+
+# IDs for AMD Vega 10
+VendorID = 0x1002
+DeviceID = 0x6863
+# Command 0x3 never gets sent indicating IO and Mem bars are enabled.  
Hard

+# code the command here and deal unassigned BARs on C++ side.
+Command = 0x3
+Status = 0x0280
+Revision = 0x0
+ClassCode = 0x03
+SubClassCode = 0x00
+ProgIF = 0x00
+
+# This does not work but I believe it is supposed to:
+#BARs = (PciMemBar(size='16GiB'), PciMemUpperBar(),  
PciMemBar(size='2MiB'),

+#PciMemUpperBar(), PciLegacyIoBar(addr = 0xf000, size='256B'),
+#PciMemBar(size='512KiB'))
+BAR0 = PciMemBar(size='16GiB')
+BAR1 = PciMemUpperBar()
+BAR2 = PciMemBar(size='2MiB')
+BAR3 = PciMemUpperBar()
+BAR4 = PciLegacyIoBar(addr=0xf000, size='256B')
+BAR5 = PciMemBar(size='512KiB')
+
+InterruptLine = 14
+InterruptPin = 2
+ExpansionROM = 0
+
+RomBin = Param.String("/i/dont/exist",
+  "ROM binary dumped from hardware")
+traceFile = Param.String("/i/dont/exist",
+ "MMIO trace collected on hardware")
+
+def setTraceFile(self, trace):
+self.traceFile = trace
+def setRomBin(self, rom):
+self.RomBin = rom
diff --git a/src/dev/amdgpu/SConscript b/src/dev/amdgpu/SConscript
new file mode 100644
index 000..dcd2d30
--- /dev/null
+++ b/src/dev/amdgpu/SConscript
@@ -0,0 +1,42 @@
+# Copyright (c) 2021 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# For use for simulation and test purposes only
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are  
met:

+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright  
notice,

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove deprecated port names in GPU_VIPER

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44906 )



Change subject: configs: Remove deprecated port names in GPU_VIPER
..

configs: Remove deprecated port names in GPU_VIPER

Remove the port names that were deprecated in 21.0 and replace with the
new names in GPU_VIPER.py.

Change-Id: Ied770982ccd365638923c71a0ea8bcf9936d358e
---
M configs/ruby/GPU_VIPER.py
1 file changed, 41 insertions(+), 40 deletions(-)



diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 1ac7c07..e315543 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -462,19 +462,19 @@

 # Connect the Directory controller to the ruby network
 dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
-dir_cntrl.requestFromCores.slave = ruby_system.network.master
+dir_cntrl.requestFromCores.in_port = ruby_system.network.out_port

 dir_cntrl.responseFromCores = MessageBuffer()
-dir_cntrl.responseFromCores.slave = ruby_system.network.master
+dir_cntrl.responseFromCores.in_port = ruby_system.network.out_port

 dir_cntrl.unblockFromCores = MessageBuffer()
-dir_cntrl.unblockFromCores.slave = ruby_system.network.master
+dir_cntrl.unblockFromCores.in_port = ruby_system.network.out_port

 dir_cntrl.probeToCore = MessageBuffer()
-dir_cntrl.probeToCore.master = ruby_system.network.slave
+dir_cntrl.probeToCore.out_port = ruby_system.network.in_port

 dir_cntrl.responseToCore = MessageBuffer()
-dir_cntrl.responseToCore.master = ruby_system.network.slave
+dir_cntrl.responseToCore.out_port = ruby_system.network.in_port

 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
@@ -482,10 +482,10 @@
 dir_cntrl.responseFromMemory = MessageBuffer()

 dir_cntrl.requestFromDMA = MessageBuffer(ordered=True)
-dir_cntrl.requestFromDMA.slave = ruby_system.network.master
+dir_cntrl.requestFromDMA.in_port = ruby_system.network.out_port

 dir_cntrl.responseToDMA = MessageBuffer()
-dir_cntrl.responseToDMA.master = ruby_system.network.slave
+dir_cntrl.responseToDMA.out_port = ruby_system.network.in_port

 dir_cntrl.requestToMemory = MessageBuffer()
 dir_cntrl.responseFromMemory = MessageBuffer()
@@ -513,19 +513,19 @@

 # Connect the CP controllers and the network
 cp_cntrl.requestFromCore = MessageBuffer()
-cp_cntrl.requestFromCore.master = ruby_system.network.slave
+cp_cntrl.requestFromCore.out_port = ruby_system.network.in_port

 cp_cntrl.responseFromCore = MessageBuffer()
-cp_cntrl.responseFromCore.master = ruby_system.network.slave
+cp_cntrl.responseFromCore.out_port = ruby_system.network.in_port

 cp_cntrl.unblockFromCore = MessageBuffer()
-cp_cntrl.unblockFromCore.master = ruby_system.network.slave
+cp_cntrl.unblockFromCore.out_port = ruby_system.network.in_port

 cp_cntrl.probeToCore = MessageBuffer()
-cp_cntrl.probeToCore.slave = ruby_system.network.master
+cp_cntrl.probeToCore.in_port = ruby_system.network.out_port

 cp_cntrl.responseToCore = MessageBuffer()
-cp_cntrl.responseToCore.slave = ruby_system.network.master
+cp_cntrl.responseToCore.in_port = ruby_system.network.out_port

 cp_cntrl.mandatoryQueue = MessageBuffer()
 cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
@@ -610,19 +610,19 @@

 # Connect the TCP controller to the ruby network
 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
-tcp_cntrl.requestFromTCP.master = ruby_system.network.slave
+tcp_cntrl.requestFromTCP.out_port = ruby_system.network.in_port

 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
-tcp_cntrl.responseFromTCP.master = ruby_system.network.slave
+tcp_cntrl.responseFromTCP.out_port = ruby_system.network.in_port

 tcp_cntrl.unblockFromCore = MessageBuffer()
-tcp_cntrl.unblockFromCore.master = ruby_system.network.slave
+tcp_cntrl.unblockFromCore.out_port = ruby_system.network.in_port

 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
-tcp_cntrl.probeToTCP.slave = ruby_system.network.master
+tcp_cntrl.probeToTCP.in_port = ruby_system.network.out_port

 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
-tcp_cntrl.responseToTCP.slave = ruby_system.network.master
+tcp_cntrl.responseToTCP.in_port = ruby_system.network.out_port

 tcp_cntrl.mandatoryQueue = MessageBuffer()

@@ -641,13 +641,13 @@

 # Connect the SQC controller to the ruby network
 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
-

[gem5-dev] Change in gem5/gem5[develop]: misc: Add dev-amdgpu tag

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44908 )



Change subject: misc: Add dev-amdgpu tag
..

misc: Add dev-amdgpu tag

This tag will be used for code related to the full-system GPU PCI
device. The purpose is to tag AMD maintainers to changes in this
directory rather than the more general dev tag maintainers.

Change-Id: I6ca5347c056ae9735c3a7bb4ae3c4e51ff786551
---
M MAINTAINERS.yaml
1 file changed, 5 insertions(+), 0 deletions(-)



diff --git a/MAINTAINERS.yaml b/MAINTAINERS.yaml
index ec5176a..7868313 100644
--- a/MAINTAINERS.yaml
+++ b/MAINTAINERS.yaml
@@ -146,6 +146,11 @@
   maintainers:
 - Matt Poremba 

+dev-amdgpu:
+  status: maintained
+  maintainers:
+- Matt Poremba 
+
 dev-virtio:
   status: maintained
   maintainers:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ca5347c056ae9735c3a7bb4ae3c4e51ff786551
Gerrit-Change-Number: 44908
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: ruby: fix typo in VIPER TCC triggerQueue

2021-04-27 Thread Matt Sinclair (Gerrit) via gem5-dev 
Matt Sinclair has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44905 )



Change subject: ruby: fix typo in VIPER TCC triggerQueue
..

ruby: fix typo in VIPER TCC triggerQueue

The GPU VIPER TCC protocol accidentally used "TiggerMsg" instead
of "TriggerMsg" for the triggerQueue_in port.  This was a benign
bug beacuse the msg type is not used in the in_port implementation
but still makes the SLICC harder to understand, so fixing it is
worthwhile.

Change-Id: I88cbc72bac93bcc58a66f057a32f7bddf821cac9
---
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm  
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm

index e21ba99..6c07416 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -252,7 +252,7 @@


 // ** IN_PORTS **
-  in_port(triggerQueue_in, TiggerMsg, triggerQueue) {
+  in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
 if (triggerQueue_in.isReady(clockEdge())) {
   peek(triggerQueue_in, TriggerMsg) {
 TBE tbe := TBEs.lookup(in_msg.addr);

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[gem5-dev] Change in gem5/gem5[develop]: scons: Add `--with-lto` flag to enabled LTO for all builds

2021-04-27 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44887 )



Change subject: scons: Add `--with-lto` flag to enabled LTO for all builds
..

scons: Add `--with-lto` flag to enabled LTO for all builds

Change-Id: I2eea7d447703491675c02730707cf9026cface5f
---
M SConstruct
M src/SConscript
2 files changed, 50 insertions(+), 25 deletions(-)



diff --git a/SConstruct b/SConstruct
index f3d65f0..d192b91 100755
--- a/SConstruct
+++ b/SConstruct
@@ -107,6 +107,8 @@
   help="Don't compress debug info in build files")
 AddOption('--no-lto', action='store_true',
   help='Disable Link-Time Optimization for fast')
+AddOption('--with-lto', action='store_true',
+  help='Enable Link-Time Optimization')
 AddOption('--verbose', action='store_true',
   help='Print full tool command lines')
 AddOption('--without-python', action='store_true',
@@ -262,9 +264,32 @@
 main.Prepend(CPPPATH=Dir('include'))

 # Initialize the Link-Time Optimization (LTO) flags
+
+if GetOption('no_lto') and GetOption('with_lto'):
+error('\n'.join((
+  "`--no-lto` and `--with-lto` are both set. These are mutually ",
+  "exclusive flags. `--no-lto` disables LTO for .fast builds ",
+  "(enabled by default). `--with-lto` enables LTO for all  
builds.")))

+
+
 main['LTO_CCFLAGS'] = []
 main['LTO_LDFLAGS'] = []

+# THE LTO flags to set for the .fast builds only (the other builds use
+# 'LTO_CCFLAGS' and 'LTO_LDFLAGS')
+main['LTO_CCFLAGS_FAST'] = []
+main['LTO_LDFLAGS_FAST'] = []
+
+lto_flags_to_set = []
+
+if not GetOption('no_lto'):
+lto_flags_to_set.append('LTO_CCFLAGS_FAST')
+lto_flags_to_set.append('LTO_LDFLAGS_FAST')
+if GetOption('with_lto'):
+lto_flags_to_set.append('LTO_CCFLAGS')
+lto_flags_to_set.append('LTO_LDFLAGS')
+
+
 # According to the readme, tcmalloc works best if the compiler doesn't
 # assume that we're using the builtin malloc and friends. These flags
 # are compiler-specific, so we need to set them after we detect which
@@ -329,22 +354,23 @@
   'Installed version:', main['CXXVERSION'])

 # Add the appropriate Link-Time Optimization (LTO) flags
-# unless LTO is explicitly turned off. Note that these flags
-# are only used by the fast target.
-if not GetOption('no_lto'):
-# g++ uses "make" to parallelize LTO. The program can be overriden  
with
-# the environment variable "MAKE", but we currently make no  
attempt to

-# plumb that variable through.
-parallelism = ''
-if main.Detect('make'):
-parallelism = '=%d' % GetOption('num_jobs')
-else:
-warning('"make" not found, link time optimization will be '
-'single threaded.')
+# Note that these flags are only used by .fast by default. If  
`--no-lto` is

+# set .fast will link without LTO. If `--with-lto` is set, all gem5
+# variants (opt, debug, etc.) are linked with LTO.
+#
+# g++ uses "make" to parallelize LTO. The program can be overriden with
+# the environment variable "MAKE", but we currently make no attempt to
+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')

-for var in 'LTO_CCFLAGS', 'LTO_LDFLAGS':
-# Use the same amount of jobs for LTO as we are running scons  
with.

-main[var] = ['-flto%s' % parallelism]
+for var in lto_flags_to_set:
+# Use the same amount of jobs for LTO as we are running scons with.
+main[var] = ['-flto%s' % parallelism]

  
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',

   '-fno-builtin-realloc', '-fno-builtin-free'])
@@ -354,10 +380,8 @@
 error('clang version 3.9 or newer required.\n'
   'Installed version:', main['CXXVERSION'])

-# If not disabled, set the Link-Time Optimization (LTO) flags.
-if not GetOption('no_lto'):
-for var in 'LTO_CCFLAGS', 'LTO_LDFLAGS':
-main[var] = ['-flto']
+for var in lto_flags_to_set:
+main[var] = ['-flto']

 # clang has a few additional warnings that we disable.
 with gem5_scons.Configure(main) as conf:
diff --git a/src/SConscript b/src/SConscript
index 47aa2ea..1daf3e6 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1431,15 +1431,16 @@
 else:
 ccflags['debug'] += ['-ggdb3']
 ldflags['debug'] += ['-O0']
-# opt, fast, prof and perf all share the same cc flags, also add
+# opt, prof and perf all share the same cc flags, also add
 # the optimization to the ldflags as LTO defers the optimization
 # to link time
-for target in ['opt', 'fast', 'prof',

[gem5-dev] Change in gem5/gem5[develop]: scons: Revert "Enable LTO for opt, perf and prof builds."

2021-04-27 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44886 )



Change subject: scons: Revert "Enable LTO for opt, perf and prof builds."
..

scons: Revert "Enable LTO for opt, perf and prof builds."

This reverts
https://gem5-review.googlesource.com/c/public/gem5/+/40815

Change-Id: I7dbd2b70c90c98f38c7c02eb052571f7b6bd
---
M SConstruct
M src/SConscript
2 files changed, 8 insertions(+), 3 deletions(-)



diff --git a/SConstruct b/SConstruct
index 3e2df39..f3d65f0 100755
--- a/SConstruct
+++ b/SConstruct
@@ -328,7 +328,9 @@
 error('gcc version 5 or newer required.\n'
   'Installed version:', main['CXXVERSION'])

-# If not disabled, set the Link-Time Optimization (LTO) flags.
+# Add the appropriate Link-Time Optimization (LTO) flags
+# unless LTO is explicitly turned off. Note that these flags
+# are only used by the fast target.
 if not GetOption('no_lto'):
 # g++ uses "make" to parallelize LTO. The program can be overriden  
with
 # the environment variable "MAKE", but we currently make no  
attempt to

diff --git a/src/SConscript b/src/SConscript
index 831f5c6..47aa2ea 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1435,8 +1435,11 @@
 # the optimization to the ldflags as LTO defers the optimization
 # to link time
 for target in ['opt', 'fast', 'prof', 'perf']:
-ccflags[target] += ['-O3'] + env['LTO_CCFLAGS']
-ldflags[target] += ['-O3'] + env['LTO_LDFLAGS']
+ccflags[target] += ['-O3']
+ldflags[target] += ['-O3']
+
+ccflags['fast'] += env['LTO_CCFLAGS']
+ldflags['fast'] += env['LTO_LDFLAGS']
 elif env['CLANG']:
 ccflags['debug'] += ['-g', '-O0']
 # opt, fast, prof and perf all share the same cc flags

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Revert "configs: Only add CPU sequencers to piobus"

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44865 )


Change subject: configs: Revert "configs: Only add CPU sequencers to piobus"
..

configs: Revert "configs: Only add CPU sequencers to piobus"

This reverts commit 4ef0bd03ab967ca76eea8061a194c677c61610a2.

Change-Id: I7c85a5166924c26de8e6e7d2a14a37ede7cedbcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44865
Maintainer: Matthew Poremba 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/Ruby.py
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matthew Poremba: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 0db9d93..16bb184 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -237,8 +237,7 @@
 # Connect the cpu sequencers and the piobus
 if piobus != None:
 for cpu_seq in cpu_sequencers:
-if cpu_seq.is_cpu_sequencer:
-cpu_seq.connectIOPorts(piobus)
+cpu_seq.connectIOPorts(piobus)

 ruby.number_of_virtual_networks =  
ruby.network.number_of_virtual_networks

 ruby._cpu_ports = cpu_sequencers

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Gerrit-Project: public/gem5
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Gerrit-Change-Number: 44865
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: python,tests: Update pyunit tests to run in TestLib

2021-04-27 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44625 )


Change subject: python,tests: Update pyunit tests to run in TestLib
..

python,tests: Update pyunit tests to run in TestLib

Previously the pyunit tests needed run in the gem5 root, this change
allows them to run as part of the quick TestLib tests (thereby having
them run as part of the presubmit checks). This runs all the TestLib
tests as a single test using the NULL gem5 binary.

`tests/run_pyunit.py` has been updated to only parse files with the
`pyunit` prefix in their filname. As such `pyunit/util/test_convert.py`
has been renamed `pyunit/util/pyunit_convert_check.py`. The word `test`
has been removed entirely as to not clash with the testlib tests as run
by `tests/main.py`.

Example usage:

```
./main.py run --uid  
SuiteUID:tests/pyunit/test_run.py:pyunit-tests-NULL-x86_64-opt

```

Discussed briefly in email thread:
https://www.mail-archive.com/gem5-dev@gem5.org/msg38563.html

Change-Id: Id566d44fcb5d8c599eb1a90bca56793158a201e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44625
Reviewed-by: Andreas Sandberg 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
A tests/pyunit/test_run.py
R tests/pyunit/util/pyunit_convert_check.py
M tests/run_pyunit.py
3 files changed, 49 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/pyunit/test_run.py b/tests/pyunit/test_run.py
new file mode 100644
index 000..2accd4c
--- /dev/null
+++ b/tests/pyunit/test_run.py
@@ -0,0 +1,48 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import os
+
+from testlib.configuration import constants
+from gem5.suite import *
+
+'''
+As the filename begins with `test_`, it will be added to the TestLib  
testsuite

+when `../main.py` is run.
+
+The purpose of this file is to ensure the pyunit tests are executed as part
+of a typical TestLib execution. These have been added as part of  
the "quick"

+tests and will run with NULL/gem5.*
+'''
+
+gem5_verify_config(
+name="pyunit-tests",
+config=os.path.join(os.getcwd(), os.pardir, 'run_pyunit.py'),
+verifiers=(),
+config_args=[],
+valid_isas=(constants.null_tag,),
+length = constants.quick_tag,
+)
\ No newline at end of file
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/pyunit_convert_check.py

similarity index 100%
rename from tests/pyunit/util/test_convert.py
rename to tests/pyunit/util/pyunit_convert_check.py
diff --git a/tests/run_pyunit.py b/tests/run_pyunit.py
index dcd8984..00f5f9c 100644
--- a/tests/run_pyunit.py
+++ b/tests/run_pyunit.py
@@ -44,7 +44,7 @@
 import unittest

 loader = unittest.TestLoader()
-tests = loader.discover("pyunit")
+tests = loader.discover("pyunit", pattern='pyunit*.py')

 runner = unittest.runner.TextTestRunner(verbosity=2)
 runner.run(tests)

--
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Gerrit-PatchSet: 4
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86

2021-04-27 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44885 )



Change subject: arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86
..

arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86

Unused variable errors occurred when compiling gem5.fast with GCC. This
patch fixes this.

Change-Id: Iaca1fb8194c2381c0a4ba5d0ea1fb5b8f2a11829
---
M src/dev/hsa/hsa_packet_processor.cc
M src/gpu-compute/gpu_compute_driver.cc
2 files changed, 2 insertions(+), 3 deletions(-)



diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index cd6ef5a..eeb64da 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -133,8 +133,7 @@
   "%s: write of size %d to reg-offset %d (0x%x)\n",
   __FUNCTION__, pkt->getSize(), daddr, daddr);

-int doorbellSize = gpu_device->driver()->doorbellSize();
-assert(doorbellSize == pkt->getSize());
+assert(gpu_device->driver()->doorbellSize() == pkt->getSize());

 uint64_t doorbell_reg(0);
 if (pkt->getSize() == 8)
diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 8c79be3..ac42752 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -582,7 +582,7 @@

 assert(isdGPU);
 assert((args->va_addr % TheISA::PageBytes) == 0);
-Addr mmap_offset = 0;
+M5_VAR_USED Addr mmap_offset = 0;

 Request::CacheCoherenceFlags mtype = defaultMtype;
 Addr pa_addr = 0;

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Revert "configs: Only add CPU sequencers to piobus"

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44865 )



Change subject: configs: Revert "configs: Only add CPU sequencers to piobus"
..

configs: Revert "configs: Only add CPU sequencers to piobus"

This reverts commit 4ef0bd03ab967ca76eea8061a194c677c61610a2.

Change-Id: I7c85a5166924c26de8e6e7d2a14a37ede7cedbcd
---
M configs/ruby/Ruby.py
1 file changed, 1 insertion(+), 2 deletions(-)



diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 0db9d93..16bb184 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -237,8 +237,7 @@
 # Connect the cpu sequencers and the piobus
 if piobus != None:
 for cpu_seq in cpu_sequencers:
-if cpu_seq.is_cpu_sequencer:
-cpu_seq.connectIOPorts(piobus)
+cpu_seq.connectIOPorts(piobus)

 ruby.number_of_virtual_networks =  
ruby.network.number_of_virtual_networks

 ruby._cpu_ports = cpu_sequencers

--
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[gem5-dev] Re: Gem5-GCN3 Checkpointing Support

2021-04-27 Thread Poremba, Matthew via gem5-dev 
[AMD Public Use]

Hi Paul,


The trick is to checkpoint "before the GPU starts doing work."  That's a bit 
vague because I am not sure where that point is on the stable release, 
unfortunately. In the new upcoming release for the GPU model it is clear this 
point is when the first dispatch packet is received by the command processor.  
I suspect on the stable branch it would be before any IOCTLs are received by 
the emulated driver, but I am not entirely sure.


-Matt

From: Tschirhart, Paul K [US] (MS) 
Sent: Friday, April 23, 2021 8:21 PM
To: Poremba, Matthew ; gem5 Developer List 

Cc: jlowepo...@ucdavis.edu
Subject: RE: [gem5-dev] Re: Gem5-GCN3 Checkpointing Support

[CAUTION: External Email]
Hi Mathew,

We are mostly just trying to avoid taking the time to simulate the runtime 
initialization in detail. Could you please explain the trick that you 
mentioned? I have tried using both fast-forwarding options that were included 
in apu_se.py but they don't seem to work.

Thanks for your help.

Paul

From: Poremba, Matthew mailto:matthew.pore...@amd.com>>
Sent: Thursday, April 22, 2021 1:17 PM
To: gem5 Developer List mailto:gem5-dev@gem5.org>>
Cc: Tschirhart, Paul K [US] (MS) 
mailto:paul.tschirh...@ngc.com>>; Jason Lowe-Power 
mailto:jlowepo...@ucdavis.edu>>
Subject: EXT :RE: [gem5-dev] Re: Gem5-GCN3 Checkpointing Support


[AMD Public Use]

Hi Paul,


Checkpoints (and similarly switchcpu) in GCN3 do not work once the GPU has 
launched a kernel because the drain functions are not implemented in the GPU 
model.  In general, there is a lot of state to be drained for the GPU.  If you 
drain/serialize between kernels it would probably be the easiest.  This has 
been low priority for us since we've found it sufficient to use KVM 
fast-forward to get to the first kernel and then switch to a timing CPU.

The use case for most users is to simulate single kernel or a handful of 
kernels at a time, so for that starting from the beginning of the application 
and exiting after a certain number of kernels is an unreasonable amount of time.

If the only concern is to avoid the time simulating the runtime initialization 
(before first kernel launch) there is a trick you can do to checkpoint or 
switchcpus (e.g., from KVM) before it launches.



MATTHEW POREMBA
MTS Silicon Design Engineer  |  AMD
AMD Research
O +(1) 425-586-6472  C +(1) 425-518-1014
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2002 156th Ave NE, Suite 300, Bellevue, WA 98007
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From: Jason Lowe-Power via gem5-dev 
mailto:gem5-dev@gem5.org>>
Sent: Thursday, April 22, 2021 8:34 AM
To: gem5-dev@gem5.org
Cc: Tschirhart, Paul K [US] (MS) 
mailto:paul.tschirh...@ngc.com>>; Jason Lowe-Power 
mailto:jlowepo...@ucdavis.edu>>
Subject: [gem5-dev] Re: Gem5-GCN3 Checkpointing Support

[CAUTION: External Email]
Hi Paul,

I've included gem5-dev mailing list here. If you're not subscribed, I would 
suggest sending these kinds of questions there where the gem5-gcn/AMD 
developers will see things.

To answer your question, adding checkpointing should be relatively 
straightforward. The main changes are exactly as you described: saving the 
architectural state of the GPU threads. There are probably a few other pieces 
of GPU state that need to be saved too (e.g., the control processor, etc.). 
Hopefully one of the devs at AMD can reply with more details.

You'll have to add the serialize/unserialize functions, and you'll probably 
have to also implement a drain() function to flush out the current in-progress 
instructions. I imagine you'll at least want to finish the in-progress 
wavefronts, and you may want to wait until the currently scheduled workgroups 
are finished as well.

As far as Ruby

[gem5-dev] Change in gem5/gem5[develop]: configs: Handle various DMA devices in GPU_VIPER

2021-04-27 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44806 )


Change subject: configs: Handle various DMA devices in GPU_VIPER
..

configs: Handle various DMA devices in GPU_VIPER

Viper is checking for the dma's type before making the port assignment.
In FullSystem mode the IDE device is a PortRef and does not have an
attribute 'type.' This handles the various types a bit better and
ensures that IDE device, the protocol tester, and upcoming DMA devices
related to FullSystem can be added.

Change-Id: I6879b25c6aabbbc22b0ee8dc9cbfec6399f70daa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44806
Reviewed-by: Matthew Poremba 
Maintainer: Matthew Poremba 
Tested-by: kokoro 
---
M configs/ruby/GPU_VIPER.py
1 file changed, 6 insertions(+), 1 deletion(-)

Approvals:
  Matthew Poremba: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 01ec602..1ac7c07 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -776,11 +776,16 @@
 dma_cntrl = DMA_Controller(version=i, dma_sequencer=dma_seq,
ruby_system=ruby_system)
 exec('system.dma_cntrl%d = dma_cntrl' % i)
-if dma_device.type == 'MemTest':
+
+# IDE doesn't have a .type but seems like everything else does.
+if not hasattr(dma_device, 'type'):
+exec('system.dma_cntrl%d.dma_sequencer.slave = dma_device' % i)
+elif dma_device.type == 'MemTest':
 exec('system.dma_cntrl%d.dma_sequencer.slave =  
dma_devices.test'

  % i)
 else:
 exec('system.dma_cntrl%d.dma_sequencer.slave =  
dma_device.dma' % i)

+
 dma_cntrl.requestToDir = MessageBuffer(buffer_size=0)
 dma_cntrl.requestToDir.master = ruby_system.network.slave
 dma_cntrl.responseFromDir = MessageBuffer(buffer_size=0)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6879b25c6aabbbc22b0ee8dc9cbfec6399f70daa
Gerrit-Change-Number: 44806
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Use memPools in SE mode only

2021-04-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44845 )


Change subject: sim: Use memPools in SE mode only
..

sim: Use memPools in SE mode only

memPools have been added by:

https://gem5-review.googlesource.com/c/public/gem5/+/42215

and are supposed to be used in SE mode only.
Current code is assuming there is at least one memory which is visible
to the OS/bootloader (conf_table_reported = True). This makes sense
in SE mode as it emulates the OS, but it shouldn't be enforced
in FS baremetal simulations

With this patch we are making sure memPools are used in SE mode
only.

Change-Id: Icebb7dafc18a6fdad0f9b16e5a988270bbebb9eb
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44845
Reviewed-by: Matthew Poremba 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/system.cc
1 file changed, 16 insertions(+), 11 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/system.cc b/src/sim/system.cc
index b4866ba..1bbda6b 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -233,18 +233,20 @@
 }
 #endif

-AddrRangeList memories = physmem.getConfAddrRanges();
-assert(!memories.empty());
-for (const auto  : memories) {
-assert(!memory.interleaved());
-memPools.emplace_back(this, memory.start(), memory.end());
-}
+if (!FullSystem) {
+AddrRangeList memories = physmem.getConfAddrRanges();
+assert(!memories.empty());
+for (const auto  : memories) {
+assert(!memory.interleaved());
+memPools.emplace_back(this, memory.start(), memory.end());
+}

-/*
- * Set freePage to what it was before Gabe Black's page table changes
- * so allocations don't trample the page table entries.
- */
-memPools[0].setFreePage(memPools[0].freePage() + 70);
+/*
+ * Set freePage to what it was before Gabe Black's page table  
changes

+ * so allocations don't trample the page table entries.
+ */
+memPools[0].setFreePage(memPools[0].freePage() + 70);
+}

 // check if the cache line size is a value known to work
 if (_cacheLineSize != 16 && _cacheLineSize != 32 &&
@@ -377,18 +379,21 @@
 Addr
 System::allocPhysPages(int npages, int poolID)
 {
+assert(!FullSystem);
 return memPools[poolID].allocate(npages);
 }

 Addr
 System::memSize(int poolID) const
 {
+assert(!FullSystem);
 return memPools[poolID].totalBytes();
 }

 Addr
 System::freeMemSize(int poolID) const
 {
+assert(!FullSystem);
 return memPools[poolID].freeBytes();
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44845
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icebb7dafc18a6fdad0f9b16e5a988270bbebb9eb
Gerrit-Change-Number: 44845
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: Nightly #291

2021-04-27 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[matthew.poremba] configs: Only add CPU sequencers to piobus

[gabe.black] arch,base,cpu: Move some type aliases into base/types.hh.


--
[...truncated 601.68 KB...]
[ RUN  ] CyclesTest.PrefixDecrement
[   OK ] CyclesTest.PrefixDecrement (0 ms)
[ RUN  ] CyclesTest.InPlaceAddition
[   OK ] CyclesTest.InPlaceAddition (0 ms)
[ RUN  ] CyclesTest.GreaterThanLessThan
[   OK ] CyclesTest.GreaterThanLessThan (0 ms)
[ RUN  ] CyclesTest.AddCycles
[   OK ] CyclesTest.AddCycles (0 ms)
[ RUN  ] CyclesTest.SubtractCycles
[   OK ] CyclesTest.SubtractCycles (0 ms)
[ RUN  ] CyclesTest.ShiftRight
[   OK ] CyclesTest.ShiftRight (0 ms)
[ RUN  ] CyclesTest.ShiftLeft
[   OK ] CyclesTest.ShiftLeft (0 ms)
[ RUN  ] CyclesTest.OutStream
[   OK ] CyclesTest.OutStream (0 ms)
[--] 10 tests from CyclesTest (0 ms total)

[--] 5 tests from MicroPCTest
[ RUN  ] MicroPCTest.CheckMicroPCRomBit
[   OK ] MicroPCTest.CheckMicroPCRomBit (0 ms)
[ RUN  ] MicroPCTest.RomMicroPCTest
[   OK ] MicroPCTest.RomMicroPCTest (0 ms)
[ RUN  ] MicroPCTest.NormalMicroPCTest
[   OK ] MicroPCTest.NormalMicroPCTest (0 ms)
[ RUN  ] MicroPCTest.IsRomMicroPCTest
[   OK ] MicroPCTest.IsRomMicroPCTest (0 ms)
[ RUN  ] MicroPCTest.IsNotRomMicroPCTest
[   OK ] MicroPCTest.IsNotRomMicroPCTest (0 ms)
[--] 5 tests from MicroPCTest (0 ms total)

[--] 4 tests from TypesTest
[ RUN  ] TypesTest.FloatToBits32
[   OK ] TypesTest.FloatToBits32 (0 ms)
[ RUN  ] TypesTest.floatToBits64
[   OK ] TypesTest.floatToBits64 (0 ms)
[ RUN  ] TypesTest.floatsToBitsDoubleInput
[   OK ] TypesTest.floatsToBitsDoubleInput (0 ms)
[ RUN  ] TypesTest.floatsToBitsFloatInput
[   OK ] TypesTest.floatsToBitsFloatInput (0 ms)
[--] 4 tests from TypesTest (0 ms total)

[--] Global test environment tear-down
[==] 19 tests from 3 test suites ran. (1 ms total)
[  PASSED  ] 19 tests.
build/NULL/base/trie.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/base/trie.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 7 tests from 1 test suite.
[--] Global test environment set-up.
[--] 7 tests from TrieTestData
[ RUN  ] TrieTestData.Empty
[   OK ] TrieTestData.Empty (0 ms)
[ RUN  ] TrieTestData.SingleEntry
[   OK ] TrieTestData.SingleEntry (0 ms)
[ RUN  ] TrieTestData.TwoOverlappingEntries
[   OK ] TrieTestData.TwoOverlappingEntries (0 ms)
[ RUN  ] TrieTestData.TwoOverlappingEntriesReversed
[   OK ] TrieTestData.TwoOverlappingEntriesReversed (0 ms)
[ RUN  ] TrieTestData.TwoIndependentEntries
[   OK ] TrieTestData.TwoIndependentEntries (0 ms)
[ RUN  ] TrieTestData.TwoEntries
[   OK ] TrieTestData.TwoEntries (0 ms)
[ RUN  ] TrieTestData.RemovingEntries
[   OK ] TrieTestData.RemovingEntries (0 ms)
[--] 7 tests from TrieTestData (0 ms total)

[--] Global test environment tear-down
[==] 7 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 7 tests.
 [LINK]  -> NULL/sim/proxy_ptr.test.prof
build/NULL/sim/byteswap.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/byteswap.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 8 tests from 1 test suite.
[--] Global test environment set-up.
[--] 8 tests from ByteswapTest
[ RUN  ] ByteswapTest.swap_byte64
[   OK ] ByteswapTest.swap_byte64 (0 ms)
[ RUN  ] ByteswapTest.swap_byte32
[   OK ] ByteswapTest.swap_byte32 (0 ms)
[ RUN  ] ByteswapTest.swap_byte16
[   OK ] ByteswapTest.swap_byte16 (0 ms)
[ RUN  ] ByteswapTest.swap_byte
[   OK ] ByteswapTest.swap_byte (0 ms)
[ RUN  ] ByteswapTest.htog
[   OK ] ByteswapTest.htog (0 ms)
[ RUN  ] ByteswapTest.gtoh
[   OK ] ByteswapTest.gtoh (0 ms)
[ RUN  ] ByteswapTest.betole
[   OK ] ByteswapTest.betole (0 ms)
[ RUN  ] ByteswapTest.letobe
[   OK ] ByteswapTest.letobe (0 ms)
[--] 8 tests from ByteswapTest (0 ms total)

[--] Global test environment tear-down
[==] 8 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 8 tests.
build/NULL/sim/proxy_ptr.test.prof 
--gtest_output=xml:build/NULL/unittests.prof/sim/proxy_ptr.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 6 tests from 1 test suite.
[--] Global test environment set-up.
[--] 6 tests from ProxyPtr
[ RUN  ] ProxyPtr.Clean
[   OK ] ProxyPtr.Clean (0 ms)
[ RUN  ] ProxyPtr.Dirty
[   OK ] ProxyPtr.Dirty (0 ms)
[ RUN  ] ProxyPtr.LoadAndFlush
[   OK ] ProxyPtr.LoadAndFlush (0 ms)
[ RUN  ] ProxyPtr.ConstOperators
[   OK ] ProxyPtr.ConstOperators (0 ms)
[ RUN  ]

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove unused argument from create_mem_intf

2021-04-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42075 )


Change subject: configs: Remove unused argument from create_mem_intf
..

configs: Remove unused argument from create_mem_intf

The number of memory controllers is not actually used by the
create_mem_intf function

Change-Id: I8663b38938de9b62b778679c1bc5c7c6e15a60da
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42075
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/MemConfig.py
M configs/ruby/Ruby.py
2 files changed, 5 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass

Objections:
  Alex Dutu: I would prefer this is not merged as is



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index fa1f084..efd3c1d 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -37,7 +37,7 @@
 from common import ObjectList
 from common import HMC

-def create_mem_intf(intf, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,
+def create_mem_intf(intf, r, i, intlv_bits, intlv_size,
 xor_low_bit):
 """
 Helper function for creating a single memoy controller from the given
@@ -199,7 +199,7 @@
 for i in range(nbr_mem_ctrls):
 if opt_mem_type and (not opt_nvm_type or range_iter % 2 != 0):
 # Create the DRAM interface
-dram_intf = create_mem_intf(intf, r, i, nbr_mem_ctrls,
+dram_intf = create_mem_intf(intf, r, i,
 intlv_bits, intlv_size, opt_xor_low_bit)

 # Set the number of ranks based on the command-line
@@ -223,8 +223,9 @@
 mem_ctrls.append(mem_ctrl)

 elif opt_nvm_type and (not opt_mem_type or range_iter % 2 ==  
0):

-nvm_intf = create_mem_intf(n_intf, r, i, nbr_mem_ctrls,
+nvm_intf = create_mem_intf(n_intf, r, i,
 intlv_bits, intlv_size, opt_xor_low_bit)
+
 # Set the number of ranks based on the command-line
 # options if it was explicitly set
 if issubclass(n_intf, m5.objects.NVMInterface) and \
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 57a5272..0db9d93 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -136,7 +136,7 @@
 for r in system.mem_ranges:
 mem_type = ObjectList.mem_list.get(options.mem_type)
 dram_intf = MemConfig.create_mem_intf(mem_type, r, index,
-options.num_dirs, int(math.log(options.num_dirs, 2)),
+int(math.log(options.num_dirs, 2)),
 intlv_size, options.xor_low_bit)
 if issubclass(mem_type, DRAMInterface):
 mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8663b38938de9b62b778679c1bc5c7c6e15a60da
Gerrit-Change-Number: 42075
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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