[gem5-dev] Change in gem5/gem5[develop]: base: Deprecate the UNIT_* macros.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45559 )



Change subject: base: Deprecate the UNIT_* macros.
..

base: Deprecate the UNIT_* macros.

When setting up a Stats::Group or its subclasses, you can use Unit::*
statif functions which provide an equally brief way to get at the same
thing as the macros, but without all the downsides of macros like
defeating the namespace system. After all, why have a Stats::Units
namespace and then effectively export those names with an
un-namespace-able UNIT_* macro?

Change-Id: I098a7d6951ccc334ae03a3a2e4da6a0f7c1e2263
---
M src/base/stats/group.hh
M src/base/stats/units.hh
2 files changed, 64 insertions(+), 13 deletions(-)



diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 85a77a1..4994ee2 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -96,6 +96,40 @@
 Group =(const Group &) = delete;
 /** @}*/ //end of api_stats

+class Unit
+{
+
+  public:
+static inline Units::Cycle *cycle() { return Units::Cycle::get(); }
+static inline Units::Tick *tick() { return Units::Tick::get(); }
+static inline Units::Second *second() { return  
Units::Second::get(); }

+static inline Units::Bit *bit() { return Units::Bit::get(); }
+static inline Units::Byte *byte() { return Units::Byte::get(); }
+static inline Units::Joule *joule() { return Units::Joule::get(); }
+static inline Units::Volt *volt() { return Units::Volt::get(); }
+static inline Units::DegreeCelsius *
+celsius()
+{
+return Units::DegreeCelsius::get();
+}
+
+template 
+static Units::Rate *
+rate()
+{
+return Units::Rate::get();
+}
+
+static inline Units::Ratio *ratio() { return Units::Ratio::get(); }
+static inline Units::Count *count() { return Units::Count::get(); }
+static inline Units::Watt *watt() { return Units::Watt::get(); }
+static inline Units::Unspecified *
+unspecified()
+{
+return Units::Unspecified::get();
+}
+};
+
 /**
  * Construct a new statistics group.
  *
diff --git a/src/base/stats/units.hh b/src/base/stats/units.hh
index 87e6025..88f93ec 100644
--- a/src/base/stats/units.hh
+++ b/src/base/stats/units.hh
@@ -31,24 +31,41 @@

 #include 

+#include "base/compiler.hh"
 #include "base/cprintf.hh"

 /**
  * Convenience macros to declare the unit of a stat.
  */
-#define UNIT_CYCLE Stats::Units::Cycle::get()
-#define UNIT_TICK Stats::Units::Tick::get()
-#define UNIT_SECOND Stats::Units::Second::get()
-#define UNIT_BIT Stats::Units::Bit::get()
-#define UNIT_BYTE Stats::Units::Byte::get()
-#define UNIT_JOULE Stats::Units::Joule::get()
-#define UNIT_VOLT Stats::Units::Volt::get()
-#define UNIT_CELSIUS Stats::Units::DegreeCelsius::get()
-#define UNIT_RATE(T1, T2) Stats::Units::Rate::get()
-#define UNIT_RATIO Stats::Units::Ratio::get()
-#define UNIT_COUNT Stats::Units::Count::get()
-#define UNIT_WATT Stats::Units::Watt::get()
-#define UNIT_UNSPECIFIED Stats::Units::Unspecified::get()
+#define UNIT_CYCLE GEM5_DEPRECATED_MACRO( \
+UNIT_CYCLE, Stats::Units::Cycle::get(), "Use Unit::cycle()")
+#define UNIT_TICK GEM5_DEPRECATED_MACRO( \
+UNIT_TICK, Stats::Units::Tick::get(), "Use Unit::tick()")
+#define UNIT_SECOND GEM5_DEPRECATED_MACRO( \
+UNIT_SECOND, Stats::Units::Second::get(), "Use Unit::second()")
+#define UNIT_BIT GEM5_DEPRECATED_MACRO( \
+UNIT_BIT, Stats::Units::Bit::get(), "Use Unit::bit()")
+#define UNIT_BYTE GEM5_DEPRECATED_MACRO( \
+UNIT_BYTE, Stats::Units::Byte::get(), "Use Unit::byte()")
+#define UNIT_JOULE GEM5_DEPRECATED_MACRO( \
+UNIT_JOULE, Stats::Units::Joule::get(), "Use Unit::joule()")
+#define UNIT_VOLT GEM5_DEPRECATED_MACRO( \
+UNIT_VOLD, Stats::Units::Volt::get(), "Use Unit::volt()")
+#define UNIT_CELSIUS GEM5_DEPRECATED_MACRO( \
+UNIT_CELSIUS, Stats::Units::DegreeCelsius::get(), \
+"Use Unit::celsius()")
+#define UNIT_RATE(T1, T2) GEM5_DEPRECATED_MACRO( \
+UNIT_RATE(T1, T2), Stats::Units::Rate::get(), \
+"Unit::rate()")
+#define UNIT_RATIO GEM5_DEPRECATED_MACRO( \
+UNIT_RATIO, Stats::Units::Ratio::get(), "Use Unit::ratio()")
+#define UNIT_COUNT GEM5_DEPRECATED_MACRO( \
+UNIT_COUNT, Stats::Units::Count::get(), "Use Unit::count()")
+#define UNIT_WATT GEM5_DEPRECATED_MACRO( \
+UNIT_WATT, Stats::Units::Watt::get(), "Use Unit::watt()")
+#define UNIT_UNSPECIFIED GEM5_DEPRECATED_MACRO( \
+UNIT_UNSPECIFIED, Stats::Units::Unspecified::get(), \
+"Use Unit::unspecified()")

 namespace Stats {


--
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[gem5-dev] Re: Build failed in Jenkins: compiler-checks #72

[Gabe Black via gem5-dev]

On this topic, what do people think about moving up the version of clang?
It would be great to get those __builtin_FILE and __builtin_LINE builtins,
since then we can potentially even un-macro really stubborn things like
panic and warn. Maybe not DPRINTF still, since that expects to call things
like curTick() and name() within the calling context, and I don't think
there's yet a good way to do that (grab the enclosing scope/context)
without a macro.

I think we're less sensitive to the version of clang we're using? I think
using clang is a more proactive choice (I assume), and if you can choose
clang you could just fall back to gcc if yours wasn't new enough, and
with just a little more flexibility might be able to choose a newer one
which is in range.

Gabe

On Fri, May 14, 2021 at 5:32 PM Bobby Bruce  wrote:

> Thanks for the info!
>
> Since it's looking like we'll need to keep GCC 5 around for a little while
> longer, I believe the following patch will fix the compilation issues we're
> facing: https://gem5-review.googlesource.com/c/public/gem5/+/45539
>
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, May 14, 2021 at 11:59 AM Kyle Roarty  wrote:
>
>> As Matt S had mentioned, I'm working on getting ROCm 4 support running
>> and I'm just debugging an issue that's popped up when using it on develop,
>> but it runs on stable. Once I get that figured out, we'll be using Ubuntu
>> 20 in the GCN Docker image instead of Ubuntu 16. We intend for ROCm 4
>> support to be in the gem5 21.1 release.
>>
>> In regards to running in a more "normal" environment, there are a couple
>> of issues with ROCm 4 that I think we would need to resolve first:
>>
>> The first one is gem5-related: ROCr-Runtime uses a currently
>> unimplemented syscall (memfd_create), but you can disable it when compiling
>> from source.
>>
>> The second one is an issue with running ROCm in a simulator: ROCclr will
>> compile some blit kernels on-the-fly whenever you run a program. It takes
>> forever, and it crashes at the end in gem5 anyway. Currently I just return
>> when that function is called, and for the programs I've run there haven't
>> been any ill effects.
>>
>> There's also a difference in how pre-built/cached kernels are handled in
>> MIOpen (stored in database vs directories), which we can also change when
>> compiling from source.
>>
>> I've also had issues with trying to install parts of ROCm from source and
>> then subsequent parts of ROCm from .deb packages or apt. That's one of the
>> reasons for the complexity in the GCN dockerfile. If that issue has gone
>> away with ROCm 4 (I haven't tried yet) that would simplify the dockerfile
>> greatly as we would only need to build ROCclr from source, assuming
>> memfd_create is implemented, and everything else could be installed from
>> apt.
>>
>> Kyle
>> --
>> *From:* gem5-dev@gem5.org 
>> *Sent:* Friday, May 14, 2021 1:07 PM
>> *To:* gem5 Developer List 
>> *Cc:* Matt Sinclair ; Poremba, Matthew <
>> matthew.pore...@amd.com>; Gabe Black ; Bobby Bruce
>> 
>> *Subject:* [gem5-dev] Re: Build failed in Jenkins: compiler-checks #72
>>
>> To clarify the docker situation, here's a quick rundown of how docker is
>> used with gem5: Docker is the fallback for people who are using
>> outdated/weird/unsupported systems and want to use gem5. It's also handy
>> for testing as we can quickly spin up different environments (different
>> OS's, different compilers, different dependencies) and see how gem5
>> performs. Docker will run in all major OS's (Mac, Windows, Linux). As long
>> as you can run docker, you should be able to build/run gem5. One of my
>> problems with docker is its CLI is needlessly verbose and confusing. You
>> need to specify way too much boilerplate stuff to get it going. However we
>> have provided some documentation here for gem5 users:
>> http://www.gem5.org/documentation/general_docs/building#docker. We're in
>> charge of the images and can change them as requirements change.
>>
>> In respect to the GPU/GCN3 stuff: This is a special case. The environment
>> needed to compile x86_gcn3 and run GCN3 is specific to the point that it'd
>> be unreasonable to ask a user to set it all up just to run some GPU
>> simulations (see the Dockerfile here to get an idea:
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/dockerfiles/gcn-gpu/Dockerfile).
>> So, for this, we recommend always compiling and running within docker, even
>> if you're using a system that can build/run gem5 without virtualization.
>>
>> I did not realize the GCN3 docker image was using GCC 5, so that is
>> problematic. I also think it using Ubuntu 16.04 isn't a good idea either as
>> we're not really supporting that anymore.  Given GCN3 is already patching a
>> lot of library code to get this all working, is it possible to patch ROCm
>> to work with newer compilers?
>>
>> Also, 

[gem5-dev] Re: Build failed in Jenkins: compiler-checks #72

[Bobby Bruce via gem5-dev]

Thanks for the info!

Since it's looking like we'll need to keep GCC 5 around for a little while
longer, I believe the following patch will fix the compilation issues we're
facing: https://gem5-review.googlesource.com/c/public/gem5/+/45539

Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, May 14, 2021 at 11:59 AM Kyle Roarty  wrote:

> As Matt S had mentioned, I'm working on getting ROCm 4 support running and
> I'm just debugging an issue that's popped up when using it on develop, but
> it runs on stable. Once I get that figured out, we'll be using Ubuntu 20 in
> the GCN Docker image instead of Ubuntu 16. We intend for ROCm 4 support to
> be in the gem5 21.1 release.
>
> In regards to running in a more "normal" environment, there are a couple
> of issues with ROCm 4 that I think we would need to resolve first:
>
> The first one is gem5-related: ROCr-Runtime uses a currently unimplemented
> syscall (memfd_create), but you can disable it when compiling from source.
>
> The second one is an issue with running ROCm in a simulator: ROCclr will
> compile some blit kernels on-the-fly whenever you run a program. It takes
> forever, and it crashes at the end in gem5 anyway. Currently I just return
> when that function is called, and for the programs I've run there haven't
> been any ill effects.
>
> There's also a difference in how pre-built/cached kernels are handled in
> MIOpen (stored in database vs directories), which we can also change when
> compiling from source.
>
> I've also had issues with trying to install parts of ROCm from source and
> then subsequent parts of ROCm from .deb packages or apt. That's one of the
> reasons for the complexity in the GCN dockerfile. If that issue has gone
> away with ROCm 4 (I haven't tried yet) that would simplify the dockerfile
> greatly as we would only need to build ROCclr from source, assuming
> memfd_create is implemented, and everything else could be installed from
> apt.
>
> Kyle
> --
> *From:* gem5-dev@gem5.org 
> *Sent:* Friday, May 14, 2021 1:07 PM
> *To:* gem5 Developer List 
> *Cc:* Matt Sinclair ; Poremba, Matthew <
> matthew.pore...@amd.com>; Gabe Black ; Bobby Bruce <
> bbr...@ucdavis.edu>
> *Subject:* [gem5-dev] Re: Build failed in Jenkins: compiler-checks #72
>
> To clarify the docker situation, here's a quick rundown of how docker is
> used with gem5: Docker is the fallback for people who are using
> outdated/weird/unsupported systems and want to use gem5. It's also handy
> for testing as we can quickly spin up different environments (different
> OS's, different compilers, different dependencies) and see how gem5
> performs. Docker will run in all major OS's (Mac, Windows, Linux). As long
> as you can run docker, you should be able to build/run gem5. One of my
> problems with docker is its CLI is needlessly verbose and confusing. You
> need to specify way too much boilerplate stuff to get it going. However we
> have provided some documentation here for gem5 users:
> http://www.gem5.org/documentation/general_docs/building#docker. We're in
> charge of the images and can change them as requirements change.
>
> In respect to the GPU/GCN3 stuff: This is a special case. The environment
> needed to compile x86_gcn3 and run GCN3 is specific to the point that it'd
> be unreasonable to ask a user to set it all up just to run some GPU
> simulations (see the Dockerfile here to get an idea:
> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/dockerfiles/gcn-gpu/Dockerfile).
> So, for this, we recommend always compiling and running within docker, even
> if you're using a system that can build/run gem5 without virtualization.
>
> I did not realize the GCN3 docker image was using GCC 5, so that is
> problematic. I also think it using Ubuntu 16.04 isn't a good idea either as
> we're not really supporting that anymore.  Given GCN3 is already patching a
> lot of library code to get this all working, is it possible to patch ROCm
> to work with newer compilers?
>
> Also, this may come across as a cheeky question (but I don't mean it to
> be): Is there anything in the pipeline to have the X86_GCN3 build run in a
> more vanilla environment? E.g., build and run in Ubuntu 18.04 with just a
> few APT installs? I would be in strong support of such a move. It'd
> simplify a lot.
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Thu, May 13, 2021 at 5:00 PM Gabe Black via gem5-dev 
> wrote:
>
> So, is this something *inside* the simulation which needs to be compiled
> with a particular version of gcc, or is it a part of the simulator itself?
> I was imagining the former, but if it's the later I see why it's
> problematic.
>
> How tightly coupled is this ROCm code base? Is it just a matter of
> updating weird gcc-isms in the code, or does it (for instance) actually use
> gcc machinery and 

[gem5-dev] Change in gem5/gem5[develop]: base: Add GEM5_DEPRECATED_ENUM_VAL

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45539 )



Change subject: base: Add GEM5_DEPRECATED_ENUM_VAL
..

base: Add GEM5_DEPRECATED_ENUM_VAL

This deperecation enum works exactly the same way as GEM5_DEPRECATED
but will not expand if using GCC <6, as enum value deprecation was only
introduced in GCC 6.

Change-Id: I64fcaca0d79a353da805642e021ec1cb101cfa0e
---
M src/base/compiler.hh
M src/sim/aux_vector.hh
2 files changed, 13 insertions(+), 3 deletions(-)



diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 4ea0dbb..58e5a6f 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -116,6 +116,16 @@
 // Mark a c++ declaration as deprecated, with a message explaining what to  
do

 // to update to a non-deprecated alternative.
 #  define GEM5_DEPRECATED(message) [[gnu::deprecated(message)]]
+// Mark a C++ emum value as deprecated, with a message explaining what to  
do
+// to update to a non-deprecated alternative. This wraps GEM5_DEPRECATED  
but

+// is guarded by a preprocessor if directive to ensure it is not included
+// when compiled in GCC < 6, as deprecation of enum values was introduced  
in

+// GCC 6.
+#  if __GNUC__ < 6
+#define GEM5_DEPRECATED_ENUM_VAL(message)
+#  else
+#define GEM5_DEPRECATED_ENUM_VAL(message) GEM5_DEPRECATED(message)
+#  endif
 // Mark an expression-like macro as deprecated by wrapping it in some code
 // which declares and uses a deprecated variable with the same name as the
 // macro. The wrapping macro evaluates to the same thing as the original  
macro.

diff --git a/src/sim/aux_vector.hh b/src/sim/aux_vector.hh
index 55a4a05..30b 100644
--- a/src/sim/aux_vector.hh
+++ b/src/sim/aux_vector.hh
@@ -98,8 +98,8 @@
 } // namespace gem5

 #define GEM5_DEPRECATE_AT(NAME, name) M5_AT_##NAME \
-GEM5_DEPRECATED("Replace M5_AT_" #NAME " with gem5::auxv::" #name) = \
-gem5::auxv::name
+GEM5_DEPRECATED_ENUM_VAL(\
+"Replace M5_AT_" #NAME " with gem5::auxv::" #name) =  
gem5::auxv::name


 enum AuxiliaryVectorType
 {
@@ -122,7 +122,7 @@
 GEM5_DEPRECATE_AT(HWCAP, Hwcap),
 GEM5_DEPRECATE_AT(CLKTCK, Clktck),
 GEM5_DEPRECATE_AT(SECURE, Secure),
-M5_BASE_PLATFORM GEM5_DEPRECATED(
+M5_BASE_PLATFORM GEM5_DEPRECATED_ENUM_VAL(
 "Replace M5_BASE_PLATFORM with gem5::auxv::BasePlatform") =
 gem5::auxv::BasePlatform,
 GEM5_DEPRECATE_AT(RANDOM, Random),

--
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https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I64fcaca0d79a353da805642e021ec1cb101cfa0e
Gerrit-Change-Number: 45539
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Jenkins build is back to normal : nightly #311

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[gem5-dev] Re: Build failed in Jenkins: compiler-checks #72

[Kyle Roarty via gem5-dev]

As Matt S had mentioned, I'm working on getting ROCm 4 support running and I'm 
just debugging an issue that's popped up when using it on develop, but it runs 
on stable. Once I get that figured out, we'll be using Ubuntu 20 in the GCN 
Docker image instead of Ubuntu 16. We intend for ROCm 4 support to be in the 
gem5 21.1 release.

In regards to running in a more "normal" environment, there are a couple of 
issues with ROCm 4 that I think we would need to resolve first:

The first one is gem5-related: ROCr-Runtime uses a currently unimplemented 
syscall (memfd_create), but you can disable it when compiling from source.

The second one is an issue with running ROCm in a simulator: ROCclr will 
compile some blit kernels on-the-fly whenever you run a program. It takes 
forever, and it crashes at the end in gem5 anyway. Currently I just return when 
that function is called, and for the programs I've run there haven't been any 
ill effects.

There's also a difference in how pre-built/cached kernels are handled in MIOpen 
(stored in database vs directories), which we can also change when compiling 
from source.

I've also had issues with trying to install parts of ROCm from source and then 
subsequent parts of ROCm from .deb packages or apt. That's one of the reasons 
for the complexity in the GCN dockerfile. If that issue has gone away with ROCm 
4 (I haven't tried yet) that would simplify the dockerfile greatly as we would 
only need to build ROCclr from source, assuming memfd_create is implemented, 
and everything else could be installed from apt.

Kyle

From: gem5-dev@gem5.org 
Sent: Friday, May 14, 2021 1:07 PM
To: gem5 Developer List 
Cc: Matt Sinclair ; Poremba, Matthew 
; Gabe Black ; Bobby Bruce 

Subject: [gem5-dev] Re: Build failed in Jenkins: compiler-checks #72

To clarify the docker situation, here's a quick rundown of how docker is used 
with gem5: Docker is the fallback for people who are using 
outdated/weird/unsupported systems and want to use gem5. It's also handy for 
testing as we can quickly spin up different environments (different OS's, 
different compilers, different dependencies) and see how gem5 performs. Docker 
will run in all major OS's (Mac, Windows, Linux). As long as you can run 
docker, you should be able to build/run gem5. One of my problems with docker is 
its CLI is needlessly verbose and confusing. You need to specify way too much 
boilerplate stuff to get it going. However we have provided some documentation 
here for gem5 users: 
http://www.gem5.org/documentation/general_docs/building#docker. We're in charge 
of the images and can change them as requirements change.

In respect to the GPU/GCN3 stuff: This is a special case. The environment 
needed to compile x86_gcn3 and run GCN3 is specific to the point that it'd be 
unreasonable to ask a user to set it all up just to run some GPU simulations 
(see the Dockerfile here to get an idea: 
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/dockerfiles/gcn-gpu/Dockerfile).
 So, for this, we recommend always compiling and running within docker, even if 
you're using a system that can build/run gem5 without virtualization.

I did not realize the GCN3 docker image was using GCC 5, so that is 
problematic. I also think it using Ubuntu 16.04 isn't a good idea either as 
we're not really supporting that anymore.  Given GCN3 is already patching a lot 
of library code to get this all working, is it possible to patch ROCm to work 
with newer compilers?

Also, this may come across as a cheeky question (but I don't mean it to be): Is 
there anything in the pipeline to have the X86_GCN3 build run in a more vanilla 
environment? E.g., build and run in Ubuntu 18.04 with just a few APT installs? 
I would be in strong support of such a move. It'd simplify a lot.

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Thu, May 13, 2021 at 5:00 PM Gabe Black via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
So, is this something *inside* the simulation which needs to be compiled with a 
particular version of gcc, or is it a part of the simulator itself? I was 
imagining the former, but if it's the later I see why it's problematic.

How tightly coupled is this ROCm code base? Is it just a matter of updating 
weird gcc-isms in the code, or does it (for instance) actually use gcc 
machinery and need literal porting to a different version of that machinery?

Gabe

On Thu, May 13, 2021 at 4:56 PM Matt Sinclair 
mailto:sincl...@cs.wisc.edu>> wrote:
This is actually what we do right now — we have a docker setup for Ubuntu 16 
and the GPU experiments are strongly recommended to be run inside it.  My 
concern though is if we deprecate support for gcc 5 before the ROCm 4 support 
is pushed, the codebases would diverge, because all the cool new features you 
mentioned would not be compatible with the gcc version we have to run in the 
current docker 

[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: sim: Fix Temperature class

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44745 )


Change subject: sim: Fix Temperature class
..

sim: Fix Temperature class

* Adding __str__ method: To fix its printing on config.ini
(Replacing  with the Temperature value)

* Replacing "fromKelvin" with from_kelvin
(that's how pybind exports it)

* Fixing config_value to allow JSON serialization
(JIRA: https://gem5.atlassian.net/browse/GEM5-951)

Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44167
Reviewed-by: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
(cherry picked from commit 6cb9c3e87fa8034122310613079ae4f058f93233)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44745
Maintainer: Jason Lowe-Power 
---
M src/python/m5/params.py
1 file changed, 5 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index d2366f6..78be6f6 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1705,12 +1705,15 @@
 self.__init__(value)
 return value

+def __str__(self):
+return str(self.value)
+
 def getValue(self):
 from _m5.core import Temperature
-return Temperature.fromKelvin(self.value)
+return Temperature.from_kelvin(self.value)

 def config_value(self):
-return self
+return self.value

 @classmethod
 def cxx_predecls(cls, code):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: minor-release-staging-v21-0-1
Gerrit-Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2
Gerrit-Change-Number: 44745
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: python,misc: Fix develop resources URL to v21-0

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/44725 )


Change subject: python,misc: Fix develop resources URL to v21-0
..

python,misc: Fix develop resources URL to v21-0

This was incorrectly kept as `http://dist.gem5.org/dist/develop` in the
v21.0.0 release of gem5. The `dist/develop` directory is used by the
develop branch, not by gem5 releases. This change updates the URL to
point towards the currect v21-0 branch, which will remain stable and
contain resoruces always compatible with the v21-0 release.

Change-Id: I5d9a9497cebffa91f08be253f1637e11e0d5e62c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44725
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M ext/testlib/configuration.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index 1fffab4..18bebdd 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -213,7 +213,7 @@
   os.pardir,
   os.pardir))
 defaults.result_path = os.path.join(os.getcwd(), 'testing-results')
-defaults.resource_url = 'http://dist.gem5.org/dist/develop'
+defaults.resource_url = 'http://dist.gem5.org/dist/v21-0'
 defaults.resource_path =  
os.path.abspath(os.path.join(defaults.base_dir,

 'tests',
 'gem5',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: minor-release-staging-v21-0-1
Gerrit-Change-Id: I5d9a9497cebffa91f08be253f1637e11e0d5e62c
Gerrit-Change-Number: 44725
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base,tests: Fix debug.cc tests to reflect new API changes

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45480 )


Change subject: base,tests: Fix debug.cc tests to reflect new API changes
..

base,tests: Fix debug.cc tests to reflect new API changes

Due to simplifications in how the debug flag is enabled (here:
https://gem5-review.googlesource.com/c/public/gem5/+/45007), the
debug.cc.test tests were failing when compiled to .fast (`scons
build/NULL/unittests.fast`). This patch fixes the tests to work with
this new API.

Change-Id: Ifd49f698dcc9e5d2a81d4b4a9363b82dd8a91a97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45480
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/debug.test.cc
1 file changed, 24 insertions(+), 22 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/debug.test.cc b/src/base/debug.test.cc
index 69ac095..b0f3a5d 100644
--- a/src/base/debug.test.cc
+++ b/src/base/debug.test.cc
@@ -84,13 +84,13 @@
 flag.enable();
 ASSERT_FALSE(flag.tracing());
 Debug::Flag::globalEnable();
-ASSERT_TRUE(flag.tracing());
+ASSERT_TRUE(!TRACING_ON || flag.tracing());

 // Verify that the global enabler works
 Debug::Flag::globalDisable();
 ASSERT_FALSE(flag.tracing());
 Debug::Flag::globalEnable();
-ASSERT_TRUE(flag.tracing());
+ASSERT_TRUE(!TRACING_ON || flag.tracing());

 // Test disabling the flag with global enabled
 flag.disable();
@@ -119,10 +119,10 @@
 ASSERT_FALSE(flag.tracing());
 Debug::Flag::globalEnable();
 for (auto  : flag.kids()) {
-ASSERT_TRUE(kid->tracing());
+ASSERT_TRUE(!TRACING_ON || kid->tracing());
 }
-ASSERT_TRUE(flag_a.tracing());
-ASSERT_TRUE(flag_b.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_b.tracing());

 // Test disabling the flag with global enabled
 flag.disable();
@@ -163,22 +163,22 @@
 ASSERT_FALSE(flag_b.tracing());
 ASSERT_FALSE(flag.tracing());
 flag_a.enable();
-ASSERT_TRUE(flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
 ASSERT_FALSE(flag_b.tracing());
 ASSERT_FALSE(flag.tracing());

 // Test that enabling both flags enables the compound flag
-ASSERT_TRUE(flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
 ASSERT_FALSE(flag_b.tracing());
 ASSERT_FALSE(flag.tracing());
 flag_b.enable();
-ASSERT_TRUE(flag_a.tracing());
-ASSERT_TRUE(flag_b.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_b.tracing());

 // Test that disabling one of the flags disables the compound flag
 flag_a.disable();
 ASSERT_FALSE(flag_a.tracing());
-ASSERT_TRUE(flag_b.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_b.tracing());
 ASSERT_FALSE(flag.tracing());
 }

@@ -195,11 +195,11 @@
 EXPECT_TRUE(flag = Debug::findFlag("FlagFindFlagTestA"));
 ASSERT_FALSE(flag_a.tracing());
 flag->enable();
-ASSERT_TRUE(flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
 EXPECT_TRUE(flag = Debug::findFlag("FlagFindFlagTestB"));
 ASSERT_FALSE(flag_b.tracing());
 flag->enable();
-ASSERT_TRUE(flag_b.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_b.tracing());

 // Search for a non-existent flag
 EXPECT_FALSE(Debug::findFlag("FlagFindFlagTestC"));
@@ -216,7 +216,7 @@
 // enabled too
 ASSERT_FALSE(flag_a.tracing());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestA", true));
-ASSERT_TRUE(flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestA", false));
 ASSERT_FALSE(flag_a.tracing());

@@ -225,7 +225,7 @@
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestB", false));
 ASSERT_FALSE(flag_b.tracing());
 EXPECT_TRUE(Debug::changeFlag("FlagChangeFlagTestB", true));
-ASSERT_TRUE(flag_b.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_b.tracing());

 // Change a non-existent flag
 ASSERT_FALSE(Debug::changeFlag("FlagChangeFlagTestC", true));
@@ -241,7 +241,7 @@
 // Enable and disable a flag
 ASSERT_FALSE(flag_a.tracing());
 setDebugFlag("FlagSetClearDebugFlagTestA");
-ASSERT_TRUE(flag_a.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_a.tracing());
 clearDebugFlag("FlagSetClearDebugFlagTestA");
 ASSERT_FALSE(flag_a.tracing());

@@ -250,7 +250,7 @@
 clearDebugFlag("FlagSetClearDebugFlagTestB");
 ASSERT_FALSE(flag_b.tracing());
 setDebugFlag("FlagSetClearDebugFlagTestB");
-ASSERT_TRUE(flag_b.tracing());
+ASSERT_TRUE(!TRACING_ON || flag_b.tracing());

 // Change a non-existent flag
 setDebugFlag("FlagSetClearDebugFlagTestC");
@@ -295,10 +295,12 @@
  

[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Fixing .fast compilation for gcn3

[Bobby R. Bruce (Gerrit) via gem5-dev]

Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45481 )


Change subject: arch-gcn3: Fixing .fast compilation for gcn3
..

arch-gcn3: Fixing .fast compilation for gcn3

DPRINTF was altered here:
https://gem5-review.googlesource.com/c/public/gem5/+/44988.
This change results in DPRINTFs always compiling. As such, the
variables decladed within NDEBUG ifdefs, and later used in DPRINTFs,
cause an error when compiling .fast. In this patch the NDEBUG ifdefs
have been removed.

Change-Id: I54992cfe152c84b265e64e1389bf2656c95ba42e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45481
Reviewed-by: Matthew Poremba 
Reviewed-by: Matt Sinclair 
Maintainer: Matthew Poremba 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/gpu_tlb.cc
1 file changed, 3 insertions(+), 4 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index f0afd827..dfe9a48 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -960,10 +960,10 @@

 Process *p = sender_state->tc->getProcessPtr();
 Addr vaddr = pkt->req->getVaddr();
-#ifndef NDEBUG
+
 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
 assert(alignedVaddr == virtPageAddr);
-#endif
+
 const EmulationPageTable::Entry *pte =  
p->pTable->lookup(vaddr);

 if (!pte && sender_state->tlbMode != BaseTLB::Execute &&
 p->fixupFault(vaddr)) {
@@ -1164,10 +1164,9 @@
 Process *p = tc->getProcessPtr();

 Addr vaddr = pkt->req->getVaddr();
-#ifndef NDEBUG
+
 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
 assert(alignedVaddr == virt_page_addr);
-#endif

 const EmulationPageTable::Entry *pte =
 p->pTable->lookup(vaddr);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I54992cfe152c84b265e64e1389bf2656c95ba42e
Gerrit-Change-Number: 45481
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: compiler-checks #72

[Bobby Bruce via gem5-dev]

To clarify the docker situation, here's a quick rundown of how docker is
used with gem5: Docker is the fallback for people who are using
outdated/weird/unsupported systems and want to use gem5. It's also handy
for testing as we can quickly spin up different environments (different
OS's, different compilers, different dependencies) and see how gem5
performs. Docker will run in all major OS's (Mac, Windows, Linux). As long
as you can run docker, you should be able to build/run gem5. One of my
problems with docker is its CLI is needlessly verbose and confusing. You
need to specify way too much boilerplate stuff to get it going. However we
have provided some documentation here for gem5 users:
http://www.gem5.org/documentation/general_docs/building#docker. We're in
charge of the images and can change them as requirements change.

In respect to the GPU/GCN3 stuff: This is a special case. The environment
needed to compile x86_gcn3 and run GCN3 is specific to the point that it'd
be unreasonable to ask a user to set it all up just to run some GPU
simulations (see the Dockerfile here to get an idea:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/util/dockerfiles/gcn-gpu/Dockerfile).
So, for this, we recommend always compiling and running within docker, even
if you're using a system that can build/run gem5 without virtualization.

I did not realize the GCN3 docker image was using GCC 5, so that is
problematic. I also think it using Ubuntu 16.04 isn't a good idea either as
we're not really supporting that anymore.  Given GCN3 is already patching a
lot of library code to get this all working, is it possible to patch ROCm
to work with newer compilers?

Also, this may come across as a cheeky question (but I don't mean it to
be): Is there anything in the pipeline to have the X86_GCN3 build run in a
more vanilla environment? E.g., build and run in Ubuntu 18.04 with just a
few APT installs? I would be in strong support of such a move. It'd
simplify a lot.

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Thu, May 13, 2021 at 5:00 PM Gabe Black via gem5-dev 
wrote:

> So, is this something *inside* the simulation which needs to be compiled
> with a particular version of gcc, or is it a part of the simulator itself?
> I was imagining the former, but if it's the later I see why it's
> problematic.
>
> How tightly coupled is this ROCm code base? Is it just a matter of
> updating weird gcc-isms in the code, or does it (for instance) actually use
> gcc machinery and need literal porting to a different version of that
> machinery?
>
> Gabe
>
> On Thu, May 13, 2021 at 4:56 PM Matt Sinclair 
> wrote:
>
>> This is actually what we do right now — we have a docker setup for Ubuntu
>> 16 and the GPU experiments are strongly recommended to be run inside it.
>> My concern though is if we deprecate support for gcc 5 before the ROCm 4
>> support is pushed, the codebases would diverge, because all the cool new
>> features you mentioned would not be compatible with the gcc version we have
>> to run in the current docker setup.
>>
>> Again, my hope is this is a short-term issue though, so it may be moot.
>>
>> Matt
>>
>> On Thu, May 13, 2021 at 6:51 PM Gabe Black via gem5-dev <
>> gem5-dev@gem5.org> wrote:
>>
>>> I'm pretty clueless as far as how the GPU code is built, but would it be
>>> possible to build it in a docker or something with a separate older
>>> compiler?
>>>
>>> Would it be reasonable to provide a docker for gem5 building in general,
>>> so we can decouple from ye-olde versions of RedHat? In the past Jason
>>> and/or Bobby have sent me a command line which builds gem5 inside of a
>>> docker with the source bind mounted, and that seemed to work well. Does
>>> that come with other baggage or limitations which make that infeasible? For
>>> instance, I don't think this is true, but does it not work on Mac? I don't
>>> think we should *require* building inside a docker, but that could give
>>> people working on old systems a solution if we move to more up to date
>>> tools.
>>>
>>> Gabe
>>>
>>> On Thu, May 13, 2021 at 4:45 PM Matt Sinclair 
>>> wrote:
>>>
 Just to be clear: Kyle R has ROCm 4.0 working locally on stable (but
 not develop), and our plan is to push the 4.0 support once Kyle’s current
 set of patches (which have a few more to be pushed still) are committed and
 we debug the issues with develop.  So, in theory, we’re talking about a
 fairly short term need to keep gcc 5.

 Matt

 On Thu, May 13, 2021 at 6:42 PM Matt Sinclair 
 wrote:

> At least for the moment, the GPU support relies on gcc 5.4, since the
> version of AMD’s ROCm stack that is supported requires 5.4 for the ML
> libraries.  We are working on updating both FS and SE mode support for
> newer versions of ROCm, which work with newer versions of gcc, but I would
> need to dig to figure out what the minimum gcc version 

[gem5-dev] Re: software floating point library(s)

[Jason Lowe-Power via gem5-dev]

I think we can use softfloat for everything now. Years ago, softfloat
wasn't BSD. So, we somewhat rolled our own to get the Arm instructions
working, but it wasn't comprehensive. Since softfloat was added in the past
few months, no one has yet migrated the old code. As far as I know, this
would be a safe thing to do.

Cheers,
Jason

On Fri, May 14, 2021 at 4:15 AM Gabe Black via gem5-dev 
wrote:

> Hi folks. I've taken a little time recently to go macro hunting, and while
> doing that I noticed what I think are three different software floating
> point implementations in gem5. There is ext/fputils which has support for
> 80 bit floats, arch/arm/insts/fplib.hh and .cc which I'm assuming ARM uses,
> and ext/softfloat which RISCV uses.
>
> I can't think of a good reason for us to need three different solutions to
> the same problem. Is there a good reason for this, or was each just not
> aware of the others? Can we fold one (or two) of these into a preferred
> implementation and get rid of the extra(s)?
>
> Gabe
> ___
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: When an inst generates a fault, return it immediately.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45520 )



Change subject: arch-riscv: When an inst generates a fault, return it  
immediately.

..

arch-riscv: When an inst generates a fault, return it immediately.

When a fault is generated, it needs to be returned, and nothing else
should be done. There's no point in keeping it around and having to
check over and over if there was a fault and if other parts of the
execute functions should be skipped.

This simplifies the logic a bit which should speed up execution, and
also makes life easier for the compiler since behavior is obvious and
doesn't have to be deduced from possible data values and ifs.

Change-Id: I2004c7d22ac6222e1ef2acb51d49b4eb2e60b144
---
M src/arch/riscv/fp_inst.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
8 files changed, 195 insertions(+), 324 deletions(-)



diff --git a/src/arch/riscv/fp_inst.hh b/src/arch/riscv/fp_inst.hh
index 3a1e2d6..604c016 100644
--- a/src/arch/riscv/fp_inst.hh
+++ b/src/arch/riscv/fp_inst.hh
@@ -34,10 +34,10 @@
 #define  
RM_REQUIRED \
 uint_fast8_t rm =  
ROUND_MODE;   \
 uint_fast8_t frm =  
xc->readMiscReg(MISCREG_FRM);\
-if (rm ==  
7) \
+if (rm ==  
7)\
 rm =  
frm;   \
-if (rm >  
4)  \
-fault = std::make_shared("RM fault",  
machInst);\
+if (rm >  
4) \
+return std::make_shared("RM fault",  
machInst);\
 softfloat_roundingMode =  
rm;\


 #endif // __ARCH_RISCV_FP_INST_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f4bdb7..823698c 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -43,7 +43,7 @@
   CIMM8<5:2> << 6;
 }}, {{
 if (machInst == 0)
-fault = std::make_shared("zero  
instruction",
+return std::make_shared("zero  
instruction",

machInst);
 Rp2 = sp + imm;
 }}, uint64_t);
@@ -53,7 +53,7 @@
 }}, {{
 STATUS status = xc->readMiscReg(MISCREG_STATUS);
 if (status.fs == FPUStatus::OFF)
-fault = std::make_shared("FPU is  
off",

+return std::make_shared("FPU is off",
machInst);

 Fp2_bits = Mem;
@@ -83,7 +83,7 @@
 }}, {{
 STATUS status = xc->readMiscReg(MISCREG_STATUS);
 if (status.fs == FPUStatus::OFF)
-fault = std::make_shared("FPU is  
off",

+return std::make_shared("FPU is off",
machInst);

 Mem = Fp2_bits;
@@ -117,11 +117,12 @@
 }}, {{
 if ((RC1 == 0) != (imm == 0)) {
 if (RC1 == 0) {
-fault = std::make_shared(
+return std::make_shared(
 "source reg x0", machInst);
-} else // imm == 0
-fault = std::make_shared(
+} else { // imm == 0
+return std::make_shared(
 "immediate = 0", machInst);
+}
 }
 Rc1_sd = Rc1_sd + imm;
 }});
@@ -131,7 +132,7 @@
 imm |= ~((uint64_t)0x1F);
 }}, {{
 if (RC1 == 0) {
-fault = std::make_shared(
+return std::make_shared(
 "source reg x0", machInst);
 }
 Rc1_sd = (int32_t)Rc1_sd + imm;
@@ -142,7 +143,7 @@
 imm |= ~((uint64_t)0x1F);
 }}, {{
 if (RC1 == 0) {
-fault = std::make_shared(
+return std::make_shared(
 "source reg x0", machInst);
 }
 Rc1_sd = imm;
@@ -157,7 +158,7 @@
 imm |= ~((int64_t)0x1FF);
 }}, {{
 if (imm == 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Split up read/write and read only CSR instructions.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45522 )



Change subject: arch-riscv: Split up read/write and read only CSR  
instructions.

..

arch-riscv: Split up read/write and read only CSR instructions.

If RS1 is X0 or if using an immediate and the value encoded in the RS1
field which is used as the immediate is zero, then the CSR is not
actually written. It doesn't matter whether the register value would
change or not.

Also, if an instruction wants to write to the CSR, the manual does not
say anything about whether or not the register value changes. If a
register is read only, attempting to write it with *any* value should be
illegal.

Change-Id: Ic876eff0fc0c7e25a40ba9213e3c3e49bfa7a33e
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 94 insertions(+), 46 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index e0b270b..dba460f 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -274,7 +274,7 @@
 }
 }};

-def template CSRExecute {{
+def template CSRExecuteRo {{
 Fault
 %(class_name)s::execute(ExecContext *xc,
 Trace::InstRecord *traceData) const
@@ -287,8 +287,6 @@
 %(op_decl)s;
 %(op_rd)s;

-RegVal data, olddata;
-
 switch (csr) {
   case CSR_SATP: {
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
@@ -313,55 +311,91 @@
 break;
 }

+RegVal data;
 if (csr == CSR_FCSR) {
-olddata = xc->readMiscReg(MISCREG_FFLAGS) |
+data = xc->readMiscReg(MISCREG_FFLAGS) |
+   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+} else {
+data = xc->readMiscReg(midx);
+}
+
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);
+
+%(code)s;
+%(op_wb)s;
+
+return NoFault;
+}
+}};
+
+def template CSRExecuteRw {{
+Fault
+%(class_name)s::execute(ExecContext *xc,
+Trace::InstRecord *traceData) const
+{
+if (!valid) {
+return std::make_shared(
+csprintf("Illegal CSR index %#x\n", csr), machInst);
+}
+if (bits(csr, 11, 10) == 0x3) {
+return std::make_shared(
+csprintf("CSR %s is read-only\n", csrName), machInst);
+}
+
+%(op_decl)s;
+%(op_rd)s;
+
+switch (csr) {
+  case CSR_SATP: {
+auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
+return std::make_shared(
+"SATP access in user mode or with TVM enabled\n",
+machInst);
+}
+break;
+  }
+  case CSR_MSTATUS: {
+auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+if (pm != PrivilegeMode::PRV_M) {
+return std::make_shared(
+"MSTATUS is only accessibly in machine mode\n",
+machInst);
+}
+break;
+  }
+  default:
+break;
+}
+
+RegVal data;
+if (csr == CSR_FCSR) {
+data = xc->readMiscReg(MISCREG_FFLAGS) |
   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
 } else {
-olddata = xc->readMiscReg(midx);
+data = xc->readMiscReg(midx);
 }
-auto olddata_all = olddata;

-olddata &= maskVal;
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, olddata);
-data = olddata;
+RegVal original = data;
+
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data &  
maskVal);


 %(code)s;

-data &= maskVal;
-if (data != olddata) {
-if (bits(csr, 11, 10) == 0x3) {
-return std::make_shared(
-csprintf("CSR %s is read-only\n", csrName),  
machInst);

-}
-auto newdata_all = data;
-// We must keep those original bits not in mask.
-// olddata and data only contain the bits visable
-// in current privilige level.
-newdata_all = (olddata_all & ~maskVal) | data;
-DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",
-newdata_all, csrName);
-switch (csr) {
-  case CSR_FCSR:
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-break;
-  case CSR_MIP: case CSR_MIE:
-  case CSR_SIP: case CSR_SIE:
-  case CSR_UIP: case CSR_UIE:
-  case 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Use operands instead of (read|set)MiscReg for FP insts.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45526 )



Change subject: arch-riscv: Use operands instead of (read|set)MiscReg for  
FP insts.

..

arch-riscv: Use operands instead of (read|set)MiscReg for FP insts.

Change-Id: I9f614225cedcd88a06737797e91f892f2f104f8d
---
M src/arch/riscv/isa/formats/fp.isa
1 file changed, 17 insertions(+), 10 deletions(-)



diff --git a/src/arch/riscv/isa/formats/fp.isa  
b/src/arch/riscv/isa/formats/fp.isa

index d015239..9f0ad20 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -36,20 +36,13 @@
 Fault %(class_name)s::execute(ExecContext *xc,
 Trace::InstRecord *traceData) const
 {
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (status.fs == FPUStatus::OFF)
-return std::make_shared("FPU is off",  
machInst);

-
+%(fp_enabled_check)s;
 %(op_decl)s;
 %(op_rd)s;

-RegVal FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
 std::feclearexcept(FE_ALL_EXCEPT);
 %(code)s;
-
-FFLAGS |= softfloat_exceptionFlags;
-softfloat_exceptionFlags = 0;
-xc->setMiscReg(MISCREG_FFLAGS, FFLAGS);
+%(set_fflags)s;

 %(op_wb)s;

@@ -58,7 +51,21 @@
 }};

 def format FPROp(code, *opt_flags) {{
-iop = InstObjParams(name, Name, 'RegOp', code, opt_flags)
+fp_enabled_check = """
+STATUS status = xc->readMiscReg(MISCREG_STATUS);
+if (status.fs == FPUStatus::OFF)
+return std::make_shared("FPU is off",  
machInst);

+"""
+
+set_fflags = """
+Fflags = Fflags | softfloat_exceptionFlags;
+softfloat_exceptionFlags = 0;
+"""
+
+iop = InstObjParams(name, Name, 'RegOp',
+{ "code": code,
+  "fp_enabled_check": fp_enabled_check,
+  "set_fflags": set_fflags }, opt_flags)
 header_output = BasicDeclare.subst(iop)
 decoder_output = BasicConstructor.subst(iop)
 decode_block = BasicDecode.subst(iop)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45526
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9f614225cedcd88a06737797e91f892f2f104f8d
Gerrit-Change-Number: 45526
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Pull some code out of a macro and into the ISA desc.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45527 )



Change subject: arch-riscv: Pull some code out of a macro and into the ISA  
desc.

..

arch-riscv: Pull some code out of a macro and into the ISA desc.

A macro defined outside of the ISA description was pulled into the
description and used in the implementation of some instructions. Macros
are inherently not great, and this also hid any operands being used from
the ISA parser. This change also makes that code use an operand to read
FRM instead of calling readMiscReg directly.

Change-Id: If3ef7aeef8299f3a0dcc9d59f01414845ea2eb36
---
D src/arch/riscv/fp_inst.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/includes.isa
4 files changed, 63 insertions(+), 118 deletions(-)



diff --git a/src/arch/riscv/fp_inst.hh b/src/arch/riscv/fp_inst.hh
deleted file mode 100644
index 604c016..000
--- a/src/arch/riscv/fp_inst.hh
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2021 StreamComputing Corp.
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kai Ren
- */
-
-#ifndef __ARCH_RISCV_FP_INST_HH__
-#define __ARCH_RISCV_FP_INST_HH__
-
-#define  
RM_REQUIRED \
-uint_fast8_t rm =  
ROUND_MODE;   \
-uint_fast8_t frm =  
xc->readMiscReg(MISCREG_FRM);\
-if (rm ==  
7)\
-rm =  
frm;   \
-if (rm >  
4) \
-return std::make_shared("RM fault",  
machInst);\
-softfloat_roundingMode =  
rm;\

-
-#endif // __ARCH_RISCV_FP_INST_HH__
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 6482dd6..f5e69c0 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -887,16 +887,14 @@

 format FPROp {
 0x10: decode FUNCT2 {
-0x0: fmadd_s({{
-RM_REQUIRED;
+0x0: FPROpRm::fmadd_s({{
 freg_t fd;
 fd = freg(f32_mulAdd(f32(freg(Fs1_bits)),
  f32(freg(Fs2_bits)),
  f32(freg(Fs3_bits;
 Fd_bits = fd.v;
 }}, FloatMultAccOp);
-0x1: fmadd_d({{
-RM_REQUIRED;
+0x1: FPROpRm::fmadd_d({{
 freg_t fd;
 fd = freg(f64_mulAdd(f64(freg(Fs1_bits)),
  f64(freg(Fs2_bits)),
@@ -905,8 +903,7 @@
 }}, FloatMultAccOp);
 }
 0x11: decode FUNCT2 {
-0x0: fmsub_s({{
-RM_REQUIRED;
+0x0: FPROpRm::fmsub_s({{
 freg_t fd;
 fd = freg(f32_mulAdd(f32(freg(Fs1_bits)),
 f32(freg(Fs2_bits)),
@@ -914,8 +911,7 @@
 mask(31, 31;
 Fd_bits = fd.v;
 }}, FloatMultAccOp);
-0x1: fmsub_d({{
-RM_REQUIRED;
+0x1: 

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Use operands instead of (read|set)MiscReg in decoder.isa.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45525 )



Change subject: arch-riscv: Use operands instead of (read|set)MiscReg in  
decoder.isa.

..

arch-riscv: Use operands instead of (read|set)MiscReg in decoder.isa.

Don't go behind the parser's back when accessing MiscReg operands.

Change-Id: Ie4f1dc34afcb7cede7f3d6ed156f1e5e6207d942
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/operands.isa
2 files changed, 30 insertions(+), 33 deletions(-)



diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 823698c..6482dd6 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -51,7 +51,7 @@
 0x1: c_fld({{
 offset = CIMM3 << 3 | CIMM2 << 6;
 }}, {{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
+STATUS status = Status;
 if (status.fs == FPUStatus::OFF)
 return std::make_shared("FPU is off",
machInst);
@@ -81,7 +81,7 @@
 0x5: c_fsd({{
 offset = CIMM3 << 3 | CIMM2 << 6;
 }}, {{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
+STATUS status = Status;
 if (status.fs == FPUStatus::OFF)
 return std::make_shared("FPU is off",
machInst);
@@ -401,7 +401,7 @@
 0x01: decode FUNCT3 {
 format Load {
 0x2: flw({{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
+STATUS status = Status;
 if (status.fs == FPUStatus::OFF)
 return std::make_shared(
 "FPU is off", machInst);
@@ -410,7 +410,7 @@
 Fd_bits = fd.v;
 }}, inst_flags=FloatMemReadOp);
 0x3: fld({{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
+STATUS status = Status;
 if (status.fs == FPUStatus::OFF)
 return std::make_shared(
 "FPU is off", machInst);
@@ -507,7 +507,7 @@
 0x09: decode FUNCT3 {
 format Store {
 0x2: fsw({{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
+STATUS status = Status;
 if (status.fs == FPUStatus::OFF)
 return std::make_shared(
 "FPU is off", machInst);
@@ -515,7 +515,7 @@
 Mem_uw = (uint32_t)Fs2_bits;
 }}, inst_flags=FloatMemWriteOp);
 0x3: fsd({{
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
+STATUS status = Status;
 if (status.fs == FPUStatus::OFF)
 return std::make_shared(
 "FPU is off", machInst);
@@ -1354,7 +1354,7 @@
 0x0: decode RS2 {
 0x0: ecall({{
 return std::make_shared(
- 
(PrivilegeMode)xc->readMiscReg(MISCREG_PRV));

+(PrivilegeMode)Prv);
 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
 No_OpClass);
 0x1: ebreak({{
@@ -1362,39 +1362,34 @@
 xc->pcState());
 }}, IsSerializeAfter, IsNonSpeculative,  
No_OpClass);

 0x2: uret({{
-STATUS status =  
xc->readMiscReg(MISCREG_STATUS);

+STATUS status = Status;
 status.uie = status.upie;
 status.upie = 1;
-xc->setMiscReg(MISCREG_STATUS, status);
-NPC = xc->readMiscReg(MISCREG_UEPC);
+Status = status;
+NPC = Uepc;
 }}, IsSerializeAfter, IsNonSpeculative, IsReturn);
 }
 0x8: decode RS2 {
 0x2: sret({{
-STATUS status =  
xc->readMiscReg(MISCREG_STATUS);

-auto pm = (PrivilegeMode)xc->readMiscReg(
-MISCREG_PRV);
-if (pm == PRV_U ||
-(pm == PRV_S && status.tsr == 1)) {
+STATUS status = Status;
+if (Prv == PRV_U ||
+(Prv == PRV_S && status.tsr == 1)) {
  

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Decode more of the CSR instructions at decode time.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45521 )



Change subject: arch-riscv: Decode more of the CSR instructions at decode  
time.

..

arch-riscv: Decode more of the CSR instructions at decode time.

Figure out more about what the CSR instructions are supposed to do at
decode/instruction construction time, instead of at run time. An
instruction will usually be constructed many fewer times than it will be
executed, so we can perform the work once and then use it many times.

Change-Id: I9941bb2555e67a6c738aa3dfdca1b4857427b71c
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 45 insertions(+), 35 deletions(-)



diff --git a/src/arch/riscv/insts/standard.hh  
b/src/arch/riscv/insts/standard.hh

index 9f9cba4..1e9fcb7 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -89,11 +89,30 @@
 uint64_t csr;
 uint64_t uimm;

+bool valid = false;
+RegIndex midx = 0;
+std::string csrName;
+uint64_t maskVal = 0;
+
 /// Constructor
 CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
 : RiscvStaticInst(mnem, _machInst, __opClass),
 csr(FUNCT12), uimm(CSRIMM)
 {
+auto csr_data_it = CSRData.find(csr);
+if (csr_data_it == CSRData.end()) {
+valid = false;
+} else {
+valid = true;
+midx = csr_data_it->second.physIndex;
+csrName = csr_data_it->second.name;
+auto mask_it = CSRMasks.find(csr);
+if (mask_it == CSRMasks.end())
+maskVal = mask(64);
+else
+maskVal = mask_it->second;
+}
+
 if (csr == CSR_SATP) {
 flags[IsSquashAfter] = true;
 }
diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index c31682d..e0b270b 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -279,15 +279,17 @@
 %(class_name)s::execute(ExecContext *xc,
 Trace::InstRecord *traceData) const
 {
+if (!valid) {
+return std::make_shared(
+csprintf("Illegal CSR index %#x\n", csr), machInst);
+}
+
 %(op_decl)s;
 %(op_rd)s;

 RegVal data, olddata;
+
 switch (csr) {
-  case CSR_FCSR:
-olddata = xc->readMiscReg(MISCREG_FFLAGS) |
-  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-break;
   case CSR_SATP: {
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
 STATUS status = xc->readMiscReg(MISCREG_STATUS);
@@ -295,8 +297,6 @@
 return std::make_shared(
 "SATP access in user mode or with TVM enabled\n",
 machInst);
-} else {
-olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
 }
 break;
   }
@@ -306,48 +306,40 @@
 return std::make_shared(
 "MSTATUS is only accessibly in machine mode\n",
 machInst);
-} else {
-olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
 }
 break;
   }
   default:
-if (CSRData.find(csr) != CSRData.end()) {
-olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
-} else {
-return std::make_shared(
-csprintf("Illegal CSR index %#x\n", csr),  
machInst);

-}
 break;
 }
-auto mask = CSRMasks.find(csr);
+
+if (csr == CSR_FCSR) {
+olddata = xc->readMiscReg(MISCREG_FFLAGS) |
+  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+} else {
+olddata = xc->readMiscReg(midx);
+}
 auto olddata_all = olddata;
-if (mask != CSRMasks.end())
-olddata &= mask->second;
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", CSRData.at(csr).name,
-olddata);
+
+olddata &= maskVal;
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, olddata);
 data = olddata;

 %(code)s;
-if (mask != CSRMasks.end())
-data &= mask->second;
+
+data &= maskVal;
 if (data != olddata) {
 if (bits(csr, 11, 10) == 0x3) {
 return std::make_shared(
-csprintf("CSR %s is read-only\n",
-CSRData.at(csr).name), machInst);
+csprintf("CSR %s is read-only\n", csrName),  
machInst);

 }
 auto newdata_all = data;
-if (mask != CSRMasks.end()) {
-// we must keep those original bits 

[gem5-dev] Change in gem5/gem5[develop]: cpu: Stop using macros for constants in the multiperpsective_perceptron.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45519 )



Change subject: cpu: Stop using macros for constants in the  
multiperpsective_perceptron.

..

cpu: Stop using macros for constants in the multiperpsective_perceptron.

Enums work just as well and respect namespaces and scopes.

Change-Id: If726ff325be7114c9a749f5f4e1a193552a24c2b
---
M src/cpu/pred/multiperspective_perceptron.cc
1 file changed, 21 insertions(+), 18 deletions(-)



diff --git a/src/cpu/pred/multiperspective_perceptron.cc  
b/src/cpu/pred/multiperspective_perceptron.cc

index f46241b..5c07c9a 100644
--- a/src/cpu/pred/multiperspective_perceptron.cc
+++ b/src/cpu/pred/multiperspective_perceptron.cc
@@ -672,18 +672,21 @@
 train(tid, *bi, taken);
 }

-#define RECORD_FILTERED_IMLI  1
-#define RECORD_FILTERED_GHIST 2
-#define RECORD_FILTERED_PATH  4
-#define RECORD_FILTERED_ACYCLIC   8
-#define RECORD_FILTERED_MOD  16
-#define RECORD_FILTERED_BLURRY   32
-// should never record a filtered local branch - duh!
-#define RECORD_FILTERED_LOCAL64
-#define RECORD_FILTERED_RECENCY 128
+enum RecordFiltered
+{
+Imli = 1,
+Ghist = 2,
+Path = 4,
+Acyclic = 8,
+Mod = 16,
+Blurry = 32,
+// Should never record a filtered local branch - duh!
+Local = 64,
+Recency = 128
+};

 // four different styles of IMLI
-if (!bi->filtered || (record_mask & RECORD_FILTERED_IMLI)) {
+if (!bi->filtered || (record_mask & Imli)) {
 unsigned int target = corrTarget;
 if (target < bi->getPC()) {
 if (taken) {
@@ -713,7 +716,7 @@
 bool hashed_taken = hash_taken ? (taken ^ !!(bi->getPC() & (1filtered || (record_mask & Ghist)) {
 bool ab = hashed_taken;
 assert(threadData[tid]->ghist_words.size() > 0);
 for (int i = 0; i < ghist_length / blockSize + 1; i += 1) {
@@ -728,7 +731,7 @@
 }

 // record into path history
-if (!bi->filtered || (record_mask & RECORD_FILTERED_PATH)) {
+if (!bi->filtered || (record_mask & Path)) {
 assert(threadData[tid]->path_history.size() > 0);
 memmove([tid]->path_history[1],
 [tid]->path_history[0],
@@ -737,12 +740,12 @@
 }

 // record into acyclic history
-if (!bi->filtered || (record_mask & RECORD_FILTERED_ACYCLIC)) {
+if (!bi->filtered || (record_mask & Acyclic)) {
 threadData[tid]->updateAcyclic(hashed_taken, bi->getHPC());
 }

 // record into modulo path history
-if (!bi->filtered || (record_mask & RECORD_FILTERED_MOD)) {
+if (!bi->filtered || (record_mask & Mod)) {
 for (int ii = 0; ii < modpath_indices.size(); ii += 1) {
 int i = modpath_indices[ii];
 if (bi->getHPC() % (i + 2) == 0) {
@@ -755,7 +758,7 @@
 }

 // update blurry history
-if (!bi->filtered || (record_mask & RECORD_FILTERED_BLURRY)) {
+if (!bi->filtered || (record_mask & Blurry)) {
 std::vector> _histories =
  threadData[tid]->blurrypath_histories;

@@ -775,7 +778,7 @@
 }

 // record into modulo pattern history
-if (!bi->filtered || (record_mask & RECORD_FILTERED_MOD)) {
+if (!bi->filtered || (record_mask & Mod)) {
 for (int ii = 0; ii < modhist_indices.size(); ii += 1) {
 int i = modhist_indices[ii];
 if (bi->getHPC() % (i + 2) == 0) {
@@ -790,13 +793,13 @@

 // insert this PC into the recency stack
 if (doing_recency) {
-if (!bi->filtered || (record_mask & RECORD_FILTERED_RECENCY)) {
+if (!bi->filtered || (record_mask & Recency)) {
 threadData[tid]->insertRecency(bi->getPC2(), assoc);
 }
 }

 // record into a local history
-if (!bi->filtered || (record_mask & RECORD_FILTERED_LOCAL)) {
+if (!bi->filtered || (record_mask & Local)) {
 threadData[tid]->localHistories.update(bi->getPC(), hashed_taken);
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If726ff325be7114c9a749f5f4e1a193552a24c2b
Gerrit-Change-Number: 45519
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Use operands instead of (read|set)MiscReg in CSR ops.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45524 )



Change subject: arch-riscv: Use operands instead of (read|set)MiscReg in  
CSR ops.

..

arch-riscv: Use operands instead of (read|set)MiscReg in CSR ops.

Don't go behind the parsers back to access operands.

Change-Id: Ie6aa581ab355271301120a5c390152f7e6f8f667
---
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/operands.isa
2 files changed, 19 insertions(+), 16 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index 23a02ff..648134f 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -464,13 +464,12 @@
 }};

 def format CSROp(code, *opt_flags) {{
-basic_read = "xc->readMiscReg(midx);"
-basic_write = "xc->setMiscReg(midx, data);"
+basic_read = "Csr;"
+basic_write = "Csr = data;"

 satp_priv = """
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
+STATUS status = Status;
+if (Prv == PRV_U || (Prv == PRV_S && status.tvm == 1)) {
 return std::make_shared(
 "SATP access in user mode or with TVM enabled\\n",
 machInst);
@@ -478,21 +477,16 @@
 """

 mstatus_priv = """
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
+if (Prv != PrivilegeMode::PRV_M) {
 return std::make_shared(
-"MSTATUS is only accessibly in machine mode\\n",
-machInst);
+"MSTATUS is only accessibly in machine mode\\n",  
machInst);

 }
 """

-fcsr_read = """
-xc->readMiscReg(MISCREG_FFLAGS) |
-(xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-"""
+fcsr_read = "Fflags | (Frm << FRM_OFFSET);"
 fcsr_write = """
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
+Fflags = bits(data, 4, 0);
+Frm = bits(data, 7, 5);
 """

 regs = (
diff --git a/src/arch/riscv/isa/operands.isa  
b/src/arch/riscv/isa/operands.isa

index 78cd5f9..959987d 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -38,7 +38,9 @@
 'sd' : 'int64_t',
 'ud' : 'uint64_t',
 'sf' : 'float',
-'df' : 'double'
+'df' : 'double',
+
+'status' : 'STATUS',
 }};

 def operands {{
@@ -74,6 +76,13 @@
 #Memory Operand
 'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 5),

+#Misc Operands
+'Csr': ('ControlReg', 'ud', 'midx', None, 9),
+'Fflags': ('ControlReg', 'ud', 'MISCREG_FFLAGS', None, 10),
+'Frm': ('ControlReg', 'ud', 'MISCREG_FRM', None, 11),
+'Prv': ('ControlReg', 'ud', 'MISCREG_PRV', None, 12),
+'Status': ('ControlReg', 'status', 'MISCREG_STATUS', None, 13),
+
 #Program Counter Operands
 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie6aa581ab355271301120a5c390152f7e6f8f667
Gerrit-Change-Number: 45524
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Choose specialized versions of CSR ops at decode time.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45523 )



Change subject: arch-riscv: Choose specialized versions of CSR ops at  
decode time.

..

arch-riscv: Choose specialized versions of CSR ops at decode time.

Generate specialized versions of the CSR ops which handle some special
cases, like CSRs with privilege checks and one which is made up of
several sub-registers.

Change-Id: I49c49b1ebe63dbae7ac1fb42cd194f4439c51032
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 88 insertions(+), 79 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index dba460f..23a02ff 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -287,37 +287,9 @@
 %(op_decl)s;
 %(op_rd)s;

-switch (csr) {
-  case CSR_SATP: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-return std::make_shared(
-"SATP access in user mode or with TVM enabled\n",
-machInst);
-}
-break;
-  }
-  case CSR_MSTATUS: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
-return std::make_shared(
-"MSTATUS is only accessibly in machine mode\n",
-machInst);
-}
-break;
-  }
-  default:
-break;
-}
+%(p_check)s;

-RegVal data;
-if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
-   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
-data = xc->readMiscReg(midx);
-}
+RegVal data = %(r_code)s;

 DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);

@@ -345,38 +317,9 @@
 %(op_decl)s;
 %(op_rd)s;

-switch (csr) {
-  case CSR_SATP: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-return std::make_shared(
-"SATP access in user mode or with TVM enabled\n",
-machInst);
-}
-break;
-  }
-  case CSR_MSTATUS: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
-return std::make_shared(
-"MSTATUS is only accessibly in machine mode\n",
-machInst);
-}
-break;
-  }
-  default:
-break;
-}
+%(p_check)s;

-RegVal data;
-if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
-  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
-data = xc->readMiscReg(midx);
-}
-
+RegVal data = %(r_code)s;
 RegVal original = data;

 DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data &  
maskVal);

@@ -389,12 +332,7 @@

 DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, csrName);

-if (csr == CSR_FCSR) {
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-} else {
-xc->setMiscReg(midx, data);
-}
+%(w_code)s;

 %(op_wb)s;
 return NoFault;
@@ -500,22 +438,93 @@
 }};

 def template CSRDecode {{
-if (RS1)
-return new %(class_name)sRw(machInst);
-else
-return new %(class_name)sRo(machInst);
+if (RS1) {
+switch (FUNCT12) {
+  case CSR_SATP:
+return new %(class_name)sSatpRw(machInst);
+  case CSR_MSTATUS:
+return new %(class_name)sMstatusRw(machInst);
+  case CSR_FCSR:
+return new %(class_name)sFcsrRw(machInst);
+  default:
+return new %(class_name)sRw(machInst);
+}
+} else {
+switch (FUNCT12) {
+  case CSR_SATP:
+return new %(class_name)sSatpRo(machInst);
+  case CSR_MSTATUS:
+return new %(class_name)sMstatusRo(machInst);
+  case CSR_FCSR:
+return new %(class_name)sFcsrRo(machInst);
+  default:
+return new %(class_name)sRo(machInst);
+}
+}
 }};

 def format CSROp(code, *opt_flags) {{
-iop = InstObjParams(name, Name + "Ro", 'CSROp', code, opt_flags)
-header_output = BasicDeclare.subst(iop)
-

[gem5-dev] software floating point library(s)

[Gabe Black via gem5-dev]

Hi folks. I've taken a little time recently to go macro hunting, and while
doing that I noticed what I think are three different software floating
point implementations in gem5. There is ext/fputils which has support for
80 bit floats, arch/arm/insts/fplib.hh and .cc which I'm assuming ARM uses,
and ext/softfloat which RISCV uses.

I can't think of a good reason for us to need three different solutions to
the same problem. Is there a good reason for this, or was each just not
aware of the others? Can we fold one (or two) of these into a preferred
implementation and get rid of the extra(s)?

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: misc: Add missing compiler.hh include

[Daniel Carvalho (Gerrit) via gem5-dev]

Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45459 )


Change subject: misc: Add missing compiler.hh include
..

misc: Add missing compiler.hh include

Add some missing base/compiler.hh includes.

Found by manually checking the files in:
  grep -r --include \*.hh -L \
'#include "base/compiler.hh"' \
$(grep -r -l "GEM5_" src/)

And occasionally checking some .cc files through
a similar methodology.

Change-Id: I6b6e27189c627bb76ace73c338486743d469be46
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45459
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/insts/macromem.cc
M src/arch/arm/insts/pred_inst.hh
M src/arch/arm/reg_abi.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/utility.cc
M src/arch/mips/linux/aligned.hh
M src/arch/sparc/faults.cc
M src/arch/x86/insts/microop_args.hh
M src/arch/x86/isa.cc
M src/arch/x86/ldstflags.hh
M src/arch/x86/linux/linux.hh
M src/arch/x86/remote_gdb.hh
M src/base/inet.hh
M src/base/loader/elf_object.cc
M src/base/statistics.hh
M src/base/stats/group.cc
M src/base/vnc/vncinput.hh
M src/base/vnc/vncserver.hh
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/fetch1.cc
M src/cpu/minor/lsq.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/simple/timing.cc
M src/cpu/testers/memtest/memtest.cc
M src/cpu/testers/traffic_gen/pygen.hh
M src/cpu/trace/trace_cpu.cc
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/smmu_v3.cc
M src/dev/net/tcp_iface.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
M src/dev/virtio/base.hh
M src/dev/virtio/block.hh
M src/dev/virtio/console.hh
M src/dev/virtio/fs9p.hh
M src/dev/virtio/pci.cc
M src/gpu-compute/gpu_compute_driver.cc
M src/gpu-compute/schedule_stage.cc
M src/kern/linux/helpers.cc
M src/kern/linux/linux.cc
M src/kern/linux/printk.cc
M src/kern/system_events.cc
M src/learning_gem5/part2/simple_cache.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.hh
M src/mem/cache/compressors/frequent_values.cc
M src/mem/cache/noncoherent_cache.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/coherent_xbar.cc
M src/mem/external_slave.cc
M src/mem/mem_interface.hh
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/RoutingUnit.cc
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/PerfectCacheMemory.hh
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubySystem.cc
M src/systemc/core/sc_main_fiber.cc
66 files changed, 71 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 6b1070b..a5eb182 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -44,6 +44,7 @@

 #include "arch/arm/generated/decoder.hh"
 #include "arch/arm/insts/neon64_mem.hh"
+#include "base/compiler.hh"

 using namespace ArmISAInst;

diff --git a/src/arch/arm/insts/pred_inst.hh  
b/src/arch/arm/insts/pred_inst.hh

index 00b8fb2..ca5f3f1 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -42,6 +42,7 @@
 #define __ARCH_ARM_INSTS_PREDINST_HH__

 #include "arch/arm/insts/static_inst.hh"
+#include "base/compiler.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"

diff --git a/src/arch/arm/reg_abi.hh b/src/arch/arm/reg_abi.hh
index 94dea18..e738c5c 100644
--- a/src/arch/arm/reg_abi.hh
+++ b/src/arch/arm/reg_abi.hh
@@ -74,4 +74,4 @@

 } // namespace GuestABI

-#endif // __ARCH_ARM_GEM5_OP_HH__
+#endif // __ARCH_ARM_REG_ABI_HH__
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 9fa4315..1b36f93 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -42,6 +42,7 @@
 #include "arch/arm/stage2_mmu.hh"
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
+#include "base/compiler.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Checkpoint.hh"
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 93995c0..bf6d0bb 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -55,6 +55,7 @@
 #include "arch/arm/table_walker.hh"
 #include "arch/arm/tlbi_op.hh"
 #include "arch/arm/utility.hh"
+#include "base/compiler.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 965ed63..263ceb7 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -46,6 +46,7 @@
 #include 

[gem5-dev] Change in gem5/gem5[develop]: arch-vega,arch-gcn3: Fix s_cmp_lt_u32

[Matthew Poremba (Gerrit) via gem5-dev]

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45499 )


Change subject: arch-vega,arch-gcn3: Fix s_cmp_lt_u32
..

arch-vega,arch-gcn3: Fix s_cmp_lt_u32

Was using less-than-or-equal rather than less-than. All other comparison
instructions look correct otherwise.

Change-Id: Iee0374554f21a80a6da2eb75f38b22c83b6e1e9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45499
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.cc
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc  
b/src/arch/amdgpu/gcn3/insts/instructions.cc

index 8cadff7..2761008 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -3496,7 +3496,7 @@
 src0.read();
 src1.read();

-scc = (src0.rawData() <= src1.rawData()) ? 1 : 0;
+scc = (src0.rawData() < src1.rawData()) ? 1 : 0;

 scc.write();
 }
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index 0a01bf2..5db3e54 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -3832,7 +3832,7 @@
 src0.read();
 src1.read();

-scc = (src0.rawData() <= src1.rawData()) ? 1 : 0;
+scc = (src0.rawData() < src1.rawData()) ? 1 : 0;

 scc.write();
 } // execute

--
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https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iee0374554f21a80a6da2eb75f38b22c83b6e1e9c
Gerrit-Change-Number: 45499
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #310

[jenkins-no-reply--- via gem5-dev]

See 

Changes:


--
[...truncated 175.79 KB...]
build/NULL/base/flags.test.fast 
--gtest_output=xml:build/NULL/unittests.fast/base/flags.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 3 tests from 1 test suite.
[--] Global test environment set-up.
[--] 3 tests from Fiber
[ RUN  ] Fiber.Starting
[   OK ] Fiber.Starting (0 ms)
[ RUN  ] Fiber.Switching
[   OK ] Fiber.Switching (0 ms)
[ RUN  ] Fiber.Linked
[   OK ] Fiber.Linked (0 ms)
[--] 3 tests from Fiber (1 ms total)

[--] Global test environment tear-down
[==] 3 tests from 1 test suite ran. (1 ms total)
[  PASSED  ] 3 tests.
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 16 tests from 1 test suite.
[--] Global test environment set-up.
[--] 16 tests from FlagsTest
[ RUN  ] FlagsTest.ConstructorZero
[   OK ] FlagsTest.ConstructorZero (0 ms)
[ RUN  ] FlagsTest.ConstructorSingle
[   OK ] FlagsTest.ConstructorSingle (0 ms)
[ RUN  ] FlagsTest.ConstructorMulti
[   OK ] FlagsTest.ConstructorMulti (0 ms)
[ RUN  ] FlagsTest.TypeAssignment
[   OK ] FlagsTest.TypeAssignment (0 ms)
[ RUN  ] FlagsTest.TypeAssignmentOverwrite
[   OK ] FlagsTest.TypeAssignmentOverwrite (0 ms)
[ RUN  ] FlagsTest.FlagsAssignment
[   OK ] FlagsTest.FlagsAssignment (0 ms)
[ RUN  ] FlagsTest.FlagsAssignmentOverwrite
[   OK ] FlagsTest.FlagsAssignmentOverwrite (0 ms)
[ RUN  ] FlagsTest.IsSetValue
[   OK ] FlagsTest.IsSetValue (0 ms)
[ RUN  ] FlagsTest.IsSetType
[   OK ] FlagsTest.IsSetType (0 ms)
[ RUN  ] FlagsTest.AllSetMatch
[   OK ] FlagsTest.AllSetMatch (0 ms)
[ RUN  ] FlagsTest.NoneSetMatch
[   OK ] FlagsTest.NoneSetMatch (0 ms)
[ RUN  ] FlagsTest.Clear
[   OK ] FlagsTest.Clear (0 ms)
[ RUN  ] FlagsTest.ClearMatch
[   OK ] FlagsTest.ClearMatch (0 ms)
[ RUN  ] FlagsTest.SetOverlapping
[   OK ] FlagsTest.SetOverlapping (0 ms)
[ RUN  ] FlagsTest.ConditionalSet
[   OK ] FlagsTest.ConditionalSet (0 ms)
[ RUN  ] FlagsTest.ReplaceOverlapping
[   OK ] FlagsTest.ReplaceOverlapping (0 ms)
[--] 16 tests from FlagsTest (0 ms total)

[--] Global test environment tear-down
[==] 16 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 16 tests.
build/NULL/base/inifile.test.fast 
--gtest_output=xml:build/NULL/unittests.fast/base/inifile.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 2 tests from 1 test suite.
[--] Global test environment set-up.
[--] 2 tests from Initest
[ RUN  ] Initest.MatchFound
[   OK ] Initest.MatchFound (0 ms)
[ RUN  ] Initest.MatchNotFound
[   OK ] Initest.MatchNotFound (0 ms)
[--] 2 tests from Initest (0 ms total)

[--] Global test environment tear-down
[==] 2 tests from 1 test suite ran. (0 ms total)
[  PASSED  ] 2 tests.
build/NULL/base/intmath.test.fast 
--gtest_output=xml:build/NULL/unittests.fast/base/intmath.test.xml
Running main() from build/googletest/googletest/src/gtest_main.cc
[==] Running 14 tests from 2 test suites.
[--] Global test environment set-up.
[--] 1 test from IntmathDeathTest
[ RUN  ] IntmathDeathTest.Log2iDeath
[  SKIPPED ] IntmathDeathTest.Log2iDeath (0 ms)
[--] 1 test from IntmathDeathTest (0 ms total)

[--] 13 tests from IntmathTest
[ RUN  ] IntmathTest.isPowerOf2
[   OK ] IntmathTest.isPowerOf2 (0 ms)
[ RUN  ] IntmathTest.floorLog2
[   OK ] IntmathTest.floorLog2 (0 ms)
[ RUN  ] IntmathTest.ceilLog2
[   OK ] IntmathTest.ceilLog2 (0 ms)
[ RUN  ] IntmathTest.divCeil
[   OK ] IntmathTest.divCeil (0 ms)
[ RUN  ] IntmathTest.mulUnsignedNarrow
[   OK ] IntmathTest.mulUnsignedNarrow (0 ms)
[ RUN  ] IntmathTest.mulSignedNarrow
[   OK ] IntmathTest.mulSignedNarrow (0 ms)
[ RUN  ] IntmathTest.mulUnsignedMid
[   OK ] IntmathTest.mulUnsignedMid (0 ms)
[ RUN  ] IntmathTest.mulSignedMid
[   OK ] IntmathTest.mulSignedMid (0 ms)
[ RUN  ] IntmathTest.mulUnsignedWide
[   OK ] IntmathTest.mulUnsignedWide (0 ms)
[ RUN  ] IntmathTest.mulSignedWide
[   OK ] IntmathTest.mulSignedWide (0 ms)
[ RUN  ] IntmathTest.roundUp
[   OK ] IntmathTest.roundUp (0 ms)
[ RUN  ] IntmathTest.roundDown
[   OK ] IntmathTest.roundDown (0 ms)
[ RUN  ] IntmathTest.Log2i
[   OK ] IntmathTest.Log2i (0 ms)
[--] 13 tests from IntmathTest (1 ms total)

[--] Global test environment tear-down
[==] 14 tests from 2 test suites ran. (1 ms total)
[  PASSED  ] 13 tests.
[  SKIPPED ] 1 test, listed below:
[  SKIPPED ] IntmathDeathTest.Log2iDeath
build/NULL/base/loader/image_file_data.test.fast