[gem5-dev] Build failed in Jenkins: weekly #28

2021-05-27 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[Giacomo Travaglini] arch-arm: Stop using the DmaPort in the TableWalker

[Giacomo Travaglini] arch: Make MMU::flushAll virtual

[odanrc] base: Add macros to deprecate namespaces and classes

[odanrc] dev: Rename Sinic namespace as sinic

[odanrc] dev: Rename TxdOp namespace as txd_op

[odanrc] dev: Rename CopyEngineReg namespace as copy_engine_reg

[odanrc] dev: Rename sinic::Regs namespace as sinic::registers

[odanrc] dev: Rename ps2 variables as ps2Device

[odanrc] dev: Rename Ps2 namespace as ps2

[odanrc] dev: Rename iGbReg namespace as igbreg

[odanrc] dev-arm: Rename SCMI namespace as scmi

[odanrc] arch: Rename some linux loader variables as linuxLoader

[odanrc] arch: Rename freebsd loader variables as freebsdLoader

[odanrc] gpu-compute: Rename prefetch variable as isPrefetch

[gabe.black] base: Initialize some variables in the wide multiply helpers.

[gabe.black] arch-x86: Work around a bug in g++ 6 and 7.

[gabe.black] cpu: Fix style in cpu/simple/base.hh.

[gabe.black] cpu: Fix syntax in cpu/simple_thread.hh.

[gabe.black] base: Use a lambda to simplify the stl_helpers template.

[gabe.black] cpu: Add a sendFunctional function to the ThreadContext.

[gabe.black] fastmodel: Implement ThreadContext::sendFunctional.

[gabe.black] scons: Increase the minimum version of clang to 6.

[fcrh] base: Construct debug flags on the heap

[gabe.black] mem: Add a ThreadContext helper constructor for PortProxy.

[gabe.black] misc: Stop using BaseCPU::getSendFunctional.

[gabe.black] cpu,fastmodel: Get rid of the getSendFunctional method.

[odanrc] dev: Put PS2 classes in the ps2 namespace

[odanrc] arch-x86: Rename RomLabels namespace as rom_labels

[gabe.black] arch-sparc: Create a local port proxy for functional accesses.

[gabe.black] cpu: Create an O3 namespace and simplify O3 names.

[gabe.black] cpu: Delete the cpu/o3/isa_specific.hh header.

[gabe.black] arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.

[gabe.black] base: Apply the stl_helpers helper judiciously.

[gabe.black] arch,cpu: Make the decoder width a property of the decoder.

[Bobby R. Bruce] tests: Add sleep and debug to the jenkins presubmit.sh

[Bobby R. Bruce] arch-riscv: Fix struct causing compilation errors in clang-11

[odanrc] base-stats: Create base struct for print structs

[odanrc] base-stats: Rename units variable as enableUnits

[odanrc] base-stats: Rename Units namespace as units

[odanrc] arch-x86: Rename SMBios namespace as smbios

[odanrc] arch-x86: Rename IntelMP namespace as intelmp

[odanrc] arch-x86: Rename ConditionTests namespace as condition_tests

[odanrc] arch-x86: Rename X86Macroop namespace as x86_macroop

[odanrc] base: Rename BloomFilter namespace as bloom_filter

[odanrc] misc: Rename SimClock namespace as sim_clock

[odanrc] arch: Rename Linux namespace as linux

[odanrc] arch: Rename FreeBSD namespace as free_bsd

[odanrc] misc: Rename BitfieldBackend namespace as bitfield_backend

[odanrc] arch,cpu: Rename DecodeCache namespace as decode_cache

[odanrc] arch,sim: Rename PseudoInst namespace as pseudo_inst

[odanrc] sim: Turn InitParamKey into an anonymous namespace

[odanrc] arch-x86,dev: Rename DeliveryMode namespace as delivery_mode

[odanrc] arch: Rename LockedMem namespace as locked_mem

[odanrc] arch,sim: Rename GuestABI namespace as guest_abi

[odanrc] fastmodel: Rename FastModel namespace as fastmodel

[odanrc] sim,misc: Rename Float namespace as as_float

[odanrc] sim,misc: Rename Int namespace as as_int

[odanrc] dev: Rename Keyboard namespace as keyboard

[odanrc] dev: Rename Mouse namespace as mouse

[odanrc] mem: Rename qos variables as _qos

[odanrc] mem: Rename QoS namespace as qos

[odanrc] mem: Rename ReplacementPolicy namespace as replacement_policy

[odanrc] sim: Fix test names in guest ABI unit test

[Jason Lowe-Power] cpu-o3: Fix parenthesis in condition

[hoanguyen] mem-ruby: replace desks, add desc where required

[fcrh] base: Construct loggers on the heap

[gabe.black] arch,kern,sim: Use a map to map syscall flags.


--
[...truncated 346.71 KB...]
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_8KB.cc -> .o
 [SOPARMHH] MultiperspectivePerceptron64KB -> 
GCN3_X86/params/MultiperspectivePerceptron64KB.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_64KB.cc -> .o
 [SOPARMHH] MPP_LoopPredictor -> GCN3_X86/params/MPP_LoopPredictor.hh
 [SOPARMHH] MPP_StatisticalCorrector -> 
GCN3_X86/params/MPP_StatisticalCorrector.hh
 [SOPARMHH] MPP_TAGE -> GCN3_X86/params/MPP_TAGE.hh
 [SOPARMHH] MultiperspectivePerceptronTAGE -> 
GCN3_X86/params/MultiperspectivePerceptronTAGE.hh
 [SOPARMHH] StatisticalCorrector -> GCN3_X86/params/StatisticalCorrector.hh
 [ CXX] GCN3_X86/cpu/pred/multiperspective_perceptron_tage.cc -> .o
 [SOPARMHH] MPP_LoopPredictor_8KB -> GCN3_X86/params/MPP_LoopPredictor_8KB.hh
 [SOPARMHH] MPP_StatisticalCorrector_8KB ->

[gem5-dev] Jenkins build is back to normal : nightly #325

2021-05-27 Thread jenkins-no-reply--- via gem5-dev 
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[gem5-dev] Change in gem5/gem5[develop]: arch,kern,sim: Use a map to map syscall flags.

2021-05-27 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45899 )


Change subject: arch,kern,sim: Use a map to map syscall flags.
..

arch,kern,sim: Use a map to map syscall flags.

Use a std::map to map target syscall flag bits to host flag bits. This
avoids having to track the number of elements in the map separately.

Change-Id: I43bd54f5286f11b9635d46240a55742ddfdb0901
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45899
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/freebsd/freebsd.cc
M src/arch/arm/freebsd/freebsd.hh
M src/arch/arm/linux/linux.hh
M src/arch/mips/linux/linux.hh
M src/arch/power/linux/linux.hh
M src/arch/riscv/linux/linux.hh
M src/arch/sparc/linux/linux.hh
M src/arch/sparc/solaris/solaris.cc
M src/arch/sparc/solaris/solaris.hh
M src/arch/x86/linux/linux.hh
M src/kern/linux/flag_tables.hh
M src/kern/operatingsystem.hh
M src/sim/syscall_emul.hh
13 files changed, 41 insertions(+), 105 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve; Looks good  
to me, approved

  kokoro: Regressions pass



diff --git a/src/arch/arm/freebsd/freebsd.cc  
b/src/arch/arm/freebsd/freebsd.cc

index 99cd032..326e1e7 100644
--- a/src/arch/arm/freebsd/freebsd.cc
+++ b/src/arch/arm/freebsd/freebsd.cc
@@ -35,7 +35,7 @@
 #include 

 // open(2) flags translation table
-SyscallFlagTransTable ArmFreebsd32::openFlagTable[] = {
+const std::map ArmFreebsd32::openFlagTable = {
   { ArmFreebsd32::TGT_O_RDONLY, O_RDONLY },
   { ArmFreebsd32::TGT_O_WRONLY, O_WRONLY },
   { ArmFreebsd32::TGT_O_RDWR,   O_RDWR },
@@ -54,11 +54,8 @@
   { ArmFreebsd32::TGT_O_NOFOLLOW,   O_NOFOLLOW },
 };

-const int ArmFreebsd32::NUM_OPEN_FLAGS =  
sizeof(ArmFreebsd32::openFlagTable) /
-
sizeof(ArmFreebsd32::openFlagTable[0]);

-
 // open(2) flags translation table
-SyscallFlagTransTable ArmFreebsd64::openFlagTable[] = {
+const std::map ArmFreebsd64::openFlagTable = {
   { ArmFreebsd64::TGT_O_RDONLY, O_RDONLY },
   { ArmFreebsd64::TGT_O_WRONLY, O_WRONLY },
   { ArmFreebsd64::TGT_O_RDWR,   O_RDWR },
@@ -76,7 +73,3 @@
   { ArmFreebsd64::TGT_O_DIRECTORY,  O_DIRECTORY },
   { ArmFreebsd64::TGT_O_NOFOLLOW,   O_NOFOLLOW },
 };
-
-const int ArmFreebsd64::NUM_OPEN_FLAGS =  
sizeof(ArmFreebsd64::openFlagTable) /
-
sizeof(ArmFreebsd64::openFlagTable[0]);

-
diff --git a/src/arch/arm/freebsd/freebsd.hh  
b/src/arch/arm/freebsd/freebsd.hh

index c552588..465b6fa 100644
--- a/src/arch/arm/freebsd/freebsd.hh
+++ b/src/arch/arm/freebsd/freebsd.hh
@@ -33,6 +33,8 @@
 #ifndef __ARCH_ARM_FREEBSD_FREEBSD_HH__
 #define __ARCH_ARM_FREEBSD_FREEBSD_HH__

+#include 
+
 #include "kern/freebsd/freebsd.hh"
 #include "sim/byteswap.hh"

@@ -47,10 +49,7 @@
   public:
 /// This table maps the target open() flags to the corresponding
 /// host open() flags.
-static SyscallFlagTransTable openFlagTable[];
-
-/// Number of entries in openFlagTable[].
-static const int NUM_OPEN_FLAGS;
+static const std::map openFlagTable;

 //@{
 /// Basic ARM FreeBSD types
@@ -211,10 +210,7 @@

 /// This table maps the target open() flags to the corresponding
 /// host open() flags.
-static SyscallFlagTransTable openFlagTable[];
-
-/// Number of entries in openFlagTable[].
-static const int NUM_OPEN_FLAGS;
+static const std::map openFlagTable;

 //@{
 /// Basic ARM FreeBSD types
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index 6ca877c..6947d2d 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -42,6 +42,8 @@
 #ifndef __ARCH_ARM_LINUX_LINUX_HH__
 #define __ARCH_ARM_LINUX_LINUX_HH__

+#include 
+
 #include "arch/arm/utility.hh"
 #include "base/compiler.hh"
 #include "kern/linux/linux.hh"
@@ -108,10 +110,7 @@

 /// This table maps the target open() flags to the corresponding
 /// host open() flags.
-static SyscallFlagTransTable openFlagTable[];
-
-/// Number of entries in openFlagTable[].
-static const int NUM_OPEN_FLAGS;
+static const std::map openFlagTable;

 //@{
 /// Basic ARM Linux types
@@ -160,8 +159,6 @@
 static const unsigned TGT_MAP_ANONYMOUS = 0x00020;
 static const unsigned TGT_MAP_FIXED = 0x00010;

-static const unsigned NUM_MMAP_FLAGS;
-
 /// For table().
 static const int TBL_SYSINFO = 12;

@@ -338,10 +335,7 @@

 /// This table maps the target open() flags to the corresponding
 /// host open() flags.
-static SyscallFlagTransTable openFlagTable[];
-
-/// Number of entries in openFlagTable[].
-static const int NUM_OPEN_FLAGS;
+static const std::map openFlagTable;

 //@{
 /// Basic ARM Linux types
@@

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Fix building with Fast Model.

2021-05-27 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46120 )



Change subject: fastmodel: Fix building with Fast Model.
..

fastmodel: Fix building with Fast Model.

Some build errors had crept in over time. This change fixes them.

Change-Id: I457d32190aa65b0ecd2d6de3f4f5d42d922ae5d5
---
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/fastmodel/iris/isa.hh
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
7 files changed, 36 insertions(+), 22 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

index 43510e6..98c2922 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -28,6 +28,7 @@
 #include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"

 #include "arch/arm/fastmodel/iris/cpu.hh"
+#include "arch/arm/regs/misc.hh"
 #include "base/logging.hh"
 #include "dev/arm/base_gic.hh"
 #include "sim/core.hh"
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc  
b/src/arch/arm/fastmodel/GIC/gic.cc

index 3133757..2830c83 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -70,7 +70,7 @@

 SCGIC::SCGIC(const SCFastModelGICParams ,
  sc_core::sc_module_name _name)
-: scx_evs_GIC(_name)
+: scx_evs_GIC(_name), _params(params)
 {
 signalInterrupt.bind(signal_interrupt);

diff --git a/src/arch/arm/fastmodel/GIC/gic.hh  
b/src/arch/arm/fastmodel/GIC/gic.hh

index 33997fd..b283108 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -81,6 +81,7 @@
 };

 std::unique_ptr terminator;
+const SCFastModelGICParams &_params;

   public:
 SCGIC(const SCFastModelGICParams ) : SCGIC(p, p.name.c_str()) {}
diff --git a/src/arch/arm/fastmodel/iris/isa.cc  
b/src/arch/arm/fastmodel/iris/isa.cc

index 4aac71f..9312d4e 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -28,8 +28,8 @@
 #include "arch/arm/fastmodel/iris/isa.hh"

 #include "arch/arm/regs/misc.hh"
+#include "base/logging.hh"
 #include "cpu/thread_context.hh"
-#include "params/IrisISA.hh"
 #include "sim/serialize.hh"

 void
@@ -40,3 +40,9 @@
 miscRegs[i] = tc->readMiscRegNoEffect(i);
 SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS);
 }
+
+void
+Iris::ISA::copyRegsFrom(ThreadContext *src)
+{
+panic("copyRegsFrom not implemented");
+}
diff --git a/src/arch/arm/fastmodel/iris/isa.hh  
b/src/arch/arm/fastmodel/iris/isa.hh

index a7ae7b5..9b2828c 100644
--- a/src/arch/arm/fastmodel/iris/isa.hh
+++ b/src/arch/arm/fastmodel/iris/isa.hh
@@ -39,13 +39,15 @@
   public:
 ISA(const Params ) : BaseISA(p) {}

-void serialize(CheckpointOut ) const;
+void serialize(CheckpointOut ) const override;
+
+void copyRegsFrom(ThreadContext *src) override;

 bool
 inUserMode() const override
 {
-CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-return ::inUserMode(cpsr);
+ArmISA::CPSR cpsr = tc->readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
+return ArmISA::inUserMode(cpsr);
 }
 };

diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc  
b/src/arch/arm/fastmodel/iris/thread_context.cc

index 3116139..7bbc28b 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -672,7 +672,7 @@
 call().resource_read(_instId, result, vecRegIds.at(idx));
 size_t data_size = result.data.size() * (sizeof(*result.data.data()));
 size_t size = std::min(data_size, reg.size());
-memcpy(reg.raw_ptr(), (void *)result.data.data(), size);
+memcpy(reg.as(), (void *)result.data.data(), size);

 return reg;
 }
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index d093138..76a2415 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -32,6 +32,7 @@
 #include 
 #include 

+#include "arch/arm/regs/vec.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "iris/IrisInstance.h"
@@ -278,21 +279,22 @@
 panic("%s not implemented.", __FUNCTION__);
 }

-const VecRegContainer (const RegId ) const override;
-VecRegContainer &
+const ArmISA::VecRegContainer (const RegId ) const  
override;

+ArmISA::VecRegContainer &
 getWritableVecReg(const RegId ) override
 {
 panic("%s not implemented.", __FUNCTION__);
 }

-const VecElem &
+const ArmISA::VecElem &
 readVecElem(const RegId ) const override
 {
 panic("%s not implemented.", __FUNCTION__);
 }

-const VecPredRegContainer (const RegId ) const

[gem5-dev] Change in gem5/gem5[develop]: base: Construct loggers on the heap

2021-05-27 Thread Jui-min Lee (Gerrit) via gem5-dev 
Jui-min Lee has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46079 )


Change subject: base: Construct loggers on the heap
..

base: Construct loggers on the heap

Loggers was previously declared as global variables, hence are unsafe to
be used inside other global objects' destructor (e.g. scMainFiber). This
CL makes them heap allocated objects hold by function static variables.

As a result:
1. The loggers never get destructed at the end of program, which makes
   them safe to be used in global objects' destructor.
2. The loggers are constructed ondemand instead of relying on linker's
   unknown way of ordering, which makes them safe to be used in global
   objects' constructor.

Change-Id: Ieb499d2fa4c5c1c015324cb72b055115b0933ab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46079
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/gtest/logging_mock.cc
M src/base/logging.cc
2 files changed, 70 insertions(+), 22 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/gtest/logging_mock.cc b/src/base/gtest/logging_mock.cc
index e09a144..572d057 100644
--- a/src/base/gtest/logging_mock.cc
+++ b/src/base/gtest/logging_mock.cc
@@ -71,16 +71,40 @@
 void exit() override { throw GTestException(); }
 };

-GTestExitLogger panicLogger("panic: ");
-GTestExitLogger fatalLogger("fatal: ");
-GTestLogger warnLogger("warn: ");
-GTestLogger infoLogger("info: ");
-GTestLogger hackLogger("hack: ");
-
 } // anonymous namespace

-Logger ::getPanic() { return panicLogger; }
-Logger ::getFatal() { return fatalLogger; }
-Logger ::getWarn() { return warnLogger; }
-Logger ::getInfo() { return infoLogger; }
-Logger ::getHack() { return hackLogger; }
+// We intentionally put all the loggers on the heap to prevent them from  
being
+// destructed at the end of the program. This make them safe to be used  
inside

+// destructor of other global objects. Also, we make them function static
+// veriables to ensure they are initialized ondemand, so it is also safe  
to use

+// them inside constructor of other global objects.
+
+Logger&
+Logger::getPanic() {
+static GTestExitLogger* panic_logger = new GTestExitLogger("panic: ");
+return *panic_logger;
+}
+
+Logger&
+Logger::getFatal() {
+static GTestExitLogger* fatal_logger = new GTestExitLogger("fatal: ");
+return *fatal_logger;
+}
+
+Logger&
+Logger::getWarn() {
+static GTestLogger* warn_logger = new GTestLogger("warn: ");
+return *warn_logger;
+}
+
+Logger&
+Logger::getInfo() {
+static GTestLogger* info_logger = new GTestLogger("info: ");
+return *info_logger;
+}
+
+Logger&
+Logger::getHack() {
+static GTestLogger* hack_logger = new GTestLogger("hack: ");
+return *hack_logger;
+}
diff --git a/src/base/logging.cc b/src/base/logging.cc
index 1290455..f96d101 100644
--- a/src/base/logging.cc
+++ b/src/base/logging.cc
@@ -70,16 +70,40 @@
 void exit() override { ::exit(1); }
 };

-ExitLogger panicLogger("panic: ");
-FatalLogger fatalLogger("fatal: ");
-Logger warnLogger("warn: ");
-Logger infoLogger("info: ");
-Logger hackLogger("hack: ");
-
 } // anonymous namespace

-Logger ::getPanic() { return panicLogger; }
-Logger ::getFatal() { return fatalLogger; }
-Logger ::getWarn() { return warnLogger; }
-Logger ::getInfo() { return infoLogger; }
-Logger ::getHack() { return hackLogger; }
+// We intentionally put all the loggers on the heap to prevent them from  
being
+// destructed at the end of the program. This make them safe to be used  
inside

+// destructor of other global objects. Also, we make them function static
+// veriables to ensure they are initialized ondemand, so it is also safe  
to use

+// them inside constructor of other global objects.
+
+Logger&
+Logger::getPanic() {
+static ExitLogger* panic_logger = new ExitLogger("panic: ");
+return *panic_logger;
+}
+
+Logger&
+Logger::getFatal() {
+static FatalLogger* fatal_logger = new FatalLogger("fatal: ");
+return *fatal_logger;
+}
+
+Logger&
+Logger::getWarn() {
+static Logger* warn_logger = new Logger("warn: ");
+return *warn_logger;
+}
+
+Logger&
+Logger::getInfo() {
+static Logger* info_logger = new Logger("info: ");
+return *info_logger;
+}
+
+Logger&
+Logger::getHack() {
+static Logger* hack_logger = new Logger("hack: ");
+return *hack_logger;
+}

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieb499d2fa4c5c1c015324cb72b055115b0933ab8
Gerrit-Change-Number: 46079
Gerrit-PatchSet: 4
Gerrit-Owner: Jui-min

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: replace desks, add desc where required

2021-05-27 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46119 )


Change subject: mem-ruby: replace desks, add desc where required
..

mem-ruby: replace desks, add desc where required

Events in *.sm are required to have "desc" defined.

JIRA: https://gem5.atlassian.net/browse/GEM5-999

Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46119
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
 DMA_WRITE_PARTIAL, desc="DMA Write partial line";
 DMA_ACK,   desc="DMA Ack";
 Data,  desc="Data to directory";
-All_Acks,  desk="All pending acks, unblocks, etc have been  
received";
+All_Acks,  desc="All pending acks, unblocks, etc have been  
received";

   }

   // TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
   state_declaration(State, default="Cache_State_null") {
 // Stable states

-I, AccessPermission:Invalid,desk="Invalid / not present locally or  
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or  
upstream";


 // States when block is present in local cache only
 SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
 UD_T, AccessPermission:Read_Write,  desc="UD with use timeout";

 // Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid,   desk="Upstream requester has line in  
UD/UC";
-RSC, AccessPermission:Invalid,  desk="Upstream requester has line in  
SC";
-RSD, AccessPermission:Invalid,  desk="Upstream requester has line in  
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has  
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has  
exclusive access";
+RU, AccessPermission:Invalid,   desc="Upstream requester has line in  
UD/UC";
+RSC, AccessPermission:Invalid,  desc="Upstream requester has line in  
SC";
+RSD, AccessPermission:Invalid,  desc="Upstream requester has line in  
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has  
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has  
exclusive access";


 // Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write,   desk="UC + RSC";
-UC_RU, AccessPermission:Invalid,   desk="UC + RU";
-UD_RU, AccessPermission:Invalid,   desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write,   desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write,   desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write,   desc="UC + RSC";
+UC_RU, AccessPermission:Invalid,   desc="UC + RU";
+UD_RU, AccessPermission:Invalid,   desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write,   desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write,   desc="UD + RSC";

 // Generic transient state
 // There is only a transient "BUSY" state. The actions taken at this  
state

@@ -261,90 +261,90 @@

 // Events triggered by sequencer requests or snoops in the rdy queue
 // See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-WriteUniqueFull_PoC_Alloc;
-SnpCleanInvalid;
-SnpShared;
-SnpSharedFwd;
-SnpNotSharedDirtyFwd;
-SnpUnique;
-SnpUniqueFwd;
-SnpOnce;
-SnpOnceFwd;
-SnpStalled; // A

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Minimally implement reading MiscRegs for the CortexR52.

2021-05-27 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46139 )



Change subject: fastmodel: Minimally implement reading MiscRegs for the  
CortexR52.

..

fastmodel: Minimally implement reading MiscRegs for the CortexR52.

This currently supports only the CPSR and SPSR currently. The CPSR is
needed to be able to read the PC since that also reads other related
info which ultimately comes from the CPSR. The SPSR is also set up
since it was easy to do at the same time.

Change-Id: I977fde47c81927f4972d4da2e781df306dfa3f4e
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 647 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc  
b/src/arch/arm/fastmodel/CortexR52/thread_context.cc

index 4ad449d..0b1bf66 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -87,6 +87,8 @@

 pcRscId = extractResourceId(resources, "R15");

+extractResourceMap(miscRegIds, resources, miscRegIdxNameMap);
+
 extractResourceMap(intReg32Ids, resources, intReg32IdxNameMap);
 extractResourceMap(ccRegIds, resources, ccRegIdxNameMap);
 }
@@ -165,6 +167,642 @@
 return bpSpaceIds;
 }

+Iris::ThreadContext::IdxNameMap CortexR52TC::miscRegIdxNameMap({
+{ ArmISA::MISCREG_CPSR, "CPSR" },
+{ ArmISA::MISCREG_SPSR, "SPSR" },
+// ArmISA::MISCREG_SPSR_FIQ?
+// ArmISA::MISCREG_SPSR_IRQ?
+// ArmISA::MISCREG_SPSR_SVC?
+// ArmISA::MISCREG_SPSR_MON?
+// ArmISA::MISCREG_SPSR_ABT?
+// ArmISA::MISCREG_SPSR_HYP?
+// ArmISA::MISCREG_SPSR_UND?
+// ArmISA::MISCREG_ELR_HYP?
+// ArmISA::MISCREG_FPSID?
+// ArmISA::MISCREG_FPSCR?
+// ArmISA::MISCREG_MVFR1?
+// ArmISA::MISCREG_MVFR0?
+// ArmISA::MISCREG_FPEXC?
+
+// Helper registers
+// ArmISA::MISCREG_CPSR_MODE?
+// ArmISA::MISCREG_CPSR_Q?
+// ArmISA::MISCREG_FPSCR_EXC?
+// ArmISA::MISCREG_FPSCR_QC?
+// ArmISA::MISCREG_LOCKADDR?
+// ArmISA::MISCREG_LOCKFLAG?
+// ArmISA::MISCREG_PRRR_MAIR0?
+// ArmISA::MISCREG_PRRR_MAIR0_NS?
+// ArmISA::MISCREG_PRRR_MAIR0_S?
+// ArmISA::MISCREG_NMRR_MAIR1?
+// ArmISA::MISCREG_NMRR_MAIR1_NS?
+// ArmISA::MISCREG_NMRR_MAIR1_S?
+// ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR?
+// ArmISA::MISCREG_SCTLR_RST?
+// ArmISA::MISCREG_SEV_MAILBOX?
+
+// AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
+// ArmISA::MISCREG_DBGDIDR?
+// ArmISA::MISCREG_DBGDSCRint?
+// ArmISA::MISCREG_DBGDCCINT?
+// ArmISA::MISCREG_DBGDTRTXint?
+// ArmISA::MISCREG_DBGDTRRXint?
+// ArmISA::MISCREG_DBGWFAR?
+// ArmISA::MISCREG_DBGVCR?
+// ArmISA::MISCREG_DBGDTRRXext?
+// ArmISA::MISCREG_DBGDSCRext?
+// ArmISA::MISCREG_DBGDTRTXext?
+// ArmISA::MISCREG_DBGOSECCR?
+// ArmISA::MISCREG_DBGBVR0?
+// ArmISA::MISCREG_DBGBVR1?
+// ArmISA::MISCREG_DBGBVR2?
+// ArmISA::MISCREG_DBGBVR3?
+// ArmISA::MISCREG_DBGBVR4?
+// ArmISA::MISCREG_DBGBVR5?
+// ArmISA::MISCREG_DBGBCR0?
+// ArmISA::MISCREG_DBGBCR1?
+// ArmISA::MISCREG_DBGBCR2?
+// ArmISA::MISCREG_DBGBCR3?
+// ArmISA::MISCREG_DBGBCR4?
+// ArmISA::MISCREG_DBGBCR5?
+// ArmISA::MISCREG_DBGWVR0?
+// ArmISA::MISCREG_DBGWVR1?
+// ArmISA::MISCREG_DBGWVR2?
+// ArmISA::MISCREG_DBGWVR3?
+// ArmISA::MISCREG_DBGWCR0?
+// ArmISA::MISCREG_DBGWCR1?
+// ArmISA::MISCREG_DBGWCR2?
+// ArmISA::MISCREG_DBGWCR3?
+// ArmISA::MISCREG_DBGDRAR?
+// ArmISA::MISCREG_DBGBXVR4?
+// ArmISA::MISCREG_DBGBXVR5?
+// ArmISA::MISCREG_DBGOSLAR?
+// ArmISA::MISCREG_DBGOSLSR?
+// ArmISA::MISCREG_DBGOSDLR?
+// ArmISA::MISCREG_DBGPRCR?
+// ArmISA::MISCREG_DBGDSAR?
+// ArmISA::MISCREG_DBGCLAIMSET?
+// ArmISA::MISCREG_DBGCLAIMCLR?
+// ArmISA::MISCREG_DBGAUTHSTATUS?
+// ArmISA::MISCREG_DBGDEVID2?
+// ArmISA::MISCREG_DBGDEVID1?
+// ArmISA::MISCREG_DBGDEVID0?
+// ArmISA::MISCREG_TEECR? not in ARM DDI 0487A.b+
+// ArmISA::MISCREG_JIDR?
+// ArmISA::MISCREG_TEEHBR? not in ARM DDI 0487A.b+
+// ArmISA::MISCREG_JOSCR?
+// ArmISA::MISCREG_JMCR?
+
+// AArch32 CP15 registers (system control)
+// ArmISA::MISCREG_MIDR?
+// ArmISA::MISCREG_CTR?
+// ArmISA::MISCREG_TCMTR?
+// ArmISA::MISCREG_TLBTR?
+// ArmISA::MISCREG_MPIDR?
+// ArmISA::MISCREG_REVIDR?
+// ArmISA::MISCREG_ID_PFR0?
+//

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Fix parenthesis in condition

2021-05-27 Thread Jason Lowe-Power (Gerrit) via gem5-dev 
Jason Lowe-Power has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46039 )


Change subject: cpu-o3: Fix parenthesis in condition
..

cpu-o3: Fix parenthesis in condition

The commit which removed the templates from fetch [1] made a mistake in
removing parentheses in a condition to get a line under 80 characters.
With this change, the O3 Arm tests pass again.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/42109

Change-Id: I3c224c59a05f08b0639aadb913401a719a82e26f
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46039
Maintainer: Jason Lowe-Power 
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Gabe Black 
Reviewed-by: Matt Sinclair 
Reviewed-by: Hoa Nguyen 
Tested-by: kokoro 
---
M src/cpu/o3/fetch.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Matt Sinclair: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Hoa Nguyen: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 8b0febb..65ed33f 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -1151,7 +1151,7 @@
 else
 ++fetchStats.miscStallCycles;
 return;
-} else if (checkInterrupt(thisPC.instAddr()  
&& !delayedCommit[tid])) {
+} else if (checkInterrupt(thisPC.instAddr())  
&& !delayedCommit[tid]) {

 // Stall CPU if an interrupt is posted and we're not issuing
 // an delayed commit micro-op currently (delayed commit
 // instructions are not interruptable by interrupts, only  
faults)


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3c224c59a05f08b0639aadb913401a719a82e26f
Gerrit-Change-Number: 46039
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: replace desks, add desc where required

2021-05-27 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46119 )



Change subject: mem-ruby: replace desks, add desc where required
..

mem-ruby: replace desks, add desc where required

Events in *.sm are required to have "desc" defined.

JIRA: https://gem5.atlassian.net/browse/GEM5-999

Change-Id: I95f59c422bdd264a9e1077b75bf7a0e9f39685aa
Signed-off-by: Hoa Nguyen 
---
M src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
M src/mem/ruby/protocol/chi/CHI-mem.sm
3 files changed, 114 insertions(+), 114 deletions(-)



diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm  
b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm

index 03010d5..3b4a801 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -114,7 +114,7 @@
 DMA_WRITE_PARTIAL, desc="DMA Write partial line";
 DMA_ACK,   desc="DMA Ack";
 Data,  desc="Data to directory";
-All_Acks,  desk="All pending acks, unblocks, etc have been  
received";
+All_Acks,  desc="All pending acks, unblocks, etc have been  
received";

   }

   // TYPES
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 160f674..a0d1888 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -206,7 +206,7 @@
   state_declaration(State, default="Cache_State_null") {
 // Stable states

-I, AccessPermission:Invalid,desk="Invalid / not present locally or  
upstream";
+I, AccessPermission:Invalid,desc="Invalid / not present locally or  
upstream";


 // States when block is present in local cache only
 SC, AccessPermission:Read_Only, desc="Shared Clean";
@@ -216,21 +216,21 @@
 UD_T, AccessPermission:Read_Write,  desc="UD with use timeout";

 // Invalid in local cache but present in upstream caches
-RU, AccessPermission:Invalid,   desk="Upstream requester has line in  
UD/UC";
-RSC, AccessPermission:Invalid,  desk="Upstream requester has line in  
SC";
-RSD, AccessPermission:Invalid,  desk="Upstream requester has line in  
SD and maybe SC";
-RUSC, AccessPermission:Invalid, desk="RSC + this node stills has  
exclusive access";
-RUSD, AccessPermission:Invalid, desk="RSD + this node stills has  
exclusive access";
+RU, AccessPermission:Invalid,   desc="Upstream requester has line in  
UD/UC";
+RSC, AccessPermission:Invalid,  desc="Upstream requester has line in  
SC";
+RSD, AccessPermission:Invalid,  desc="Upstream requester has line in  
SD and maybe SC";
+RUSC, AccessPermission:Invalid, desc="RSC + this node stills has  
exclusive access";
+RUSD, AccessPermission:Invalid, desc="RSD + this node stills has  
exclusive access";


 // Both in local and upstream caches. In some cases local maybe stale
-SC_RSC, AccessPermission:Read_Only,desk="SC + RSC";
-SD_RSC, AccessPermission:Read_Only,desk="SD + RSC";
-SD_RSD, AccessPermission:Read_Only,desk="SD + RSD";
-UC_RSC, AccessPermission:Read_Write,   desk="UC + RSC";
-UC_RU, AccessPermission:Invalid,   desk="UC + RU";
-UD_RU, AccessPermission:Invalid,   desk="UD + RU";
-UD_RSD, AccessPermission:Read_Write,   desk="UD + RSD";
-UD_RSC, AccessPermission:Read_Write,   desk="UD + RSC";
+SC_RSC, AccessPermission:Read_Only,desc="SC + RSC";
+SD_RSC, AccessPermission:Read_Only,desc="SD + RSC";
+SD_RSD, AccessPermission:Read_Only,desc="SD + RSD";
+UC_RSC, AccessPermission:Read_Write,   desc="UC + RSC";
+UC_RU, AccessPermission:Invalid,   desc="UC + RU";
+UD_RU, AccessPermission:Invalid,   desc="UD + RU";
+UD_RSD, AccessPermission:Read_Write,   desc="UD + RSD";
+UD_RSC, AccessPermission:Read_Write,   desc="UD + RSC";

 // Generic transient state
 // There is only a transient "BUSY" state. The actions taken at this  
state

@@ -261,90 +261,90 @@

 // Events triggered by sequencer requests or snoops in the rdy queue
 // See CHIRequestType in CHi-msg.sm for descriptions
-Load;
-Store;
-Prefetch;
-ReadShared;
-ReadNotSharedDirty;
-ReadUnique;
-ReadUnique_PoC;
-ReadOnce;
-CleanUnique;
-Evict;
-WriteBackFull;
-WriteEvictFull;
-WriteCleanFull;
-WriteUnique;
-WriteUniquePtl_PoC;
-WriteUniqueFull_PoC;
-WriteUniqueFull_PoC_Alloc;
-SnpCleanInvalid;
-SnpShared;
-SnpSharedFwd;
-SnpNotSharedDirtyFwd;
-SnpUnique;
-SnpUniqueFwd;
-SnpOnce;
-SnpOnceFwd;
-SnpStalled; // A snoop stall triggered from the inport
+Load,desc="";
+Store,   desc="";
+Prefetch,desc="";
+ReadShared,  desc="";
+ReadNotSharedDirty,  desc="";
+

[gem5-dev] Change in gem5/gem5[develop]: configs: fix se.py error when using "--redirects"

2021-05-27 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46099 )



Change subject: configs: fix se.py error when using "--redirects"
..

configs: fix se.py error when using "--redirects"

Currently, the workload is initialized before host filesystem
redirections take place (i.e. before --redirects is taken into
account).

This change moves the initialization of the workload to the place
when the redirections have taken place.

Change-Id: Id8f4c8486b4e0adb19ccc25d02d0c28cbf671063
Signed-off-by: Hoa Nguyen 
---
M configs/example/se.py
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/configs/example/se.py b/configs/example/se.py
index 891dd72..d42d147 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -166,8 +166,7 @@
 system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
 mem_mode = test_mem_mode,
 mem_ranges = [AddrRange(args.mem_size)],
-cache_line_size = args.cacheline_size,
-workload = SEWorkload.init_compatible(mp0_path))
+cache_line_size = args.cacheline_size)

 if numThreads > 1:
 system.multi_thread = True
@@ -262,6 +261,8 @@
 MemConfig.config_mem(args, system)
 config_filesystem(system, args)

+system.workload = SEWorkload.init_compatible(mp0_path))
+
 if args.wait_gdb:
 for cpu in system.cpu:
 cpu.wait_for_remote_gdb = True

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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix test names in guest ABI unit test

2021-05-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/46059 )


Change subject: sim: Fix test names in guest ABI unit test
..

sim: Fix test names in guest ABI unit test

Fix test names that were incorrectly sed'ed. Instead of
reversing, we have added a Test suffix as it is the
predominant approach among unit tests.

Change-Id: I4f5e9539de7646dee6c1e40076f18595d591dabf
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46059
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/sim/guest_abi.test.cc
1 file changed, 7 insertions(+), 7 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/guest_abi.test.cc b/src/sim/guest_abi.test.cc
index 3dbe60f..19f3c30 100644
--- a/src/sim/guest_abi.test.cc
+++ b/src/sim/guest_abi.test.cc
@@ -292,7 +292,7 @@


 // The actual test bodies.
-TEST(guest_abi, ABI_1D_args)
+TEST(GuestABITest, ABI_1D_args)
 {
 ThreadContext tc;
 invokeSimcall(, testIntVoid);
@@ -300,14 +300,14 @@
 EXPECT_EQ(tc.floatResult, tc.DefaultFloatResult);
 }

-TEST(guest_abi, ABI_Prepare)
+TEST(GuestABITest, ABI_Prepare)
 {
 ThreadContext tc;
 invokeSimcall(, testPrepareVoid);
 invokeSimcall(, testPrepareInt);
 }

-TEST(guest_abi, ABI_2D_args)
+TEST(GuestABITest, ABI_2D_args)
 {
 ThreadContext tc;
 invokeSimcall(, test2DVoid);
@@ -315,14 +315,14 @@
 EXPECT_EQ(tc.floatResult, tc.DefaultFloatResult);
 }

-TEST(guest_abi, ABI_TC_init)
+TEST(GuestABITest, ABI_TC_init)
 {
 ThreadContext tc;
 tc.intOffset = 2;
 invokeSimcall(, testTcInit);
 }

-TEST(guest_abi, ABI_returns)
+TEST(GuestABITest, ABI_returns)
 {
 // 1D returns.
 {
@@ -380,14 +380,14 @@
 }
 }

-TEST(guest_abi, dumpSimcall)
+TEST(GuestABITest, dumpSimcall)
 {
 ThreadContext tc;
 std::string dump = dumpSimcall("test", , testIntVoid);
 EXPECT_EQ(dump, "test(0, 11, 2, 13, ...)");
 }

-TEST(guest_abi, isVarArgs)
+TEST(GuestABITest, isVarArgs)
 {
 EXPECT_TRUE(guest_abi::IsVarArgs>::value);
 EXPECT_FALSE(guest_abi::IsVarArgs::value);



1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4f5e9539de7646dee6c1e40076f18595d591dabf
Gerrit-Change-Number: 46059
Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: mem: Rename QoS namespace as qos

2021-05-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45404 )


Change subject: mem: Rename QoS namespace as qos
..

mem: Rename QoS namespace as qos

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::QoS became ::qos.

Fixed some incorrect occurrences of the class name
on debug prints.

Change-Id: I163eae14e1e343384faa22af08570cfb81ae6fb6
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45404
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
Reviewed-by: Hoa Nguyen 
---
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/qos/QoSMemCtrl.py
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qos/QoSPolicy.py
M src/mem/qos/QoSTurnaround.py
M src/mem/qos/mem_ctrl.cc
M src/mem/qos/mem_ctrl.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qos/policy.cc
M src/mem/qos/policy.hh
M src/mem/qos/policy_fixed_prio.cc
M src/mem/qos/policy_fixed_prio.hh
M src/mem/qos/policy_pf.cc
M src/mem/qos/policy_pf.hh
M src/mem/qos/q_policy.cc
M src/mem/qos/q_policy.hh
M src/mem/qos/turnaround_policy.hh
M src/mem/qos/turnaround_policy_ideal.cc
M src/mem/qos/turnaround_policy_ideal.hh
21 files changed, 114 insertions(+), 76 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index 1816c63..6f871b1 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -50,7 +50,7 @@
 #include "sim/system.hh"

 MemCtrl::MemCtrl(const MemCtrlParams ) :
-QoS::MemCtrl(p),
+qos::MemCtrl(p),
 port(name() + ".port", *this), isTimingMode(false),
 retryRdReq(false), retryWrReq(false),
 nextReqEvent([this]{ processNextReqEvent(); }, name()),
@@ -1393,7 +1393,7 @@
 MemCtrl::getPort(const std::string _name, PortID idx)
 {
 if (if_name != "port") {
-return QoS::MemCtrl::getPort(if_name, idx);
+return qos::MemCtrl::getPort(if_name, idx);
 } else {
 return port;
 }
diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh
index dd13e3c..ec2459b 100644
--- a/src/mem/mem_ctrl.hh
+++ b/src/mem/mem_ctrl.hh
@@ -233,7 +233,7 @@
  * please cite the paper.
  *
  */
-class MemCtrl : public QoS::MemCtrl
+class MemCtrl : public qos::MemCtrl
 {
   private:

diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py
index e4826d6..71cb903 100644
--- a/src/mem/qos/QoSMemCtrl.py
+++ b/src/mem/qos/QoSMemCtrl.py
@@ -44,7 +44,7 @@
 class QoSMemCtrl(ClockedObject):
 type = 'QoSMemCtrl'
 cxx_header = "mem/qos/mem_ctrl.hh"
-cxx_class = 'QoS::MemCtrl'
+cxx_class = 'qos::MemCtrl'
 abstract = True

 system = Param.System(Parent.any, "System that the controller belongs  
to.")

diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py
index fafac64..42a4ea7 100644
--- a/src/mem/qos/QoSMemSinkCtrl.py
+++ b/src/mem/qos/QoSMemSinkCtrl.py
@@ -42,7 +42,7 @@
 class QoSMemSinkCtrl(QoSMemCtrl):
 type = 'QoSMemSinkCtrl'
 cxx_header = "mem/qos/mem_sink.hh"
-cxx_class = "QoS::MemSinkCtrl"
+cxx_class = "qos::MemSinkCtrl"
 port = ResponsePort("Response ports")


diff --git a/src/mem/qos/QoSPolicy.py b/src/mem/qos/QoSPolicy.py
index 6e9e90e..f202413 100644
--- a/src/mem/qos/QoSPolicy.py
+++ b/src/mem/qos/QoSPolicy.py
@@ -41,12 +41,12 @@
 type = 'QoSPolicy'
 abstract = True
 cxx_header = "mem/qos/policy.hh"
-cxx_class = 'QoS::Policy'
+cxx_class = 'qos::Policy'

 class QoSFixedPriorityPolicy(QoSPolicy):
 type = 'QoSFixedPriorityPolicy'
 cxx_header = "mem/qos/policy_fixed_prio.hh"
-cxx_class = 'QoS::FixedPriorityPolicy'
+cxx_class = 'qos::FixedPriorityPolicy'

 cxx_exports = [
 PyBindMethod('initRequestorName'),
@@ -90,7 +90,7 @@
 class QoSPropFairPolicy(QoSPolicy):
 type = 'QoSPropFairPolicy'
 cxx_header = "mem/qos/policy_pf.hh"
-cxx_class = 'QoS::PropFairPolicy'
+cxx_class = 'qos::PropFairPolicy'

 cxx_exports = [
 PyBindMethod('initRequestorName'),
diff --git a/src/mem/qos/QoSTurnaround.py b/src/mem/qos/QoSTurnaround.py
index 3b3991f..4ea9c26 100644
--- a/src/mem/qos/QoSTurnaround.py
+++ b/src/mem/qos/QoSTurnaround.py
@@ -39,10 +39,10 @@
 class QoSTurnaroundPolicy(SimObject):
 type = 'QoSTurnaroundPolicy'
 cxx_header = "mem/qos/turnaround_policy.hh"
-cxx_class = 'QoS::TurnaroundPolicy'
+cxx_class = 'qos::TurnaroundPolicy'
 abstract = True

 class QoSTurnaroundPolicyIdeal(QoSTurnaroundPolicy):
 type = 'QoSTurnaroundPolicyIdeal'
 cxx_header = "mem/qos/turnaround_policy_ideal.hh"
-cxx_class = 'QoS::TurnaroundPolicyIdeal'
+cxx_class = 'qos::TurnaroundPolicyIdeal'
diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index 270cfd3..7a5a524 100644
--- a/src/mem/qos/mem_ctrl.cc
+++

[gem5-dev] Change in gem5/gem5[develop]: mem: Rename ReplacementPolicy namespace as replacement_policy

2021-05-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45405 )


Change subject: mem: Rename ReplacementPolicy namespace as  
replacement_policy

..

mem: Rename ReplacementPolicy namespace as replacement_policy

As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ReplacementPolicy became ::replacement_policy.

Change-Id: Id46cd9d89e9424fd3c5484e2f9c69ef2b73f135b
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45405
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
Reviewed-by: Hoa Nguyen 
---
M src/mem/cache/prefetch/associative_set.hh
M src/mem/cache/prefetch/associative_set_impl.hh
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/replacement_policies/ReplacementPolicies.py
M src/mem/cache/replacement_policies/base.hh
M src/mem/cache/replacement_policies/bip_rp.cc
M src/mem/cache/replacement_policies/bip_rp.hh
M src/mem/cache/replacement_policies/brrip_rp.cc
M src/mem/cache/replacement_policies/brrip_rp.hh
M src/mem/cache/replacement_policies/fifo_rp.cc
M src/mem/cache/replacement_policies/fifo_rp.hh
M src/mem/cache/replacement_policies/lfu_rp.cc
M src/mem/cache/replacement_policies/lfu_rp.hh
M src/mem/cache/replacement_policies/lru_rp.cc
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.cc
M src/mem/cache/replacement_policies/mru_rp.hh
M src/mem/cache/replacement_policies/random_rp.cc
M src/mem/cache/replacement_policies/random_rp.hh
M src/mem/cache/replacement_policies/replaceable_entry.hh
M src/mem/cache/replacement_policies/second_chance_rp.cc
M src/mem/cache/replacement_policies/second_chance_rp.hh
M src/mem/cache/replacement_policies/tree_plru_rp.cc
M src/mem/cache/replacement_policies/tree_plru_rp.hh
M src/mem/cache/replacement_policies/weighted_lru_rp.cc
M src/mem/cache/replacement_policies/weighted_lru_rp.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/sector_tags.hh
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
30 files changed, 120 insertions(+), 71 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/cache/prefetch/associative_set.hh  
b/src/mem/cache/prefetch/associative_set.hh

index 61fd1f6..d349dc0 100644
--- a/src/mem/cache/prefetch/associative_set.hh
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -55,7 +55,7 @@
 /** Pointer to the indexing policy */
 BaseIndexingPolicy* const indexingPolicy;
 /** Pointer to the replacement policy */
-ReplacementPolicy::Base* const replacementPolicy;
+replacement_policy::Base* const replacementPolicy;
 /** Vector containing the entries of the container */
 std::vector entries;

@@ -70,7 +70,7 @@
  * @param init_val initial value of the elements of the set
  */
 AssociativeSet(int assoc, int num_entries, BaseIndexingPolicy  
*idx_policy,
-ReplacementPolicy::Base *rpl_policy, Entry const _val =  
Entry());
+replacement_policy::Base *rpl_policy, Entry const _val =  
Entry());


 /**
  * Find an entry within the set
diff --git a/src/mem/cache/prefetch/associative_set_impl.hh  
b/src/mem/cache/prefetch/associative_set_impl.hh

index 4b16dbb..6118009 100644
--- a/src/mem/cache/prefetch/associative_set_impl.hh
+++ b/src/mem/cache/prefetch/associative_set_impl.hh
@@ -34,7 +34,7 @@

 template
 AssociativeSet::AssociativeSet(int assoc, int num_entries,
-BaseIndexingPolicy *idx_policy, ReplacementPolicy::Base  
*rpl_policy,
+BaseIndexingPolicy *idx_policy, replacement_policy::Base  
*rpl_policy,

 Entry const _value)
   : associativity(assoc), numEntries(num_entries),  
indexingPolicy(idx_policy),

 replacementPolicy(rpl_policy), entries(numEntries, init_value)
diff --git a/src/mem/cache/prefetch/stride.hh  
b/src/mem/cache/prefetch/stride.hh

index 36fc194..077a035 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -61,7 +61,9 @@
 #include "params/StridePrefetcherHashedSetAssociative.hh"

 class BaseIndexingPolicy;
-namespace ReplacementPolicy {
+GEM5_DEPRECATED_NAMESPACE(ReplacementPolicy, replacement_policy);
+namespace replacement_policy
+{
 class Base;
 }
 struct StridePrefetcherParams;
@@ -109,14 +111,13 @@
 const int numEntries;

 BaseIndexingPolicy* const indexingPolicy;
-ReplacementPolicy::Base* const replacementPolicy;
+replacement_policy::Base* const replacementPolicy;

 PCTableInfo(int assoc, int num_entries,
 BaseIndexingPolicy* indexing_policy,
-ReplacementPolicy::Base* replacement_policy)
+replacement_policy::Base* repl_policy)
   : assoc(assoc), numEntries(num_entries),
-

[gem5-dev] Change in gem5/gem5[develop]: mem: Rename qos variables as _qos

2021-05-27 Thread Daniel Carvalho (Gerrit) via gem5-dev 
Daniel Carvalho has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/45403 )


Change subject: mem: Rename qos variables as _qos
..

mem: Rename qos variables as _qos

Pave the way for a qos namespace.

Change-Id: I2c225c4c6005846a0253b7df68d874498502d0f5
Signed-off-by: Daniel R. Carvalho 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45403
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
Reviewed-by: Hoa Nguyen 
---
M src/mem/qos/mem_ctrl.cc
1 file changed, 25 insertions(+), 25 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/qos/mem_ctrl.cc b/src/mem/qos/mem_ctrl.cc
index 8de78cb..270cfd3 100644
--- a/src/mem/qos/mem_ctrl.cc
+++ b/src/mem/qos/mem_ctrl.cc
@@ -81,7 +81,7 @@
 {}

 void
-MemCtrl::logRequest(BusState dir, RequestorID id, uint8_t qos,
+MemCtrl::logRequest(BusState dir, RequestorID id, uint8_t _qos,
 Addr addr, uint64_t entries)
 {
 // If needed, initialize all counters and statistics
@@ -92,31 +92,31 @@
 "QoSMemCtrl::logRequest REQUESTOR %s [id %d] address %d"
 " prio %d this requestor q packets %d"
 " - queue size %d - requested entries %d\n",
-requestors[id], id, addr, qos, packetPriorities[id][qos],
-(dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos],
+requestors[id], id, addr, _qos, packetPriorities[id][_qos],
+(dir == READ) ? readQueueSizes[_qos]: writeQueueSizes[_qos],
 entries);

 if (dir == READ) {
-readQueueSizes[qos] += entries;
+readQueueSizes[_qos] += entries;
 totalReadQueueSize += entries;
 } else if (dir == WRITE) {
-writeQueueSizes[qos] += entries;
+writeQueueSizes[_qos] += entries;
 totalWriteQueueSize += entries;
 }

-packetPriorities[id][qos] += entries;
+packetPriorities[id][_qos] += entries;
 for (auto j = 0; j < entries; ++j) {
 requestTimes[id][addr].push_back(curTick());
 }

 // Record statistics
-stats.avgPriority[id].sample(qos);
+stats.avgPriority[id].sample(_qos);

 // Compute avg priority distance

 for (uint8_t i = 0; i < packetPriorities[id].size(); ++i) {
 uint8_t distance =
-(abs(int(qos) - int(i))) * packetPriorities[id][i];
+(abs(int(_qos) - int(i))) * packetPriorities[id][i];

 if (distance > 0) {
 stats.avgPriorityDistance[id].sample(distance);
@@ -132,13 +132,13 @@
 DPRINTF(QOS,
 "QoSMemCtrl::logRequest REQUESTOR %s [id %d] prio %d "
 "this requestor q packets %d - new queue size %d\n",
-requestors[id], id, qos, packetPriorities[id][qos],
-(dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos]);
+requestors[id], id, _qos, packetPriorities[id][_qos],
+(dir == READ) ? readQueueSizes[_qos]: writeQueueSizes[_qos]);

 }

 void
-MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t qos,
+MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t _qos,
  Addr addr, uint64_t entries, double delay)
 {
 panic_if(!hasRequestor(id),
@@ -148,23 +148,23 @@
 "QoSMemCtrl::logResponse REQUESTOR %s [id %d] address %d prio"
 " %d this requestor q packets %d"
 " - queue size %d - requested entries %d\n",
-requestors[id], id, addr, qos, packetPriorities[id][qos],
-(dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos],
+requestors[id], id, addr, _qos, packetPriorities[id][_qos],
+(dir == READ) ? readQueueSizes[_qos]: writeQueueSizes[_qos],
 entries);

 if (dir == READ) {
-readQueueSizes[qos] -= entries;
+readQueueSizes[_qos] -= entries;
 totalReadQueueSize -= entries;
 } else if (dir == WRITE) {
-writeQueueSizes[qos] -= entries;
+writeQueueSizes[_qos] -= entries;
 totalWriteQueueSize -= entries;
 }

-panic_if(packetPriorities[id][qos] == 0,
+panic_if(packetPriorities[id][_qos] == 0,
  "QoSMemCtrl::logResponse requestor %s negative packets "
- "for priority %d", requestors[id], qos);
+ "for priority %d", requestors[id], _qos);

-packetPriorities[id][qos] -= entries;
+packetPriorities[id][_qos] -= entries;

 for (auto j = 0; j < entries; ++j) {
 auto it = requestTimes[id].find(addr);
@@ -188,13 +188,13 @@

 if (latency > 0) {
 // Record per-priority latency stats
-if (stats.priorityMaxLatency[qos].value() < latency) {
-stats.priorityMaxLatency[qos] = latency;
+if (stats.priorityMaxLatency[_qos].value() < latency) {
+stats.priorityMaxLatency[_qos] = latency;
 }

-

[gem5-dev] Jenkins build is back to normal : compiler-checks #76

2021-05-27 Thread jenkins-no-reply--- via gem5-dev 
See 

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