[gem5-dev] Change in gem5/gem5[develop]: stdlib: Call `setup_memory_ranges()` from the constructor
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/52883 ) Change subject: stdlib: Call `setup_memory_ranges()` from the constructor .. stdlib: Call `setup_memory_ranges()` from the constructor `setup_memory_ranges()`, now `_setup_memory_ranges()`, had to be called by subclasses. Since `setup_memory_ranges() was always called at the top of the `_setup_board()` function (or could be), this function is now automatically called within the AbstractBoard's constructor prior to `_setup_board` and `_connect_things`. Change-Id: I6bf3231666b86059ffc484cfca44e45cfde52ea6 --- M src/python/gem5/components/boards/simple_board.py M src/python/gem5/components/boards/riscv_board.py M src/python/gem5/components/boards/test_board.py M src/python/gem5/components/boards/x86_board.py M src/python/gem5/components/boards/abstract_board.py 5 files changed, 41 insertions(+), 24 deletions(-) diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index 4055e17..a27cecd 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -86,6 +86,8 @@ self.memory = memory self.cache_hierarchy = cache_hierarchy +# Setup the board and memory system's memory ranges. +self._setup_memory_ranges() # Setup board properties unique to the board being constructed. self._setup_board() @@ -143,8 +145,9 @@ """ This function is called in the AbstractBoard constructor, before the memory, processor, and cache hierarchy components are incorporated via -`_connect_thing()`. This function should be overridden by boards to -specify components, connections unique to that board. +`_connect_thing()`, but after the `_setup_memory_ranges()` function. +This function should be overridden by boards to specify components, +connections unique to that board. """ raise NotImplementedError @@ -212,18 +215,24 @@ raise NotImplementedError @abstractmethod -def setup_memory_ranges(self) -> None: +def _setup_memory_ranges(self) -> None: """ -Set the memory ranges for this board. +Set the memory ranges for this board and memory system. -This is called by at the end of the constructor. It can query the -board's memory to determine the size and the set the memory ranges on -the memory if it needs to move the memory devices. +This is called in the constructor, prior to `_setup_board` and +`_connect_things`. It should query the board's memory to determine the +size and the set the memory ranges on the memory system and on the +board. -The simplest implementation just sets the board's memory range to be -the size of memory and memory's memory range to be the same as the -board. Full system implementations will likely need something more -complicated. +The simplest implementation sets the board's memory range to the size +of memory and memory system's range to be the same as the board. Full +system implementations will likely need something more complicated. + +Notes +- +* This *must* be called prior to the incorporation of the cache +hierarchy (via `_connect_things`) as cache hierarchies depend upon +knowing the memory system's ranges. """ raise NotImplementedError diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index f64640c..8945f22 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -121,9 +121,6 @@ self._on_chip_devices = [self.platform.clint, self.platform.plic] self._off_chip_devices = [self.platform.uart, self.disk] -# Set up the memory ranges -self.setup_memory_ranges() - def _setup_io_devices(self) -> None: """Connect the I/O devices to the I/O bus""" @@ -189,7 +186,7 @@ return self.iobus.mem_side_ports @overrides(AbstractBoard) -def setup_memory_ranges(self): +def _setup_memory_ranges(self): memory = self.get_memory() mem_size = memory.get_size() self.mem_ranges = [AddrRange(start=0x8000, size=mem_size)] diff --git a/src/python/gem5/components/boards/simple_board.py b/src/python/gem5/components/boards/simple_board.py index c011132..d0f4f2a 100644 --- a/src/python/gem5/components/boards/simple_board.py +++ b/src/python/gem5/components/boards/simple_board.py @@ -67,8 +67,7 @@ @overrides(AbstractBoard) def _setup_board(self) -> None: -# Set up the memory ranges -
[gem5-dev] Change in gem5/gem5[develop]: arch: Add vec_reg.test & vec_pred_reg.test unittests
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44508 )
Change subject: arch: Add vec_reg.test & vec_pred_reg.test unittests
..
arch: Add vec_reg.test & vec_pred_reg.test unittests
Change-Id: Ieb85e0d35032585ead1e3b399f8eaf5dbc246d76
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44508
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/generic/SConscript
A src/arch/generic/vec_reg.test.cc
A src/arch/generic/vec_pred_reg.test.cc
3 files changed, 495 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index 70bb2de..8231ccf 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -50,6 +50,9 @@
"Page table walker state machine debugging")
DebugFlag('TLB')
+GTest('vec_reg.test', 'vec_reg.test.cc')
+GTest('vec_pred_reg.test', 'vec_pred_reg.test.cc')
+
if env['TARGET_ISA'] == 'null':
Return()
diff --git a/src/arch/generic/vec_pred_reg.test.cc
b/src/arch/generic/vec_pred_reg.test.cc
new file mode 100644
index 000..4cedb6e
--- /dev/null
+++ b/src/arch/generic/vec_pred_reg.test.cc
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include "arch/generic/vec_pred_reg.hh"
+#include "base/str.hh"
+
+using namespace gem5;
+
+TEST(VecPredReg, reset)
+{
+constexpr size_t size = 4;
+VecPredRegContainer vec;
+
+vec.reset();
+
+for (auto idx = 0; idx < size; idx++) {
+ASSERT_FALSE(vec[idx]);
+}
+}
+
+TEST(VecPredReg, set)
+{
+constexpr size_t size = 4;
+VecPredRegContainer vec;
+
+vec.set();
+
+for (auto idx = 0; idx < size; idx++) {
+ASSERT_TRUE(vec[idx]);
+}
+}
+
+template
+class TwoDifferentVecPredRegsBase : public testing::Test
+{
+ protected:
+static constexpr ssize_t size = 4;
+VecPredRegContainer pred1;
+VecPredRegContainer pred2;
+
+void
+SetUp() override
+{
+// Initializing with:
+// 0,1,0,1
+for (auto idx = 0; idx < size; idx++) {
+pred1[idx] = (idx % 2);
+}
+
+// Initializing with:
+// 1,0,1,0
+for (auto idx = 0; idx < size; idx++) {
+pred2[idx] = !(idx % 2);
+}
+}
+};
+
+using TwoDifferentVecPredRegs = TwoDifferentVecPredRegsBase;
+using TwoPackedDifferentVecPredRegs = TwoDifferentVecPredRegsBase;
+
+// Testing operator=
+TEST_F(TwoDifferentVecPredRegs, Assignment)
+{
+pred2 = pred1;
+
+for (auto idx = 0; idx < size; idx++) {
+ASSERT_EQ(pred2[idx], idx % 2);
+}
+}
+
+// Testing operator==
[gem5-dev] Change in gem5/gem5[develop]: configs: Replace master/slave terminology from configs scripts
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52866 )
Change subject: configs: Replace master/slave terminology from configs
scripts
..
configs: Replace master/slave terminology from configs scripts
Signed-off-by: Giacomo Travaglini
Change-Id: I6a1a06abeca1621efb378c400c5b24b33a7a3727
---
M configs/example/ruby_direct_test.py
M configs/common/GPUTLBConfig.py
M configs/common/MemConfig.py
M configs/example/ruby_random_test.py
M configs/common/FSConfig.py
M configs/common/HMC.py
M configs/nvm/sweep.py
M configs/common/CacheConfig.py
M configs/example/se.py
M configs/example/garnet_synth_traffic.py
M configs/example/memcheck.py
M configs/splash2/cluster.py
M configs/dram/low_power_sweep.py
M configs/nvm/sweep_hybrid.py
M configs/example/memtest.py
M configs/example/ruby_mem_test.py
M configs/example/etrace_replay.py
M configs/splash2/run.py
M configs/example/read_config.py
M configs/example/fs.py
M configs/example/hmctest.py
M configs/dram/lat_mem_rd.py
M configs/dram/sweep.py
M configs/example/hmc_hello.py
24 files changed, 178 insertions(+), 154 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index b270a83..4979f7d 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -122,8 +122,8 @@
**_get_cache_opts('l2', options))
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
-system.l2.cpu_side = system.tol2bus.master
-system.l2.mem_side = system.membus.slave
+system.l2.cpu_side = system.tol2bus.mem_side_ports
+system.l2.mem_side = system.membus.cpu_side_ports
if options.memchecker:
system.memchecker = MemChecker()
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index efb0af6..8b8fb4e 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -120,11 +120,11 @@
self.t1000.attachIO(self.iobus)
self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
AddrRange(Addr('2GB'), size ='256MB')]
-self.bridge.master = self.iobus.slave
-self.bridge.slave = self.membus.master
+self.bridge.mem_side_port = self.iobus.cpu_side_ports
+self.bridge.cpu_side_port = self.membus.mem_side_ports
self.disk0 = CowMmDisk()
self.disk0.childImage(mdesc.disks()[0])
-self.disk0.pio = self.iobus.master
+self.disk0.pio = self.iobus.mem_side_ports
# The puart0 and hvuart are placed on the IO bus, so create ranges
# for them. The remaining IO range is rather fragmented, so poke
@@ -160,12 +160,12 @@
self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
range=AddrRange(0x1f1200, size='8kB'))
-self.rom.port = self.membus.master
-self.nvram.port = self.membus.master
-self.hypervisor_desc.port = self.membus.master
-self.partition_desc.port = self.membus.master
+self.rom.port = self.membus.mem_side_ports
+self.nvram.port = self.membus.mem_side_ports
+self.hypervisor_desc.port = self.membus.mem_side_ports
+self.partition_desc.port = self.membus.mem_side_ports
-self.system_port = self.membus.slave
+self.system_port = self.membus.cpu_side_ports
self.workload = workload
@@ -189,10 +189,10 @@
self.iobus = IOXBar()
if not ruby:
self.bridge = Bridge(delay='50ns')
-self.bridge.master = self.iobus.slave
+self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
-self.bridge.slave = self.membus.master
+self.bridge.cpu_side_port = self.membus.mem_side_ports
self.mem_mode = mem_mode
@@ -299,13 +299,13 @@
# I/O traffic enters iobus
self.external_io = ExternalMaster(port_data="external_io",
port_type=external_memory)
-self.external_io.port = self.iobus.slave
+self.external_io.port = self.iobus.cpu_side_ports
# Ensure iocache only receives traffic destined for (actual)
memory.
self.iocache = ExternalSlave(port_data="iocache",
port_type=external_memory,
addr_ranges=self.mem_ranges)
-self.iocache.port = self.iobus.master
+self.iocache.port = self.iobus.mem_side_ports
# Let system_port get to nvmem and nothing else.
self.bridge.ranges = [self.realview.nvmem.range]
@@ -336,7 +336,7 @@
attach_9p(self.realview, self.iobus)
if not ruby:
-self.system_port = self.membus.slave
+self.system_port = self.membus.cpu_side_ports
if ruby:
if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
@@ -362,15 +362,15 @@
self.membus = MemBus()
self.bridge =
[gem5-dev] Change in gem5/gem5[develop]: configs: Replace master/slave terminology from ruby scripts
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52865 )
Change subject: configs: Replace master/slave terminology from ruby scripts
..
configs: Replace master/slave terminology from ruby scripts
Signed-off-by: Giacomo Travaglini
Change-Id: Iabc82a19e8d6c7cf619874dc2926276c349eba7c
---
M configs/ruby/MI_example.py
M configs/ruby/AMD_Base_Constructor.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/CHI_config.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MESI_Three_Level_HTM.py
M configs/ruby/Ruby.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MOESI_AMD_Base.py
11 files changed, 164 insertions(+), 155 deletions(-)
diff --git a/configs/ruby/AMD_Base_Constructor.py
b/configs/ruby/AMD_Base_Constructor.py
index cd4733b..1abc6d7 100644
--- a/configs/ruby/AMD_Base_Constructor.py
+++ b/configs/ruby/AMD_Base_Constructor.py
@@ -116,11 +116,11 @@
cp_cntrl.create(options, ruby_system, system)
# Connect the CP controllers to the ruby network
-cp_cntrl.requestFromCore = ruby_system.network.slave
-cp_cntrl.responseFromCore = ruby_system.network.slave
-cp_cntrl.unblockFromCore = ruby_system.network.slave
-cp_cntrl.probeToCore = ruby_system.network.master
-cp_cntrl.responseToCore = ruby_system.network.master
+cp_cntrl.requestFromCore = ruby_system.network.in_port
+cp_cntrl.responseFromCore = ruby_system.network.in_port
+cp_cntrl.unblockFromCore = ruby_system.network.in_port
+cp_cntrl.probeToCore = ruby_system.network.out_port
+cp_cntrl.responseToCore = ruby_system.network.out_port
exec("system.cp_cntrl%d = cp_cntrl" % i)
#
diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py
index 6507970..2d39659 100644
--- a/configs/ruby/CHI_config.py
+++ b/configs/ruby/CHI_config.py
@@ -351,7 +351,6 @@
self.__dict__['support_inst_reqs'] = True
# Compatibility with certain scripts that wire up ports
# without connectCpuPorts
-self.__dict__['slave'] = dseq.in_ports
self.__dict__['in_ports'] = dseq.in_ports
def connectCpuPorts(self, cpu):
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index 4088ecd..c184e57 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -173,16 +173,16 @@
# Connect the L1 controllers and the network
l1_cntrl.requestToL2 = MessageBuffer()
-l1_cntrl.requestToL2.master = ruby_system.network.slave
+l1_cntrl.requestToL2.out_port = ruby_system.network.in_port
l1_cntrl.responseToL2 = MessageBuffer()
-l1_cntrl.responseToL2.master = ruby_system.network.slave
+l1_cntrl.responseToL2.out_port = ruby_system.network.in_port
l1_cntrl.unblockToL2 = MessageBuffer()
-l1_cntrl.unblockToL2.master = ruby_system.network.slave
+l1_cntrl.unblockToL2.out_port = ruby_system.network.in_port
l1_cntrl.requestFromL2 = MessageBuffer()
-l1_cntrl.requestFromL2.slave = ruby_system.network.master
+l1_cntrl.requestFromL2.in_port = ruby_system.network.out_port
l1_cntrl.responseFromL2 = MessageBuffer()
-l1_cntrl.responseFromL2.slave = ruby_system.network.master
+l1_cntrl.responseFromL2.in_port = ruby_system.network.out_port
for j in range(num_l2caches_per_cluster):
@@ -203,18 +203,18 @@
# Connect the L2 controllers and the network
l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
-l2_cntrl.DirRequestFromL2Cache.master =
ruby_system.network.slave
+l2_cntrl.DirRequestFromL2Cache.out_port =
ruby_system.network.in_port
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
-l2_cntrl.L1RequestFromL2Cache.master =
ruby_system.network.slave
+l2_cntrl.L1RequestFromL2Cache.out_port =
ruby_system.network.in_port
l2_cntrl.responseFromL2Cache = MessageBuffer()
-l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
+l2_cntrl.responseFromL2Cache.out_port =
ruby_system.network.in_port
l2_cntrl.unblockToL2Cache = MessageBuffer()
-l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
+l2_cntrl.unblockToL2Cache.in_port =
ruby_system.network.out_port
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
-l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
+l2_cntrl.L1RequestToL2Cache.in_port =
ruby_system.network.out_port
l2_cntrl.responseToL2Cache = MessageBuffer()
-l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
+
[gem5-dev] Change in gem5/gem5[develop]: tests: Replace master/slave terminology from tests scripts
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/52863 ) Change subject: tests: Replace master/slave terminology from tests scripts .. tests: Replace master/slave terminology from tests scripts Signed-off-by: Giacomo Travaglini Change-Id: Id7aafc082c7e4cfc977e807141e63a3feb5a6348 --- M tests/gem5/memory/simple-run.py M tests/gem5/configs/base_config.py M tests/gem5/memory/memtest-run.py M tests/gem5/cpu_tests/run.py M tests/configs/memtest-filter.py M tests/configs/memtest.py 6 files changed, 41 insertions(+), 31 deletions(-) diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py index cce7397..23b7550 100644 --- a/tests/configs/memtest-filter.py +++ b/tests/configs/memtest-filter.py @@ -50,7 +50,7 @@ system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, snoop_filter = SnoopFilter()) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master +system.l2c.cpu_side = system.toL2Bus.mem_side_ports # connect l2c to membus system.l2c.mem_side = system.membus.slave @@ -66,7 +66,7 @@ system.system_port = system.membus.slave # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # --- diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index a957674..31ab14d 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -49,7 +49,7 @@ system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master +system.l2c.cpu_side = system.toL2Bus.mem_side_ports # connect l2c to membus system.l2c.mem_side = system.membus.slave @@ -65,7 +65,7 @@ system.system_port = system.membus.slave # connect memory to membus -system.physmem.port = system.membus.master +system.physmem.port = system.membus.mem_side_ports # --- diff --git a/tests/gem5/configs/base_config.py b/tests/gem5/configs/base_config.py index 9496f41..9867ede 100644 --- a/tests/gem5/configs/base_config.py +++ b/tests/gem5/configs/base_config.py @@ -108,8 +108,8 @@ system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave +system.l2c.cpu_side = system.toL2Bus.mem_side_ports +system.l2c.mem_side = system.membus.cpu_side_ports return system.toL2Bus def init_cpu(self, system, cpu, sha_bus): @@ -250,8 +250,8 @@ mem_mode = self.mem_mode, multi_thread = (self.num_threads > 1)) if not self.use_ruby: -system.system_port = system.membus.slave -system.physmem.port = system.membus.master +system.system_port = system.membus.cpu_side_ports +system.physmem.port = system.membus.mem_side_ports self.init_system(system) return system @@ -293,7 +293,7 @@ if self.use_ruby: # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. -system.iobus.master = system.ruby._io_port.slave +system.iobus.mem_side_ports = system.ruby._io_port.slave else: # create the memory controllers and connect them, stick with # the physmem name to avoid bumping all the reference stats @@ -308,12 +308,12 @@ system.physmem = [self.mem_class(range = r) for r in system.mem_ranges] for i in range(len(system.physmem)): -system.physmem[i].port = system.membus.master +system.physmem[i].port = system.membus.mem_side_ports # create the iocache, which by default runs at the system clock system.iocache = IOCache(addr_ranges=system.mem_ranges) -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave +system.iocache.cpu_side = system.iobus.mem_side_ports +system.iocache.mem_side = system.membus.cpu_side_ports def create_root(self): system = self.create_system() diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py index f6a1cf6..c17956e 100644 --- a/tests/gem5/cpu_tests/run.py +++ b/tests/gem5/cpu_tests/run.py @@ -43,7 +43,7 @@ def connectBus(self, bus): """Connect this cache to a memory-side bus""" -self.mem_side = bus.slave +self.mem_side = bus.cpu_side_ports def connectCPU(self, cpu): """Connect this cache's port to a
[gem5-dev] Change in gem5/gem5[develop]: learning_gem5: Replace master/slave terminology from learning_gem5 sc...
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/52864 ) Change subject: learning_gem5: Replace master/slave terminology from learning_gem5 scripts .. learning_gem5: Replace master/slave terminology from learning_gem5 scripts Signed-off-by: Giacomo Travaglini Change-Id: I6c30d18155acb151d732ae7e35e29f6facad78fd --- M configs/learning_gem5/part3/msi_caches.py M configs/learning_gem5/part3/ruby_caches_MI_example.py M configs/learning_gem5/part3/test_caches.py 3 files changed, 38 insertions(+), 27 deletions(-) diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py index 1614c46..957adf2 100644 --- a/configs/learning_gem5/part3/msi_caches.py +++ b/configs/learning_gem5/part3/msi_caches.py @@ -98,7 +98,7 @@ # Set up a proxy port for the system_port. Used for load binaries and # other functional-only things. self.sys_port_proxy = RubyPortProxy() -system.system_port = self.sys_port_proxy.slave +system.system_port = self.sys_port_proxy.in_ports # Connect the cpu's cache, interrupt, and TLB ports to Ruby for i,cpu in enumerate(cpus): @@ -155,18 +155,19 @@ # explicitly connected to anything. self.mandatoryQueue = MessageBuffer() -# All message buffers must be created and connected to the general -# Ruby network. In this case, "slave/master" don't mean the same thing -# as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out) -# then you use the "master", otherwise, the slave. +# All message buffers must be created and connected to the +# general Ruby network. In this case, "in_port/out_port" don't +# mean the same thing as normal gem5 ports. If a MessageBuffer +# is a "to" buffer (i.e., out) then you use the "out_port", +# otherwise, the in_port. self.requestToDir = MessageBuffer(ordered = True) -self.requestToDir.master = ruby_system.network.slave +self.requestToDir.out_port = ruby_system.network.in_port self.responseToDirOrSibling = MessageBuffer(ordered = True) -self.responseToDirOrSibling.master = ruby_system.network.slave +self.responseToDirOrSibling.out_port = ruby_system.network.in_port self.forwardFromDir = MessageBuffer(ordered = True) -self.forwardFromDir.slave = ruby_system.network.master +self.forwardFromDir.in_port = ruby_system.network.out_port self.responseFromDirOrSibling = MessageBuffer(ordered = True) -self.responseFromDirOrSibling.slave = ruby_system.network.master +self.responseFromDirOrSibling.in_port = ruby_system.network.out_port class DirController(Directory_Controller): @@ -192,14 +193,14 @@ def connectQueues(self, ruby_system): self.requestFromCache = MessageBuffer(ordered = True) -self.requestFromCache.slave = ruby_system.network.master +self.requestFromCache.in_port = ruby_system.network.out_port self.responseFromCache = MessageBuffer(ordered = True) -self.responseFromCache.slave = ruby_system.network.master +self.responseFromCache.in_port = ruby_system.network.out_port self.responseToCache = MessageBuffer(ordered = True) -self.responseToCache.master = ruby_system.network.slave +self.responseToCache.out_port = ruby_system.network.in_port self.forwardToCache = MessageBuffer(ordered = True) -self.forwardToCache.master = ruby_system.network.slave +self.forwardToCache.out_port = ruby_system.network.in_port # These are other special message buffers. They are used to send # requests to memory and responses from memory back to the controller. diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py b/configs/learning_gem5/part3/ruby_caches_MI_example.py index 0406829..b67e6b1 100644 --- a/configs/learning_gem5/part3/ruby_caches_MI_example.py +++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py @@ -96,7 +96,7 @@ # Set up a proxy port for the system_port. Used for load binaries and # other functional-only things. self.sys_port_proxy = RubyPortProxy() -system.system_port = self.sys_port_proxy.slave +system.system_port = self.sys_port_proxy.in_ports # Connect the cpu's cache, interrupt, and TLB ports to Ruby for i,cpu in enumerate(cpus): @@ -149,13 +149,13 @@ """ self.mandatoryQueue = MessageBuffer() self.requestFromCache = MessageBuffer(ordered = True) -self.requestFromCache.master = ruby_system.network.slave +self.requestFromCache.out_port = ruby_system.network.in_port self.responseFromCache = MessageBuffer(ordered = True) -self.responseFromCache.master =
[gem5-dev] Change in gem5/gem5[develop]: ext: Add extra defines to libelf to support Apple silicon.
Richard Cooper has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/52723 ) Change subject: ext: Add extra defines to libelf to support Apple silicon. .. ext: Add extra defines to libelf to support Apple silicon. The current version of libelf does not include a configuration compatible with Apple silicon. This patch adds the required defines. Change-Id: I9b7b9b1f711973159f31666d3fe480c2dc01a6b7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52723 Reviewed-by: Jason Lowe-Power Reviewed-by: Austin Harris Maintainer: Bobby R. Bruce Tested-by: kokoro --- M ext/libelf/_libelf_config.h 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve Austin Harris: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/ext/libelf/_libelf_config.h b/ext/libelf/_libelf_config.h index 1b8f35b..b968441 100644 --- a/ext/libelf/_libelf_config.h +++ b/ext/libelf/_libelf_config.h @@ -36,9 +36,15 @@ #defineLIBELF_ARCH EM_386 #defineLIBELF_BYTEORDERELFDATA2LSB #defineLIBELF_CLASSELFCLASS32 +#elif defined(__aarch64__) +#defineLIBELF_ARCH EM_AARCH64 +#defineLIBELF_BYTEORDERELFDATA2LSB +#defineLIBELF_CLASSELFCLASS64 +#else +#error Unknown Apple or DragonFly architecture. #endif -#endif /* __DragonFly__ */ +#endif /* __APPLE__ || __DragonFly__ */ #ifdef __FreeBSD__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52723 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I9b7b9b1f711973159f31666d3fe480c2dc01a6b7 Gerrit-Change-Number: 52723 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Cooper Gerrit-Reviewer: Austin Harris Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
