date:20221105

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Updating the SD bit of mstatus upon the register read

2022-11-05 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65273?usp=email )


Change subject: arch-riscv: Updating the SD bit of mstatus upon the  
register read

..

arch-riscv: Updating the SD bit of mstatus upon the register read

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26, the SD bit is
a read-only bit indicating whether any of FS, VS, and XS fields being
in the respective dirty state.

Per section 3.1.6, page 20, the SD bit is the most significant bit of
the mstatus register for both RV32 and RV64.

Per section 3.1.6.6, page 29, the explicit formula for updating the SD is,
SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))

Previously in gem5, this bit is not updated anywhere in the gem5
implementation. This cause an issue of incorrectly saving the context
before entering the system call and consequently, incorecttly restoring
the context after a system call as described here [1].

Ideally, we want to update the SD after every relevant instruction;
however, lazily updating the Status register upon its read produces
the same effect.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/65272/

Change-Id: I1db0cc619d43bc5bacb1d03f6f214345d9d90e28
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65273
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/riscv/isa.cc
1 file changed, 58 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e215e24..c76bb2b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -348,6 +348,29 @@
 else
 return mbits(val, 63, 1);
 }
+  case MISCREG_STATUS:
+{
+// Updating the SD bit.
+// . Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26,
+// the SD bit is a read-only bit indicating whether any of
+// FS, VS, and XS fields being in the respective dirty state.
+// . Per section 3.1.6, page 20, the SD bit is the most
+// significant bit of the MSTATUS CSR for both RV32 and RV64.
+// . Per section 3.1.6.6, page 29, the explicit formula for
+// updating the SD is,
+//   SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))
+// . Ideally, we want to update the SD after every relevant
+// instruction, however, lazily updating the Status register
+// upon its read produces the same effect as well.
+STATUS status = readMiscRegNoEffect(idx);
+uint64_t sd_bit = \
+(status.xs == 3) || (status.fs == 3) || (status.vs == 3);
+// We assume RV64 here, updating the SD bit at index 63.
+status.sd = sd_bit;
+setMiscRegNoEffect(idx, status);
+
+return readMiscRegNoEffect(idx);
+}
   default:
 // Try reading HPM counters
 // As a placeholder, all HPM counters are just cycle counters

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1db0cc619d43bc5bacb1d03f6f214345d9d90e28
Gerrit-Change-Number: 65273
Gerrit-PatchSet: 6
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #410

2022-11-05 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[Bobby R. Bruce] stdlib: Update AbstractCore `set_simpoint` func

[Bobby R. Bruce] stdlib: Update AbstractCore's 'set_inst_stop_any_thread'

[Bobby R. Bruce] stdlib: Fix typos and remove unneeded import in Simulator

[Bobby R. Bruce] stdlib: Fixing erroneous typing in Simulator __init__

[hoanguyen] stdlib: Change the default kernel boot param from "ro" to "rw"

[hoanguyen] arch-riscv: Add VS field to the STATUS CSR

[hoanguyen] arch-riscv: Update FS field of mstatus register where approriate.

[Giacomo Travaglini] dev-arm: Setup TC/ISA at construction time of 
Gicv3CPUInterface

[Giacomo Travaglini] arch-arm: Setup ISA::gicv3CpuInterface on demand only


--
[...truncated 464.60 KB...]
 [ CXX] ALL/python/_m5/param_ArmTLB.cc -> .o
 [ENUM STR] m5.objects.ArmTLB, ArmLookupLevel -> ALL/enums/ArmLookupLevel.cc
 [ CXX] ALL/enums/ArmLookupLevel.cc -> .o
 [ CXX] ALL/arch/arm/ArmPMU.py.cc -> .o
 [SO Param] m5.objects.ArmPMU, ArmPMU -> ALL/python/_m5/param_ArmPMU.cc
 [ CXX] ALL/arch/arm/ArmCPU.py.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmPMU.cc -> .o
 [ CXX] ALL/debug/Arm.cc -> .o
 [ CXX] ALL/debug/ArmTme.cc -> .o
 [ CXX] ALL/debug/Semihosting.cc -> .o
 [ CXX] ALL/debug/PMUVerbose.cc -> .o
 [ CXX] ALL/arch/arm/generated/decoder.cc -> .o
 [ CXX] ALL/arch/arm/generated/inst-constrs-1.cc -> .o
 [ CXX] ALL/arch/arm/generated/inst-constrs-2.cc -> .o
 [ CXX] ALL/arch/arm/generated/inst-constrs-3.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_1.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_2.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_3.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_4.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_5.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_6.cc -> .o
 [ CXX] ALL/arch/arm/tracers/TarmacTrace.py.cc -> .o
 [SO Param] m5.objects.TarmacTrace, TarmacParser -> 
ALL/python/_m5/param_TarmacParser.cc
 [SO Param] m5.objects.TarmacTrace, TarmacParser -> ALL/params/TarmacParser.hh
 [SO Param] m5.objects.TarmacTrace, TarmacTracer -> 
ALL/python/_m5/param_TarmacTracer.cc
 [ENUM STR] m5.objects.TarmacTrace, TarmacDump -> ALL/enums/TarmacDump.cc
 [ CXX] ALL/python/_m5/param_TarmacParser.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_base.cc -> .o
 [ENUMDECL] m5.objects.TarmacTrace, TarmacDump -> ALL/enums/TarmacDump.hh
 [SO Param] m5.objects.TarmacTrace, TarmacTracer -> ALL/params/TarmacTracer.hh
 [ CXX] ALL/arch/arm/tracers/tarmac_parser.cc -> .o
 [ CXX] ALL/enums/TarmacDump.cc -> .o
 [ CXX] ALL/python/_m5/param_TarmacTracer.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_tracer.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_record.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_record_v8.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_arm_target.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_arm_core.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_arm_vfpv3.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_aarch64_target.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_aarch64_core.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_aarch64_fpu.cc -> .o
 [ CXX] ALL/arch/generic/htm.cc -> .o
 [ CXX] ALL/arch/generic/mmu.cc -> .o
 [ CXX] ALL/arch/generic/BaseInterrupts.py.cc -> .o
 [SO Param] m5.objects.BaseInterrupts, BaseInterrupts -> 
ALL/python/_m5/param_BaseInterrupts.cc
 [ CXX] ALL/arch/generic/BaseISA.py.cc -> .o
 [SO Param] m5.objects.BaseISA, BaseISA -> ALL/python/_m5/param_BaseISA.cc
 [ CXX] ALL/python/_m5/param_BaseInterrupts.cc -> .o
 [ CXX] ALL/arch/generic/BaseMMU.py.cc -> .o
 [ CXX] ALL/python/_m5/param_BaseISA.cc -> .o
 [SO Param] m5.objects.BaseMMU, BaseMMU -> ALL/python/_m5/param_BaseMMU.cc
 [ CXX] ALL/python/_m5/param_BaseMMU.cc -> .o
 [ CXX] ALL/arch/generic/BaseTLB.py.cc -> .o
 [SO Param] m5.objects.BaseTLB, BaseTLB -> ALL/python/_m5/param_BaseTLB.cc
 [ENUM STR] m5.objects.BaseTLB, TypeTLB -> ALL/enums/TypeTLB.cc
 [ CXX] ALL/arch/generic/InstDecoder.py.cc -> .o
 [ CXX] ALL/python/_m5/param_BaseTLB.cc -> .o
 [ CXX] ALL/enums/TypeTLB.cc -> .o
 [SO Param] m5.objects.InstDecoder, InstDecoder -> 
ALL/python/_m5/param_InstDecoder.cc
 [ CXX] ALL/python/_m5/param_InstDecoder.cc -> .o
 [ CXX] ALL/debug/PageTableWalker.cc -> .o
 [ CXX] ALL/debug/TLB.cc -> .o
 [ CXX] ALL/arch/generic/decoder.cc -> .o
 [ CXX] ALL/arch/x86/cpuid.cc -> .o
 [SO Param] m5.objects.X86Decoder, X86Decoder -> ALL/params/X86Decoder.hh
 [ CXX] ALL/arch/x86/decoder.cc -> .o
 [ CXX] ALL/arch/x86/decoder_tables.cc -> .o
 [ CXX] ALL/arch/x86/emulenv.cc -> .o
 [ISA DESC] ALL/arch/x86/isa/main.isa -> generated/decoder-g.cc.inc, 
generated/decoder-ns.cc.inc, generated/decode-method.cc.inc, 
generated/decoder.hh, generated/decoder-g.hh.inc,

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: Updating the SD bit of mstatus upon the register read

[gem5-dev] Build failed in Jenkins: nightly #410

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