[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, tests: Refactor SimpleProcessor and SimpleCore

2022-12-08 Thread Roger Chang (Gerrit) via gem5-dev 
Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66592?usp=email )



Change subject: stdlib, tests: Refactor SimpleProcessor and SimpleCore
..

stdlib, tests: Refactor SimpleProcessor and SimpleCore

1. Add riscv_bits parameters to cpu_simobject_factory
2. Use Riscv32CPU if user set riscv_bits = 32

Change-Id: I411ba912a16fc870d02fe1850f387b1a5e6ecbea
---
M src/python/gem5/components/processors/simple_core.py
M src/python/gem5/components/processors/simple_processor.py
2 files changed, 27 insertions(+), 5 deletions(-)



diff --git a/src/python/gem5/components/processors/simple_core.py  
b/src/python/gem5/components/processors/simple_core.py

index 15e15dc..6391eda 100644
--- a/src/python/gem5/components/processors/simple_core.py
+++ b/src/python/gem5/components/processors/simple_core.py
@@ -42,7 +42,8 @@
 """

 def __init__(
-self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None
+self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None,
+riscv_bits: int = 64,
 ):

 # If the ISA is not specified, we infer it via the  
`get_runtime_isa`

@@ -55,7 +56,8 @@

 super().__init__(
 core=SimpleCore.cpu_simobject_factory(
-isa=isa, cpu_type=cpu_type, core_id=core_id
+isa=isa, cpu_type=cpu_type, core_id=core_id,
+riscv_bits=riscv_bits,
 ),
 isa=isa,
 )
@@ -66,7 +68,9 @@
 return self._cpu_type

 @classmethod
-def cpu_simobject_factory(cls, cpu_type: CPUTypes, isa: ISA, core_id:  
int):

+def cpu_simobject_factory(
+cls, cpu_type: CPUTypes, isa: ISA, core_id: int, riscv_bits: int =  
64

+):
 """
 A factory used to return the SimObject core object given the cpu  
type,

 and ISA target. An exception will be thrown if there is an
@@ -130,6 +134,10 @@
 f"{_isa_string_map[isa]}V8"
 f"{_cpu_types_string_map[cpu_type]}"
 )
+elif riscv_bits == 32:
+cpu_class_str = (
+f"{_isa_string_map[isa]}32"  
f"{_cpu_types_string_map[cpu_type]}"

+)
 else:
 cpu_class_str = (
 f"{_isa_string_map[isa]}"  
f"{_cpu_types_string_map[cpu_type]}"
diff --git a/src/python/gem5/components/processors/simple_processor.py  
b/src/python/gem5/components/processors/simple_processor.py

index 510e37d..0cafed1 100644
--- a/src/python/gem5/components/processors/simple_processor.py
+++ b/src/python/gem5/components/processors/simple_processor.py
@@ -42,7 +42,8 @@
 """

 def __init__(
-self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] = None
+self, cpu_type: CPUTypes, num_cores: int, isa: Optional[ISA] =  
None,

+riscv_bits: int = 64,
 ) -> None:
 """
 :param cpu_type: The CPU type for each type in the processor.
@@ -64,7 +65,8 @@
 )
 super().__init__(
 cores=[
-SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa)
+SimpleCore(cpu_type=cpu_type, core_id=i, isa=isa,
+   riscv_bits=riscv_bits)
 for i in range(num_cores)
 ]
 )

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I411ba912a16fc870d02fe1850f387b1a5e6ecbea
Gerrit-Change-Number: 66592
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] Jenkins build is back to normal : nightly #450

2022-12-08 Thread jenkins-no-reply--- via gem5-dev 
See 
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[gem5-dev] [M] Change in gem5/gem5[release-staging-v22-1]: misc: Update .mailmap

2022-12-08 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66531?usp=email )


Change subject: misc: Update .mailmap
..

misc: Update .mailmap

This commit updates the mailmap since the initial commit in mid-July
2020: https://gem5-review.googlesource.com/c/public/gem5/+/29672.

`sort -u` has been run on this file so some previous entries have been
moved.

Change-Id: I46df1e9675f6f7057b680ca2abbcebdffd50462a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66531
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
---
M .mailmap
1 file changed, 179 insertions(+), 61 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/.mailmap b/.mailmap
index 5125666..49c438d 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1,37 +1,43 @@
-ARM gem5 Developers 
 Abdul Mutaal Ahmad 
+adarshpatil 
+Adrià Armejach  Adrià Armejach  


 Adrian Herrera 
 Adrien Pesle 
-Adrià Armejach  Adrià Armejach  


 Akash Bagdia  Akash Bagdia 
 Alec Roelke  Alec Roelke 
+Alexander Klimov 
 Alexandru Dutu  Alexandru 
+Alex Richardson 
 Ali Jafri 
-Ali Saidi  Ali Saidi 
 Ali Saidi  Ali Saidi 
+Ali Saidi  Ali Saidi 
 Ali Saidi  Ali Saidi 
+Alistair Delva 
 Amin Farmahini 
 Anders Handler 
-Andrea Mondelli  Andrea Mondelli  

+Andrea Mondelli  Andrea Mondelli  

+Andrea Mondelli  Andrea Mondelli  


 Andrea Pellegrini 
-Andreas Hansson  Andreas Hansson  


 Andreas Hansson  Andreas Hansson 
 Andreas Hansson  Andreas Hansson  

+Andreas Hansson  Andreas Hansson  

 Andreas Hansson  Andreas Hansson  

-Andreas Sandberg  Andreas Sandberg  

 Andreas Sandberg  Andreas Sandberg  

+Andreas Sandberg  Andreas Sandberg  

 Andreas Sandberg  Andreas Sandberg  

 Andrew Bardsley  Andrew Bardsley  


 Andrew Lukefahr 
 Andrew Schultz 
 Andriani Mappoura 
-Ani Udipi 
+Angie Lee 
 Anis Peysieux 
+Ani Udipi 
 Anouk Van Laer 
-Arthur Perais 
+ARM gem5 Developers 
+Arthur Perais  Arthur Perais  


+Arun Rodrigues 
 Ashkan Tousi 
-Austin Harris 
-Richard D. Strong 
+Austin Harris  Austin Harris  


 Avishai Tvila 
 Ayaz Akram 
 Bagus Hanindhito 
@@ -41,80 +47,108 @@
 Bjoern A. Zeeb 
 Blake Hechtman  Blake Hechtman 
 Blake Hechtman  Blake Hechtman  
ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) 

-Bobby R. Bruce 
+Bobby R. Bruce  Bobby Bruce  

 Boris Shingarov  Boris Shingarov  


 Brad Beckmann  Brad Beckmann 
 Brad Beckmann  Brad Beckmann  
ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)  


 Brad Danofsky 
 Bradley Wang  Bradley 
+Brandon Potter  BKP 
 Brandon Potter  bpotter 
 Brandon Potter  Brandon Potter  


-Brandon Potter  BKP 
 Brian Grayson 
 Cagdas Dirik  cdirik 
+Carlos Falquez 
 Chander Sudanthi  Chander Sudanthi  

 Chander Sudanthi  Chander Sudanthi  


+Charles Jamieson 
+CHEN Meng 
 Chen Zou 
+Chia-You Chen 
+Chow, Marcus 
 Chris Adeniyi-Jones 
-Chris Emmons  Chris Emmons 
 Chris Emmons  Chris Emmons 
+Chris Emmons  Chris Emmons 
+Chris January 
 Christian Menard  Christian Menard  


-Christoph Pfister 
 Christopher Torng 
+Christoph Pfister 
 Chuan Zhu 
 Chun-Chen Hsu  Chun-Chen TK Hsu  


 Ciro Santilli 
 Clint Smullen 
+Cui Jin  Cui Jin 
 Curtis Dunham 
+Daecheol You 
 Dam Sunwoo 
 Dan Gibson 
 Daniel Carvalho  Daniel 
 Daniel Carvalho  Daniel R. Carvalho  


+Daniel Gerzhoy 
 Daniel Johnson 
 Daniel Sanchez 
+Davide Basilio Bartolini 
 David Guillen-Fandos  David Guillen  

 David Guillen-Fandos  David Guillen Fandos  


 David Hashe  David Hashe 
 David Oehmke 
+David Schall 
+Derek Christ 
 Derek Hower 
-Deyaun Guo  Deyuan Guo  

 Deyaun Guo  Deyuan Guo  
ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)  

+Deyaun Guo  Deyuan Guo  

 Dibakar Gope  Dibakar Gope  
ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) 

+Dimitrios Chasapis 
 Djordje Kovacevic  Djordje Kovacevic  


-Dongxue Zhang 
 Doğukan Korkmaztürk 
+Dongxue Zhang 
 Dylan Johnson 
 Earl Ou 
+eavivi 
+Éder F. Zulian 
 Edmund Grimley Evans 
+Eduardo José Gómez Hernández 
+Eliot Moss 
 Emilio Castillo  Emilio Castillo 
 Emilio Castillo  Emilio Castillo  
ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) 

+Emily Brickey 
 Erfan Azarkhish 
+Erhu 
 Eric Van Hensbergen  Eric Van Hensbergen  


+Eric Ye 
 Erik Hallnor 
 Erik Tomusk 
 Faissal Sleiman  Faissal Sleiman  


 Fernando Endo 
+Franklin He 
 Gabe Black  Gabe Black 
 Gabe Black  Gabe Black 
+Gabe Loh  gloh 
 Gabor Dozsa 
+Gabriel Busnot 
+gauravjain14 
 Gedare Bloom  Gedare Bloom 
 Gene Wu  Gene WU 
 Gene WU  Gene Wu 
-Geoffrey Blake  Geoffrey Blake  


 Geoffrey Blake  Geoffrey Blake 
+Geoffrey Blake  Geoffrey Blake  


 Georg Kotheimer 
 Giacomo Gabrielli  Giacomo Gabrielli  


 Giacomo Travaglini 
 Glenn Bergmans 
+GWDx 
 Hamid Reza Khaleghzadeh  Hamid Reza Khaleghzadeh  
ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)

[gem5-dev] [XL] Change in gem5/gem5[develop]: arch-riscv: Add RV64 vector extension support

2022-12-08 Thread Gerrit 
轩胡 has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66552?usp=email )



Change subject: arch-riscv: Add RV64 vector extension support
..

arch-riscv: Add RV64 vector extension support

Change-Id: I7cec10412c00a35c247299cd92d83cdee9066410
Co-authored-by: Xuan Hu 
Co-authored-by: Yang Liu 
Co-authored-by: Fan Yang <1209202...@qq.com>
Co-authored-by: Jerin Joy 
---
M ext/softfloat/SConscript
A ext/softfloat/fall_maxmin.c
A ext/softfloat/fall_reciprocal.c
M ext/softfloat/platform.h
M ext/softfloat/softfloat.h
M ext/softfloat/softfloat.mk.in
M src/arch/generic/decoder.hh
M src/arch/isa_parser/operand_types.py
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.hh
M src/arch/riscv/insts/SConscript
M src/arch/riscv/insts/amo.cc
D src/arch/riscv/insts/bitfields.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/insts/unknown.hh
A src/arch/riscv/insts/vector.cc
A src/arch/riscv/insts/vector.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/formats.isa
A src/arch/riscv/isa/formats/vector_arith.isa
A src/arch/riscv/isa/formats/vector_conf.isa
A src/arch/riscv/isa/formats/vector_mem.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/main.isa
M src/arch/riscv/isa/operands.isa
A src/arch/riscv/isa/templates/templates.isa
A src/arch/riscv/isa/templates/vector_arith.isa
A src/arch/riscv/isa/templates/vector_mem.isa
M src/arch/riscv/regs/float.hh
M src/arch/riscv/regs/misc.hh
A src/arch/riscv/regs/vector.hh
M src/arch/riscv/types.hh
M src/arch/riscv/utility.hh
M src/cpu/FuncUnit.py
M src/cpu/minor/BaseMinorCPU.py
M src/cpu/minor/fetch2.cc
M src/cpu/o3/fetch.cc
M src/cpu/op_class.hh
44 files changed, 9,925 insertions(+), 124 deletions(-)




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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I7cec10412c00a35c247299cd92d83cdee9066410
Gerrit-Change-Number: 66552
Gerrit-PatchSet: 1
Gerrit-Owner: 轩胡 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Implement and use the recvMemBackdoorReq func.

2022-12-08 Thread Yu-hsin Wang (Gerrit) via gem5-dev 
Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/66551?usp=email )



Change subject: mem: Implement and use the recvMemBackdoorReq func.
..

mem: Implement and use the recvMemBackdoorReq func.

In the previous change, we miss some model supporting atomic backdoor.
We should also implement the recvMemBackdoorReq to them.

Change-Id: I4706d215aa4a5d18fe4306b2387f9c8750cb4b4a
---
M src/mem/hbm_ctrl.cc
M src/mem/hbm_ctrl.hh
M src/mem/thread_bridge.cc
M src/mem/thread_bridge.hh
4 files changed, 39 insertions(+), 0 deletions(-)



diff --git a/src/mem/hbm_ctrl.cc b/src/mem/hbm_ctrl.cc
index 99618c4..747e714 100644
--- a/src/mem/hbm_ctrl.cc
+++ b/src/mem/hbm_ctrl.cc
@@ -150,6 +150,21 @@
 return latency;
 }

+void
+HBMCtrl::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+auto  = req.range();
+if (pc0Int && pc0Int->getAddrRange().isSubset(range)) {
+pc0Int->getBackdoor(backdoor);
+} else if (pc1Int && pc1Int->getAddrRange().isSubset(range)) {
+pc1Int->getBackdoor(backdoor);
+}
+else {
+panic("Can't handle address range for range %s\n",  
range.to_string());

+}
+}
+
 bool
 HBMCtrl::writeQueueFullPC0(unsigned int neededEntries) const
 {
diff --git a/src/mem/hbm_ctrl.hh b/src/mem/hbm_ctrl.hh
index c9045f0..a6ecf6c 100644
--- a/src/mem/hbm_ctrl.hh
+++ b/src/mem/hbm_ctrl.hh
@@ -259,6 +259,8 @@
 Tick recvAtomic(PacketPtr pkt) override;
 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr )  
override;

 void recvFunctional(PacketPtr pkt) override;
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr &_backdoor) override;
 bool recvTimingReq(PacketPtr pkt) override;

 };
diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
index 3f76ef4..efaf19a 100644
--- a/src/mem/thread_bridge.cc
+++ b/src/mem/thread_bridge.cc
@@ -84,6 +84,14 @@
 device_.out_port_.sendFunctional(pkt);
 }

+void
+ThreadBridge::IncomingPort::recvMemBackdoorReq(const MemBackdoorReq ,
+   MemBackdoorPtr )
+{
+EventQueue::ScopedMigration migrate(device_.eventQueue());
+device_.out_port_.sendMemBackdoorReq(req, backdoor);
+}
+
 ThreadBridge::OutgoingPort::OutgoingPort(const std::string ,
  ThreadBridge )
 : RequestPort(name, ), device_(device)
diff --git a/src/mem/thread_bridge.hh b/src/mem/thread_bridge.hh
index 28c9591..92cb078 100644
--- a/src/mem/thread_bridge.hh
+++ b/src/mem/thread_bridge.hh
@@ -61,6 +61,8 @@

 // FunctionalResponseProtocol
 void recvFunctional(PacketPtr pkt) override;
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr ) override;

   private:
 ThreadBridge _;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4706d215aa4a5d18fe4306b2387f9c8750cb4b4a
Gerrit-Change-Number: 66551
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Jenkins build is back to normal : compiler-checks #447

2022-12-08 Thread jenkins-no-reply--- via gem5-dev 
See 

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