[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Support str-convertible args in gem5_verify_config
Gabriel B. has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66893?usp=email )
Change subject: ext-testlib: Support str-convertible args in
gem5_verify_config
..
ext-testlib: Support str-convertible args in gem5_verify_config
gem5_verify_config dit not support string-convertible args due to log_call()
not trying to call str() on them. This patch maps str() on the command
paramters.
It is now possible to pass native integers or even string-like types like
pathlib.Path as arguments without manually converting them to string.
Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66893
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M ext/testlib/helper.py
1 file changed, 28 insertions(+), 1 deletion(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index ed6e325..ea102f2 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -149,7 +149,14 @@
if isinstance(command, str):
cmdstr = command
else:
-cmdstr = ' '.join(command)
+try:
+command = list(map(str, command))
+cmdstr = " ".join(command)
+except TypeError as e:
+logger.trace(
+"Argument must be an iterable of
string-convertible types"
+)
+raise e
logger_callback = logger.trace
logger.trace('Logging call to command: %s' % cmdstr)
--
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Gerrit-Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
Gerrit-Change-Number: 66893
Gerrit-PatchSet: 2
Gerrit-Owner: Gabriel B.
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabriel B.
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Improve error reporting when test definition fails
Gabriel B. has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66892?usp=email )
Change subject: ext-testlib: Improve error reporting when test definition
fails
..
ext-testlib: Improve error reporting when test definition fails
The error reason is now reported as an element in the XML testing result
summary.
Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66892
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M ext/testlib/result.py
1 file changed, 37 insertions(+), 10 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 5c60342..786febd 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -191,17 +191,23 @@
def begin(self, file_):
file_.write('<')
file_.write(self.name)
-for attr in self.attributes:
-file_.write(' ')
-attr.write(file_)
+if hasattr(self, 'attributes'):
+for attr in self.attributes:
+file_.write(' ')
+attr.write(file_)
file_.write('>')
self.body(file_)
def body(self, file_):
-for elem in self.elements:
-file_.write('\n')
-elem.write(file_)
+if hasattr(self, 'elements'):
+for elem in self.elements:
+file_.write('\n')
+elem.write(file_)
+if hasattr(self, 'content'):
+file_.write('\n')
+file_.write(
+xml.sax.saxutils.escape(self.content))
file_.write('\n')
def end(self, file_):
@@ -286,17 +292,22 @@
]
if str(test_result.result) == 'Failed':
-self.elements.append(JUnitFailure('Test failed', 'ERROR'))
+self.elements.append(JUnitFailure(
+'Test failed',
+str(test_result.result.reason))
+)
class JUnitFailure(XMLElement):
name = 'failure'
-def __init__(self, message, fail_type):
+def __init__(self, message, cause):
self.attributes = [
XMLAttribute('message', message),
-XMLAttribute('type', fail_type),
]
-self.elements = []
+cause_element = XMLElement()
+cause_element.name = 'cause'
+cause_element.content = cause
+self.elements = [cause_element]
class LargeFileElement(XMLElement):
--
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Gerrit-Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
Gerrit-Change-Number: 66892
Gerrit-PatchSet: 2
Gerrit-Owner: Gabriel B.
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabriel B.
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66771?usp=email )
Change subject: stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
..
stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy
Change-Id: I60ae47f4336cb1b54bcca3fce3bdd13858daa92a
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66771
Reviewed-by: Matt Sinclair
Reviewed-by: Jason Lowe-Power
Maintainer: Matt Sinclair
Tested-by: kokoro
---
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
4 files changed, 47 insertions(+), 19 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Matt Sinclair: Looks good to me, but someone else must approve; Looks
good to me, approved
kokoro: Regressions pass
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
index ab76d4c..f731869 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py
@@ -25,16 +25,26 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from ..utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController
-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, DMA_Controller
-class DMAController(AbstractDMAController):
-def __init__(self, network, cache_line_size):
-super().__init__(network, cache_line_size)
+class DMAController(DMA_Controller):
+_version = 0
-@overrides(AbstractDMAController)
+@classmethod
+def _get_version(cls):
+cls._version += 1
+return cls._version - 1
+
+def __init__(self, dma_sequencer, ruby_system):
+super().__init__(
+version=self._get_version(),
+dma_sequencer=dma_sequencer,
+ruby_system=ruby_system,
+)
+self.connectQueues(self.ruby_system.network)
+
def connectQueues(self, network):
self.mandatoryQueue = MessageBuffer()
self.responseFromDir = MessageBuffer(ordered=True)
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
index 2ce13d3..9f47e41 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
@@ -68,14 +68,14 @@
self.Icache = RubyCache(
size=l1i_size,
assoc=l1i_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
is_icache=True,
replacement_policy=LRURP(),
)
self.Dcache = RubyCache(
size=l1d_size,
assoc=l1d_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
is_icache=False,
replacement_policy=LRURP(),
)
@@ -88,12 +88,11 @@
self.response_latency = 2
self.version = self.versionCount()
-self._cache_line_size = cache_line_size
self.connectQueues(network)
-def getBlockSizeBits(self):
-bits = int(math.log(self._cache_line_size, 2))
-if 2**bits != self._cache_line_size.value:
+def getBlockSizeBits(self, cache_line_size):
+bits = int(math.log(cache_line_size, 2))
+if 2**bits != cache_line_size:
raise Exception("Cache line size is not a power of 2!")
return bits
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
index e29f566..d8c9659 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
@@ -67,7 +67,7 @@
self.cache = RubyCache(
size=l2_size,
assoc=l2_assoc,
-start_index_bit=self.getBlockSizeBits(),
+start_index_bit=self.getBlockSizeBits(cache_line_size.value),
is_icache=False,
)
# l2_select_num_bits is ruby backend
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Fix signed BFE instructions
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66751?usp=email )
Change subject: arch-vega: Fix signed BFE instructions
..
arch-vega: Fix signed BFE instructions
The bitfield extract instructions come in unsigned and signed variants.
The documentation on this is not correct, however the GCN3 documentation
gives some clues. The instruction should extract an N-bit integer where
N is defined in a source operand starting at some bit also defined by a
source operand. For signed variants of this instruction, the N-bit
integer should be sign extended but is currently not.
This changeset does sign extension using the runtime value of N by ORing
the upper bits with ones if the most significant bit is one. This was
verified by writing these instructions in assembly and running on a real
GPU. Changes are made to v_bfe_i32, s_bfe_i32, and s_bfe_i64.
Change-Id: Ia192f5940200c6de48867b02f709a7f1b2daa974
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66751
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 55 insertions(+), 0 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index f5b08b7..c9e57bc 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -1302,6 +1302,21 @@
sdst = (src0.rawData() >> bits(src1.rawData(), 4, 0))
& ((1 << bits(src1.rawData(), 22, 16)) - 1);
+
+// Above extracted a signed int of size src1[22:16] bits which
needs
+// to be signed-extended. Check if the MSB of our src1[22:16]-bit
+// integer is 1, and sign extend it is.
+//
+// Note: The description in the Vega ISA manual does not mention to
+// sign-extend the result. An update description can be found in
the
+// more recent RDNA3 manual here:
+// https://developer.amd.com/wp-content/resources/
+// RDNA3_Shader_ISA_December2022.pdf
+if (sdst.rawData() >> (bits(src1.rawData(), 22, 16) - 1)) {
+sdst = sdst.rawData()
+ | (0x << bits(src1.rawData(), 22, 16));
+}
+
scc = sdst.rawData() ? 1 : 0;
sdst.write();
@@ -1373,6 +1388,14 @@
sdst = (src0.rawData() >> bits(src1.rawData(), 5, 0))
& ((1 << bits(src1.rawData(), 22, 16)) - 1);
+
+// Above extracted a signed int of size src1[22:16] bits which
needs
+// to be signed-extended. Check if the MSB of our src1[22:16]-bit
+// integer is 1, and sign extend it is.
+if (sdst.rawData() >> (bits(src1.rawData(), 22, 16) - 1)) {
+sdst = sdst.rawData()
+ | 0x << bits(src1.rawData(), 22, 16);
+}
scc = sdst.rawData() ? 1 : 0;
sdst.write();
@@ -30544,6 +30567,13 @@
if (wf->execMask(lane)) {
vdst[lane] = (src0[lane] >> bits(src1[lane], 4, 0))
& ((1 << bits(src2[lane], 4, 0)) - 1);
+
+// Above extracted a signed int of size src2 bits which
needs
+// to be signed-extended. Check if the MSB of our src2-bit
+// integer is 1, and sign extend it is.
+if (vdst[lane] >> (bits(src2[lane], 4, 0) - 1)) {
+vdst[lane] |= 0x << bits(src2[lane], 4, 0);
+}
}
}
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ia192f5940200c6de48867b02f709a7f1b2daa974
Gerrit-Change-Number: 66751
Gerrit-PatchSet: 4
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Fix several issues with DPP
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66752?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-vega: Fix several issues with DPP
..
arch-vega: Fix several issues with DPP
DPP processing has several issues which are fixed in this changeset:
1) Incorrect comment is updated
2) newLane calculation for shift/rotate instructions is corrected
3) A copy of original data is made so that a copy of a copy is not made
4) Reset all booleans (OOB, zeroSrc, laneDisabled) after each lane
iteration
The shift, rotate, and broadcast variants were tested by implementing
them in assembly and running on silicon.
Change-Id: If86fbb26c87eaca4ef0587fd846978115858b168
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66752
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/inst_util.hh
1 file changed, 58 insertions(+), 23 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/inst_util.hh
b/src/arch/amdgpu/vega/insts/inst_util.hh
index 01925f9..7ec2e2d 100644
--- a/src/arch/amdgpu/vega/insts/inst_util.hh
+++ b/src/arch/amdgpu/vega/insts/inst_util.hh
@@ -303,9 +303,9 @@
* Currently the values are:
* 0x0 - 0xFF: full permute of four threads
* 0x100: reserved
- * 0x101 - 0x10F: row shift right by 1-15 threads
+ * 0x101 - 0x10F: row shift left by 1-15 threads
* 0x111 - 0x11F: row shift right by 1-15 threads
- * 0x121 - 0x12F: row shift right by 1-15 threads
+ * 0x121 - 0x12F: row rotate right by 1-15 threads
* 0x130: wavefront left shift by 1 thread
* 0x134: wavefront left rotate by 1 thread
* 0x138: wavefront right shift by 1 thread
@@ -322,7 +322,8 @@
// newLane will be the same as the input lane unless swizzling
happens
int newLane = currLane;
// for shift/rotate permutations; positive values are LEFT rotates
-int count = 1;
+// shift/rotate left means lane n -> lane n-1 (e.g., lane 1 ->
lane 0)
+int count = 0;
int localRowOffset = rowOffset;
int localRowNum = rowNum;
@@ -335,51 +336,47 @@
panic("ERROR: instruction using reserved DPP_CTRL value\n");
} else if ((dppCtrl >= SQ_DPP_ROW_SL1) &&
(dppCtrl <= SQ_DPP_ROW_SL15)) { // DPP_ROW_SL{1:15}
-count -= (dppCtrl - SQ_DPP_ROW_SL1 + 1);
+count = (dppCtrl - SQ_DPP_ROW_SL1 + 1);
if ((localRowOffset + count >= 0) &&
(localRowOffset + count < ROW_SIZE)) {
localRowOffset += count;
-newLane = (rowNum | localRowOffset);
+newLane = ((rowNum * ROW_SIZE) | localRowOffset);
} else {
outOfBounds = true;
}
} else if ((dppCtrl >= SQ_DPP_ROW_SR1) &&
(dppCtrl <= SQ_DPP_ROW_SR15)) { // DPP_ROW_SR{1:15}
-count -= (dppCtrl - SQ_DPP_ROW_SR1 + 1);
+count = -(dppCtrl - SQ_DPP_ROW_SR1 + 1);
if ((localRowOffset + count >= 0) &&
(localRowOffset + count < ROW_SIZE)) {
localRowOffset += count;
-newLane = (rowNum | localRowOffset);
+newLane = ((rowNum * ROW_SIZE) | localRowOffset);
} else {
outOfBounds = true;
}
} else if ((dppCtrl >= SQ_DPP_ROW_RR1) &&
(dppCtrl <= SQ_DPP_ROW_RR15)) { // DPP_ROW_RR{1:15}
-count -= (dppCtrl - SQ_DPP_ROW_RR1 + 1);
+count = -(dppCtrl - SQ_DPP_ROW_RR1 + 1);
localRowOffset = (localRowOffset + count + ROW_SIZE) %
ROW_SIZE;
-newLane = (rowNum | localRowOffset);
+newLane = ((rowNum * ROW_SIZE) | localRowOffset);
} else if (dppCtrl == SQ_DPP_WF_SL1) { // DPP_WF_SL1
-count = 1;
if ((currLane >= 0) && (currLane < NumVecElemPerVecReg)) {
-newLane += count;
+newLane += 1;
} else {
outOfBounds = true;
}
} else if (dppCtrl == SQ_DPP_WF_RL1) { // DPP_WF_RL1
-count = 1;
-newLane = (currLane + count + NumVecElemPerVecReg) %
+newLane = (currLane - 1 + NumVecElemPerVecReg) %
NumVecElemPerVecReg;
} else if (dppCtrl == SQ_DPP_WF_SR1) { // DPP_WF_SR1
-count = -1;
-int currVal = (currLane + count);
+int currVal = (currLane - 1);
if ((currVal >= 0) && (currVal < NumVecElemPerVecReg)) {
-newLane += count;
+newLane -= 1;
}
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-vega: Add missing operand size for ds_write2st64_b64
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67071?usp=email )
Change subject: arch-vega: Add missing operand size for ds_write2st64_b64
..
arch-vega: Add missing operand size for ds_write2st64_b64
This instruction takes three operands (address, and two datas) but there
were only operand sizes for two operands tripping assert in default
case.
Change-Id: I3f505b6432aee5f3f265acac46b83c0c7daff3e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67071
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.hh
1 file changed, 20 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 0671df8..1c42248 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -33553,7 +33553,9 @@
switch (opIdx) {
case 0: //vgpr_a
return 4;
- case 1: //vgpr_d1
+ case 1: //vgpr_d0
+return 8;
+ case 2: //vgpr_d1
return 8;
default:
fatal("op idx %i out of bounds\n", opIdx);
--
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Gerrit-Change-Number: 67071
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Implement ds_add_u32 atomic
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67072?usp=email )
Change subject: arch-vega: Implement ds_add_u32 atomic
..
arch-vega: Implement ds_add_u32 atomic
This instruction does an atomic add of unsigned 32-bit data with a VGPR
and value in LDS atomically, without return.
Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67072
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
2 files changed, 64 insertions(+), 3 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 1f37ff1..afdfde3 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -34071,6 +34071,10 @@
Inst_DS__DS_ADD_U32::Inst_DS__DS_ADD_U32(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u32")
{
+setFlag(MemoryRef);
+setFlag(GroupSegment);
+setFlag(AtomicAdd);
+setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U32
Inst_DS__DS_ADD_U32::~Inst_DS__DS_ADD_U32()
@@ -34079,14 +34083,53 @@
// --- description from .arch file ---
// 32b:
-// tmp = MEM[ADDR];
// MEM[ADDR] += DATA;
-// RETURN_DATA = tmp.
void
Inst_DS__DS_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (gpuDynInst->exec_mask.none()) {
+wf->decLGKMInstsIssued();
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(
+gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
+ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA0);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
+
+void
+Inst_DS__DS_ADD_U32::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+Addr offset0 = instData.OFFSET0;
+Addr offset1 = instData.OFFSET1;
+Addr offset = (offset1 << 8) | offset0;
+
+initAtomicAccess(gpuDynInst, offset);
+} // initiateAcc
+
+void
+Inst_DS__DS_ADD_U32::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+} // completeAcc
// --- Inst_DS__DS_SUB_U32 class methods ---
Inst_DS__DS_SUB_U32::Inst_DS__DS_SUB_U32(InFmt_DS *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh
b/src/arch/amdgpu/vega/insts/instructions.hh
index 1c42248..33be33e 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -31211,6 +31211,8 @@
}
} // getOperandSize
+void initiateAcc(GPUDynInstPtr gpuDynInst) override;
+void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U32
--
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Gerrit-Change-Id: I87579a94f6200a9a066f8f7390e57fb5fb6eff8e
Gerrit-Change-Number: 67072
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
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Gerrit-Reviewer: kokoro
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-vega: Add DPP support for V_AND_B32
Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66753?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-vega: Add DPP support for V_AND_B32
..
arch-vega: Add DPP support for V_AND_B32
A DPP variant of V_AND_B32 was found in rocPRIM. With this changeset the
unit tests for rocPRIM scan_inclusive are passing.
Change-Id: I5a65f2cf6b56ac13609b191e3b3dfeb55e630942
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66753
Tested-by: kokoro
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 46 insertions(+), 4 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index c9e57bc..1f37ff1 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -6844,15 +6844,41 @@
{
Wavefront *wf = gpuDynInst->wavefront();
ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
-ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
+VecOperandU32 src1(gpuDynInst, instData.VSRC1);
VecOperandU32 vdst(gpuDynInst, instData.VDST);
src0.readSrc();
src1.read();
-for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
-if (wf->execMask(lane)) {
-vdst[lane] = src0[lane] & src1[lane];
+if (isDPPInst()) {
+VecOperandU32 src0_dpp(gpuDynInst, extData.iFmt_VOP_DPP.SRC0);
+src0_dpp.read();
+
+DPRINTF(VEGA, "Handling V_AND_B32 SRC DPP. SRC0: register
v[%d], "
+"DPP_CTRL: 0x%#x, SRC0_ABS: %d, SRC0_NEG: %d, "
+"SRC1_ABS: %d, SRC1_NEG: %d, BC: %d, "
+"BANK_MASK: %d, ROW_MASK: %d\n",
extData.iFmt_VOP_DPP.SRC0,
+extData.iFmt_VOP_DPP.DPP_CTRL,
+extData.iFmt_VOP_DPP.SRC0_ABS,
+extData.iFmt_VOP_DPP.SRC0_NEG,
+extData.iFmt_VOP_DPP.SRC1_ABS,
+extData.iFmt_VOP_DPP.SRC1_NEG,
+extData.iFmt_VOP_DPP.BC,
+extData.iFmt_VOP_DPP.BANK_MASK,
+extData.iFmt_VOP_DPP.ROW_MASK);
+
+processDPP(gpuDynInst, extData.iFmt_VOP_DPP, src0_dpp, src1);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = src0_dpp[lane] & src1[lane];
+}
+}
+} else {
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = src0[lane] & src1[lane];
+}
}
}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5a65f2cf6b56ac13609b191e3b3dfeb55e630942
Gerrit-Change-Number: 66753
Gerrit-PatchSet: 5
Gerrit-Owner: Matthew Poremba
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Re-add -Werror for gem5 develop branch
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67052?usp=email )
Change subject: scons: Re-add -Werror for gem5 develop branch
..
scons: Re-add -Werror for gem5 develop branch
This is removed from the stable branch to avoid build errors but should
included on the develop branch to aid developers.
This reverts commit 7dd61c865975862b099e1af5e867083ac9307d9b.
Change-Id: I1fe249ce87aa8d70c1f092fc7db1554e6aee7355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67052
Tested-by: kokoro
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
---
M SConstruct
1 file changed, 26 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index e8107ea..bd26e45 100755
--- a/SConstruct
+++ b/SConstruct
@@ -420,6 +420,14 @@
conf.CheckLinkFlag('-Wl,--threads')
conf.CheckLinkFlag(
'-Wl,--thread-count=%d' %
GetOption('num_jobs'))
+
+# Treat warnings as errors but white list some warnings that we
+# want to allow (e.g., deprecation warnings).
+env.Append(CCFLAGS=['-Werror',
+ '-Wno-error=deprecated-declarations',
+ '-Wno-error=deprecated',
+])
+
else:
error('\n'.join((
"Don't know what compiler options to use for your compiler.",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1fe249ce87aa8d70c1f092fc7db1554e6aee7355
Gerrit-Change-Number: 67052
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Update version info for develop branch
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67053?usp=email )
Change subject: misc: Update version info for develop branch
..
misc: Update version info for develop branch
Change-Id: Icd409acda0e88852938b2af9f170e2a410e91f8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67053
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M ext/sst/README.md
M ext/testlib/configuration.py
M src/Doxyfile
M src/base/version.cc
M src/python/gem5/resources/downloader.py
M tests/compiler-tests.sh
M tests/jenkins/presubmit.sh
M tests/nightly.sh
M tests/weekly.sh
M util/dockerfiles/docker-compose.yaml
M util/dockerfiles/gcn-gpu/Dockerfile
11 files changed, 50 insertions(+), 37 deletions(-)
Approvals:
kokoro: Regressions pass
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
diff --git a/ext/sst/README.md b/ext/sst/README.md
index 49f5634..1f37cb4 100644
--- a/ext/sst/README.md
+++ b/ext/sst/README.md
@@ -62,7 +62,7 @@
Downloading the built bootloader containing a Linux Kernel and a workload,
```sh
-wget http://dist.gem5.org/dist/v22-1/misc/riscv/bbl-busybox-boot-exit
+wget http://dist.gem5.org/dist/develop/misc/riscv/bbl-busybox-boot-exit
```
Running the simulation
@@ -87,7 +87,7 @@
directory):
```sh
-wget http://dist.gem5.org/dist/v22-1/arm/aarch-sst-20211207.tar.bz2
+wget http://dist.gem5.org/dist/develop/arm/aarch-sst-20211207.tar.bz2
tar -xf aarch-sst-20211207.tar.bz2
# copying bootloaders
diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index 97c6376..fd47e3b 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -213,7 +213,7 @@
os.pardir,
os.pardir))
defaults.result_path = os.path.join(os.getcwd(), 'testing-results')
-defaults.resource_url = 'http://dist.gem5.org/dist/v22-1'
+defaults.resource_url = 'http://dist.gem5.org/dist/develop'
defaults.resource_path =
os.path.abspath(os.path.join(defaults.base_dir,
'tests',
'gem5',
diff --git a/src/Doxyfile b/src/Doxyfile
index 4d14b7c..24d70bb 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -31,7 +31,7 @@
# This could be handy for archiving the generated documentation or
# if some version control system is used.
-PROJECT_NUMBER = v22.1.0.0
+PROJECT_NUMBER = [DEVELOP-FOR-23.0]
# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
# base path where the generated documentation will be put.
diff --git a/src/base/version.cc b/src/base/version.cc
index 050aea0..8131a31 100644
--- a/src/base/version.cc
+++ b/src/base/version.cc
@@ -32,6 +32,6 @@
/**
* @ingroup api_base_utils
*/
-const char *gem5Version = "22.1.0.0";
+const char *gem5Version = "[DEVELOP-FOR-23.0]";
} // namespace gem5
diff --git a/src/python/gem5/resources/downloader.py
b/src/python/gem5/resources/downloader.py
index f619b97..1fda8d8 100644
--- a/src/python/gem5/resources/downloader.py
+++ b/src/python/gem5/resources/downloader.py
@@ -55,7 +55,7 @@
"""
Specifies the version of resources.json to obtain.
"""
-return "22.1"
+return "develop"
def _get_resources_json_uri() -> str:
diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index 044ceb2..f5d4bb1 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -114,7 +114,7 @@
# targets for this test
build_indices=(${build_permutation[@]:0:$builds_count})
-repo_name="${base_url}/${compiler}:v22-1"
+repo_name="${base_url}/${compiler}:latest"
# Grab compiler image
docker pull $repo_name >/dev/null
diff --git a/tests/jenkins/presubmit.sh b/tests/jenkins/presubmit.sh
index 36da3fa..91eb95f 100755
--- a/tests/jenkins/presubmit.sh
+++ b/tests/jenkins/presubmit.sh
@@ -37,8 +37,8 @@
set -e
-DOCKER_IMAGE_ALL_DEP=gcr.io/gem5-test/ubuntu-22.04_all-dependencies:v22-1
-DOCKER_IMAGE_CLANG_COMPILE=gcr.io/gem5-test/clang-version-14:v22-1
+DOCKER_IMAGE_ALL_DEP=gcr.io/gem5-test/ubuntu-22.04_all-dependencies:latest
+DOCKER_IMAGE_CLANG_COMPILE=gcr.io/gem5-test/clang-version-14:latest
PRESUBMIT_STAGE2=tests/jenkins/presubmit-stage2.sh
GEM5ART_TESTS=tests/jenkins/gem5art-tests.sh
diff --git a/tests/nightly.sh b/tests/nightly.sh
index bf05154..1360c44 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -37,7 +37,7 @@
# The docker tag to use (varies between develop, and versions on the
staging
# branch)
-tag="v22-1"
+tag="latest"
# The first argument is the number of threads to be used for compilation.
If no
# argument is given we default to one.
diff --git a/tests/weekly.sh b/tests/weekly.sh
index 9b400b9..c7f834b 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -37,7 +37,7
[gem5-dev] [M] Change in gem5/gem5[develop]: misc: Merge branch stable into develop branch
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67051?usp=email )
Change subject: misc: Merge branch stable into develop branch
..
misc: Merge branch stable into develop branch
This ensures both branches are in-sync and have not diverged.
Change-Id: Ib487d8596037017b9ec03d7e8a76229373c153db
---
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_engine.hh
4 files changed, 60 insertions(+), 34 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/amdgpu/pm4_packet_processor.cc
b/src/dev/amdgpu/pm4_packet_processor.cc
index 3c832c5..152fd4d 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -458,13 +458,7 @@
SDMAEngine *sdma_eng = gpuDevice->getSDMAById(pkt->engineSel - 2);
// Register RLC queue with SDMA
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2, addr, mqd);
-===
-sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2,
- mqd->rb_base << 8, rlc_size,
- rptr_wb_addr);
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
// Register doorbell with GPU device
gpuDevice->setSDMAEngine(pkt->doorbellOffset << 2, sdma_eng);
diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 0a167bf..4c03bf5 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -165,12 +165,7 @@
}
void
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
SDMAEngine::registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc
*mqd)
-===
-SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr)
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
{
uint32_t rlc_size = 4UL << bits(mqd->sdmax_rlcx_rb_cntl, 6, 1);
Addr rptr_wb_addr = mqd->sdmax_rlcx_rb_rptr_addr_hi;
@@ -185,43 +180,25 @@
rlc0.base(mqd->rb_base << 8);
rlc0.size(rlc_size);
rlc0.rptr(0);
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc0.incRptr(mqd->rptr);
rlc0.setWptr(mqd->wptr);
-===
-rlc0.wptr(0);
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
rlc0.rptrWbAddr(rptr_wb_addr);
rlc0.processing(false);
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc0.setMQD(mqd);
rlc0.setMQDAddr(mqdAddr);
-===
-rlc0.size(size);
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
} else if (!rlc1.valid()) {
DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC1\n", doorbell);
rlcInfo[1] = doorbell;
rlc1.valid(true);
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc1.base(mqd->rb_base << 8);
rlc1.size(rlc_size);
rlc1.rptr(0);
rlc1.incRptr(mqd->rptr);
rlc1.setWptr(mqd->wptr);
-===
-rlc1.base(rb_base);
-rlc1.rptr(0);
-rlc1.wptr(0);
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
rlc1.rptrWbAddr(rptr_wb_addr);
rlc1.processing(false);
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
rlc1.setMQD(mqd);
rlc1.setMQDAddr(mqdAddr);
-===
-rlc1.size(size);
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
} else {
panic("No free RLCs. Check they are properly unmapped.");
}
diff --git a/src/dev/amdgpu/sdma_engine.hh b/src/dev/amdgpu/sdma_engine.hh
index 6a12f97..27c1691 100644
--- a/src/dev/amdgpu/sdma_engine.hh
+++ b/src/dev/amdgpu/sdma_engine.hh
@@ -287,12 +287,7 @@
/**
* Methods for RLC queues
*/
-<<< HEAD (fcde59 util: ext/systemc is importing env Environment
instead of ma)
void registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc *mqd);
-===
-void registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr);
->>> BRANCH (5fa484 misc: Merge the v22.1 release staging into stable)
void unregisterRLCQueue(Addr doorbell);
void deallocateRLCQueues();
--
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Gerrit-Change-Id: Ib487d8596037017b9ec03d7e8a76229373c153db
[gem5-dev] [L] Change in gem5/gem5[develop]: gpu-compute,mem-ruby: Add support for GPU cache bypassing
VISHNU RAMADAS has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66991?usp=email )
(
7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: gpu-compute,mem-ruby: Add support for GPU cache bypassing
..
gpu-compute,mem-ruby: Add support for GPU cache bypassing
The GPU cache models do not support cache bypassing when the GLC or SLC
AMDGPU instruction modifiers are used in a load or store. This commit
adds cache bypass support by introducing new transitions in the
coherence protocol used by the GPU memory system. Now, instructions with
the GLC bit set will not cache in the L1 and instructions with SLC bit
set will not cache in L1 or L2.
Change-Id: Id29a47b0fa7e16a21a7718949db802f85e9897c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66991
Reviewed-by: Jason Lowe-Power
Maintainer: Matt Sinclair
Tested-by: kokoro
Reviewed-by: Matt Sinclair
---
M src/mem/packet.hh
M src/mem/request.hh
M src/mem/ruby/protocol/GPU_VIPER-TCC.sm
M src/mem/ruby/protocol/GPU_VIPER-TCP.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
M src/mem/ruby/protocol/RubySlicc_MemControl.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/RubyRequest.hh
9 files changed, 337 insertions(+), 8 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, but someone else must approve; Looks
good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 9238dbe..a80b918 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -1101,6 +1101,16 @@
}
/**
+ * Accessor functions for the cache bypass flags. The cache bypass
+ * can specify which levels in the hierarchy to bypass. If GLC_BIT
+ * is set, the requests are globally coherent and bypass TCP.
+ * If SLC_BIT is set, then the requests are system level coherent
+ * and bypass both TCP and TCC.
+ */
+bool isGLCSet() const { return req->isGLCSet();}
+bool isSLCSet() const { return req->isSLCSet();}
+
+/**
* Check if packet corresponds to a given block-aligned address and
* address space.
*
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 39d9d72..6a0cbc2 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -1071,6 +1071,17 @@
bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
+
+/**
+ * Accessor functions for the cache bypass flags. The cache bypass
+ * can specify which levels in the hierarchy to bypass. If GLC_BIT
+ * is set, the requests are globally coherent and bypass TCP.
+ * If SLC_BIT is set, then the requests are system level coherent
+ * and bypass both TCP and TCC.
+ */
+bool isGLCSet() const {return _cacheCoherenceFlags.isSet(GLC_BIT); }
+bool isSLCSet() const {return _cacheCoherenceFlags.isSet(SLC_BIT); }
+
/**
* Accessor functions for the memory space configuration flags and
used by
* GPU ISAs such as the Heterogeneous System Architecture (HSA). Note
that
diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
index 032a64c..ae14247 100644
--- a/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
@@ -56,8 +56,10 @@
enumeration(Event, desc="TCC Events") {
// Requests coming from the Cores
RdBlk, desc="RdBlk event";
+RdBypassEvict, desc="Bypass L2 on reads. Evict if cache block
already allocated";
WrVicBlk, desc="L1 Write Through";
WrVicBlkBack, desc="L1 Write Through(dirty cache)";
+WrVicBlkEvict, desc="L1 Write Through(dirty cache) and evict";
Atomic, desc="Atomic Op";
AtomicDone, desc="AtomicOps Complete";
AtomicNotDone, desc="AtomicOps not Complete";
@@ -68,6 +70,7 @@
PrbInv, desc="Invalidating probe";
// Coming from Memory Controller
WBAck, desc="writethrough ack from memory";
+Bypass, desc="Bypass the entire L2 cache";
}
// STATES
@@ -107,6 +110,8 @@
NetDest Destination, desc="Data destination";
int numAtomics, desc="number remaining atomics";
int atomicDoneCnt, desc="number AtomicDones triggered";
+bool isGLCSet, desc="Bypass L1 Cache";
+bool isSLCSet, desc="Bypass L1 and L2 Cache";
}
structure(TBETable, external="yes") {
@@ -173,7 +178,6 @@
int functionalWrite(Addr addr, Packet *pkt) {
int num_functional_writes := 0;
-
TBE tbe := TBEs.lookup(addr);
if(is_valid(tbe)) {
num_functional_writes := num_functional_writes +
@@ -279,7 +283,11 @@
peek(responseFromNB_in, ResponseMsg,
[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Improve error reporting when test definition fails
Gabriel B. has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66892?usp=email )
Change subject: ext-testlib: Improve error reporting when test definition
fails
..
ext-testlib: Improve error reporting when test definition fails
The error reason is now reported as an element in the XML testing result
summary.
Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
---
M ext/testlib/result.py
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 5c60342..786febd 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -191,17 +191,23 @@
def begin(self, file_):
file_.write('<')
file_.write(self.name)
-for attr in self.attributes:
-file_.write(' ')
-attr.write(file_)
+if hasattr(self, 'attributes'):
+for attr in self.attributes:
+file_.write(' ')
+attr.write(file_)
file_.write('>')
self.body(file_)
def body(self, file_):
-for elem in self.elements:
-file_.write('\n')
-elem.write(file_)
+if hasattr(self, 'elements'):
+for elem in self.elements:
+file_.write('\n')
+elem.write(file_)
+if hasattr(self, 'content'):
+file_.write('\n')
+file_.write(
+xml.sax.saxutils.escape(self.content))
file_.write('\n')
def end(self, file_):
@@ -286,17 +292,22 @@
]
if str(test_result.result) == 'Failed':
-self.elements.append(JUnitFailure('Test failed', 'ERROR'))
+self.elements.append(JUnitFailure(
+'Test failed',
+str(test_result.result.reason))
+)
class JUnitFailure(XMLElement):
name = 'failure'
-def __init__(self, message, fail_type):
+def __init__(self, message, cause):
self.attributes = [
XMLAttribute('message', message),
-XMLAttribute('type', fail_type),
]
-self.elements = []
+cause_element = XMLElement()
+cause_element.name = 'cause'
+cause_element.content = cause
+self.elements = [cause_element]
class LargeFileElement(XMLElement):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I18b84422bb9580709cf1c5f2a14a5cbb0caf1876
Gerrit-Change-Number: 66892
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel B.
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: ext-testlib: Support str-convertible args in gem5_verify_config
Gabriel B. has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66893?usp=email )
Change subject: ext-testlib: Support str-convertible args in
gem5_verify_config
..
ext-testlib: Support str-convertible args in gem5_verify_config
gem5_verify_config dit not support string-convertible args due to log_call()
not trying to call str() on them. This patch maps str() on the command
paramters.
It is now possible to pass native integers or even string-like types like
pathlib.Path as arguments without manually converting them to string.
Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
---
M ext/testlib/helper.py
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index ed6e325..ea102f2 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -149,7 +149,14 @@
if isinstance(command, str):
cmdstr = command
else:
-cmdstr = ' '.join(command)
+try:
+command = list(map(str, command))
+cmdstr = " ".join(command)
+except TypeError as e:
+logger.trace(
+"Argument must be an iterable of
string-convertible types"
+)
+raise e
logger_callback = logger.trace
logger.trace('Logging call to command: %s' % cmdstr)
--
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https://gem5-review.googlesource.com/c/public/gem5/+/66893?usp=email
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifa987f5f1a20f17c8710e1a36d99d424e4c9ce6c
Gerrit-Change-Number: 66893
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel B.
Gerrit-MessageType: newchange
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