[gem5-dev] [L] Change in gem5/gem5[develop]: mem: create port_wrapper classes
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67232?usp=email )
Change subject: mem: create port_wrapper classes
..
mem: create port_wrapper classes
The port_wrapper classes convert the Request/ResponsePort from
inherit-base to callback registrations. This help 'composition over
inheritance' that most design pattern follows, which help reducing
code length and increase reusability.
Change-Id: Ia13cc62507ac8425bd7cf143a2e080d041c173f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67232
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/SConscript
A src/mem/port_wrapper.cc
A src/mem/port_wrapper.hh
3 files changed, 347 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 3bcfc0d..ca164c1 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -88,6 +88,7 @@
Source('port.cc')
Source('packet_queue.cc')
Source('port_proxy.cc')
+Source('port_wrapper.cc')
Source('physical.cc')
Source('shared_memory_server.cc')
Source('simple_mem.cc')
diff --git a/src/mem/port_wrapper.cc b/src/mem/port_wrapper.cc
new file mode 100644
index 000..fd5ebbd
--- /dev/null
+++ b/src/mem/port_wrapper.cc
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2023 Google, LLC.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/port_wrapper.hh"
+
+namespace gem5
+{
+
+RequestPortWrapper::RequestPortWrapper(const std::string& name,
+ SimObject* _owner, PortID id)
+: RequestPort(name, _owner, id)
+{
+}
+
+void
+RequestPortWrapper::recvRangeChange()
+{
+if (!recvRangeChangeCb) {
+RequestPort::recvRangeChange();
+return;
+}
+recvRangeChangeCb();
+}
+
+bool
+RequestPortWrapper::recvTimingResp(PacketPtr packet)
+{
+panic_if(!recvTimingRespCb, "RecvTimingRespCallback is empty.");
+return recvTimingRespCb(packet);
+}
+
+void
+RequestPortWrapper::recvReqRetry()
+{
+panic_if(!recvReqRetryCb, "RecvReqRetryCallback is empty.");
+recvReqRetryCb();
+}
+
+void
+RequestPortWrapper::setRangeChangeCallback(RecvReqRetryCallback cb)
+{
+recvRangeChangeCb = std::move(cb);
+}
+
+void
+RequestPortWrapper::setTimingCallbacks(RecvTimingRespCallback resp_cb,
+ RecvReqRetryCallback retry_cb)
+{
+recvTimingRespCb = std::move(resp_cb);
+recvReqRetryCb = std::move(retry_cb);
+}
+
+ResponsePortWrapper::ResponsePortWrapper(const std::string& name,
+ SimObject* _owner, PortID id)
+: ResponsePort(name, _owner, id)
+{
+}
+
+AddrRangeList
+ResponsePortWrapper::getAddrRanges() const
+{
+panic_if(!getAddrRangesCb, "GetAddrRangesCallback is empty.");
+return getAddrRangesCb();
+}
+
+bool
+ResponsePortWrapper::recvTimingReq(PacketPtr packet)
+{
+panic_if(!recvTimingReqCb, "RecvTimingReqCallback is empty.");
+return recvTimingReqCb(packet);
+}
+
+void
+ResponsePortWrapper::recvRespRetry()
+{
+panic_if(!recvRespRetryCb, "RecvRespRetryCallback is empty.");
+recvRespRetryCb();
+}
+
+Tick
+ResponsePortWrapper::recvAtomic(PacketPtr packet)
+{
+panic_if(!recvAtomicCb, "RecvAtomicCallback is empty.");
+return recvAtomicCb(packet);
+}
+
+Tick
+ResponsePortWrapper::recvAtomicBackdoor(PacketPtr packet,
+
[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: fix -Wno-free-nonheap-object for building scheduler.cc
Earl Ou has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email )
Change subject: systemc: fix -Wno-free-nonheap-object for building
scheduler.cc
..
systemc: fix -Wno-free-nonheap-object for building scheduler.cc
-Wno-free-nonheap-object can happen at compile or link time depending on
the versions. To better disable this false alarm, we move the memory
management part into .cc file, so the check is always done at link time.
This change also removes the global flags so other code is still checked
with the flags.
Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67237
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
---
M SConstruct
M src/sim/eventq.cc
M src/sim/eventq.hh
M src/systemc/core/SConscript
4 files changed, 52 insertions(+), 22 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index bd26e45..e08c2984 100755
--- a/SConstruct
+++ b/SConstruct
@@ -447,10 +447,6 @@
error('gcc version 7 or newer required.\n'
'Installed version:', env['CXXVERSION'])
-with gem5_scons.Configure(env) as conf:
-# This warning has a false positive in the systemc in g++ 11.1.
-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
# Add the appropriate Link-Time Optimization (LTO) flags if
# `--with-lto` is set.
if GetOption('with_lto'):
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 66d0385..23ca2f6 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -109,6 +109,32 @@
}
void
+Event::acquire()
+{
+if (flags.isSet(Event::Managed))
+acquireImpl();
+}
+
+void
+Event::release()
+{
+if (flags.isSet(Event::Managed))
+releaseImpl();
+}
+
+void
+Event::acquireImpl()
+{
+}
+
+void
+Event::releaseImpl()
+{
+if (!scheduled())
+delete this;
+}
+
+void
EventQueue::insert(Event *event)
{
// Deal with the head case
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index cd5d285f..62495bf 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -381,26 +381,16 @@
/**
* Managed event scheduled and being held in the event queue.
*/
-void acquire()
-{
-if (flags.isSet(Event::Managed))
-acquireImpl();
-}
+void acquire();
/**
* Managed event removed from the event queue.
*/
-void release() {
-if (flags.isSet(Event::Managed))
-releaseImpl();
-}
+void release();
-virtual void acquireImpl() {}
+virtual void acquireImpl();
-virtual void releaseImpl() {
-if (!scheduled())
-delete this;
-}
+virtual void releaseImpl();
/** @} */
diff --git a/src/systemc/core/SConscript b/src/systemc/core/SConscript
index 2b88111..c7c9dbb 100644
--- a/src/systemc/core/SConscript
+++ b/src/systemc/core/SConscript
@@ -40,6 +40,7 @@
Source('port.cc')
Source('process.cc')
Source('sched_event.cc')
+Source('scheduler.cc')
Source('sensitivity.cc')
Source('time.cc')
@@ -75,7 +76,4 @@
# Disable the false positive warning for the event members of the
scheduler.
with gem5_scons.Configure(env) as conf:
flag = '-Wno-free-nonheap-object'
-append = {}
-if conf.CheckCxxFlag(flag, autoadd=False):
-append['CCFLAGS'] = [flag]
-Source('scheduler.cc', append=append)
+conf.CheckLinkFlag(flag)
--
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https://gem5-review.googlesource.com/c/public/gem5/+/67237?usp=email
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8f1e20197b25c90b5f439e2ecc474bd99e4f82ed
Gerrit-Change-Number: 67237
Gerrit-PatchSet: 3
Gerrit-Owner: Earl Ou
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-CC: Nicolas Boichat
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: nightly #482
Hi Bobby,
Just checking on this again.
Thanks,
Matt
On Mon, Jan 9, 2023 at 11:21 PM Matt Sinclair
wrote:
> Bobby do you need me to clean up the machine or open a ticket with IT at
> UW:
>
> *19:22:13* {standard input}: Fatal error: can't write 97 bytes to section
> .text of build/ARM/python/_m5/param_TickedObject.o: 'No space left on device'
>
> Matt
>
> On Mon, Jan 9, 2023 at 7:23 PM jenkins-no-reply--- via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> See <
>> https://jenkins.gem5.org/job/nightly/482/display/redirect?page=changes>
>>
>> Changes:
>>
>> [mattdsinclair] mem-ruby, gpu-compute: fix TCP GLC cache bypassing
>>
>> [mattdsinclair] mem-ruby: fix TCP spacing/spelling
>>
>> [mattdsinclair] mem-ruby: add GPU cache bypass I->I transition
>>
>>
>> --
>> [...truncated 4.09 MB...]
>> [SO Param] m5.objects.Cache_Controller, Cache_Controller ->
>> ARM/python/_m5/param_Cache_Controller.cc
>> [ CXX] ARM/mem/ruby/protocol/Cache_DirEntry.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_Event.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_ReplacementMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_RequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_RetryQueueEntry.cc -> .o
>> [ CXX] ARM/python/_m5/param_Cache_Controller.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_RetryTriggerMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_State.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_TBE.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_Transitions.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_TriggerMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Cache_Wakeup.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/DMASequencerRequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/DirectoryRequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/HtmCallbackMode.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/HtmFailedInCacheReason.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/InvalidateGeneratorStatus.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/LinkDirection.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/LockStatus.cc -> .o
>> [SO Param] m5.objects.Memory_Controller, Memory_Controller ->
>> ARM/params/Memory_Controller.hh
>> [SO Param] m5.objects.MiscNode_Controller, MiscNode_Controller ->
>> ARM/params/MiscNode_Controller.hh
>> [ CXX] ARM/mem/ruby/protocol/MaskPredictorIndex.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MaskPredictorTraining.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MaskPredictorType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MemoryControlRequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MemoryMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MemoryRequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MachineType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_Controller.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_Controller.py.cc -> .o
>> [SO Param] m5.objects.Memory_Controller, Memory_Controller ->
>> ARM/python/_m5/param_Memory_Controller.cc
>> [ CXX] ARM/mem/ruby/protocol/Memory_Event.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_RetryQueueEntry.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_State.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_TBE.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_Transitions.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_TriggerMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/Memory_Wakeup.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MessageSizeType.cc -> .o
>> [ CXX] ARM/python/_m5/param_Memory_Controller.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_Controller.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_Controller.py.cc -> .o
>> [SO Param] m5.objects.MiscNode_Controller, MiscNode_Controller ->
>> ARM/python/_m5/param_MiscNode_Controller.cc
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_Event.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_RetryQueueEntry.cc -> .o
>> [ CXX] ARM/python/_m5/param_MiscNode_Controller.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_RetryTriggerMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_State.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_TBE.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_Transitions.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_TriggerMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/MiscNode_Wakeup.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/PrefetchBit.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/RequestStatus.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/RubyAccessMode.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/RubyRequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/SequencerMsg.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/SequencerRequestType.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/SequencerStatus.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/SeriesRequestGeneratorStatus.cc -> .o
>> [ CXX] ARM/mem/ruby/protocol/TesterStatus.cc
