date:20230203

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export the reset signals of the GIC.

2023-02-03 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67575?usp=email )


Change subject: fastmodel: Export the reset signals of the GIC.
..

fastmodel: Export the reset signals of the GIC.

These are the "reset" and "po_reset" lines. It seems reasonable that
these are the normal reset and the power on reset signals, but that's
not spelled out in the fast model "lisa" file, nor does it explain
exactly what the difference is between them.

Change-Id: I686b4d973fc3cfff8a3ec05f8c95ee2cb6ff6698
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67575
Reviewed-by: Jui-min Lee 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/fastmodel/GIC/GIC.lisa
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
4 files changed, 54 insertions(+), 1 deletion(-)

Approvals:
  Jui-min Lee: Looks good to me, approved
  kokoro: Regressions pass
  Gabe Black: Looks good to me, approved




diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py  
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py

index ce0a8c5..b1a9a3c 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -42,6 +42,7 @@
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.Gic import BaseGic
 from m5.objects.IntPin import VectorIntSourcePin
+from m5.objects.ResetPort import ResetResponsePort
 from m5.objects.SystemC import SystemC_ScModule

 GICV3_COMMS_TARGET_ROLE = "GICV3 COMMS TARGET"
@@ -850,6 +851,9 @@

 wake_request = VectorIntSourcePin("GIC wake request initiator")

+reset = ResetResponsePort("Reset")
+po_reset = ResetResponsePort("Power on reset")
+
 # Used for DTB autogeneration
 _state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)

diff --git a/src/arch/arm/fastmodel/GIC/GIC.lisa  
b/src/arch/arm/fastmodel/GIC/GIC.lisa

index 34b09c8..5443b55 100644
--- a/src/arch/arm/fastmodel/GIC/GIC.lisa
+++ b/src/arch/arm/fastmodel/GIC/GIC.lisa
@@ -56,6 +56,10 @@
 // Outgoing wake requests.
 gic.wake_request => self.wake_request;

+// Reset signals.
+self.normal_reset => gic.reset;
+self.po_reset => gic.po_reset;
+
 // Internal ports for PPI and SPI programmatic access.
 self.ppi_0 => gic.ppi_in_0;
 self.ppi_1 => gic.ppi_in_1;
@@ -405,6 +409,9 @@
 }
 }

+slave port normal_reset;
+slave port po_reset;
+
 internal slave port spi[988];

 internal slave port ppi_0[16];
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc  
b/src/arch/arm/fastmodel/GIC/gic.cc

index 493aa81..5f01cfb 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -72,10 +72,15 @@

 SCGIC::SCGIC(const SCFastModelGICParams ,
  sc_core::sc_module_name _name)
-: scx_evs_GIC(_name), _params(params)
+: scx_evs_GIC(_name), _params(params),
+  resetPort(params.name + ".reset", 0),
+  poResetPort(params.name + ".po_reset", 0)
 {
 signalInterrupt.bind(signal_interrupt);

+resetPort.signal_out.bind(scx_evs_GIC::normal_reset);
+poResetPort.signal_out.bind(scx_evs_GIC::po_reset);
+
 for (int i = 0; i < wake_request.size(); i++) {
 wakeRequests.emplace_back(
 new SignalReceiver(csprintf("%s.wakerequest[%d]", name(), i)));
@@ -298,6 +303,18 @@
 set_parameter("gic.consolidators", params.consolidators);
 }

+Port &
+SCGIC::gem5_getPort(const std::string _name, int idx)
+{
+if (if_name == "reset") {
+return resetPort;
+} else if (if_name == "po_reset") {
+return poResetPort;
+} else {
+return scx_evs_GIC::gem5_getPort(if_name, idx);
+}
+}
+
 void
 SCGIC::before_end_of_elaboration()
 {
@@ -341,6 +358,8 @@
 return *ptr;
 } else if (if_name == "wake_request") {
 return *wakeRequestPorts.at(idx);
+} else if (if_name == "reset" || if_name == "po_reset") {
+return scGIC->gem5_getPort(if_name, idx);
 } else {
 return BaseGic::getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh  
b/src/arch/arm/fastmodel/GIC/gic.hh

index 0e502fc..070fe3b 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -37,6 +37,7 @@

 #include "arch/arm/fastmodel/amba_ports.hh"
 #include "arch/arm/fastmodel/common/signal_receiver.hh"
+#include "arch/arm/fastmodel/common/signal_sender.hh"
 #include "dev/arm/base_gic.hh"
 #include "dev/intpin.hh"
 #include "params/FastModelGIC.hh"
@@ -91,9 +92,13 @@
 SCGIC(const SCFastModelGICParams ) : SCGIC(p, p.name.c_str()) {}
 SCGIC(const SCFastModelGICParams , sc_core::sc_module_name  
_name);


+Port _getPort(const std::string _name, int idx) override;
+
 SignalInterruptInitiatorSocket signalInterrupt;

 std::vector> wakeRequests;
+SignalSender

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: forward stream ID to gem5

2023-02-03 Thread Wei-Han Chen (Gerrit) via gem5-dev

Wei-Han Chen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67591?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: forward stream ID to gem5
..

fastmodel: forward stream ID to gem5

This CL enables forwarding stream ID from amba_pv to gem5 world.

The stream ID information is originally stored in master_id of
pv::TransactionAtrribute, then it will be stored to m_id of
amba_pv::amba_pv_extension.

This CL brings the information to stream ID field of
Gem5SystemC::ControlExtension. Then the information can be set to stream
ID of the gem5 packet's request.

After bringing the information to gem5, we can identify the packet's
stream ID from gem5 side. One example usage is PL330. In PL330_DMAC, each
transaction is associated with a stream ID. If we can identitfy the
stream ID, we can, for example, set attribute to specific DMAC channel.

Change-Id: I943ce49fde57b0bcfc18b58c7566eec61cc676f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67591
Reviewed-by: Yu-hsin Wang 
Tested-by: kokoro 
Maintainer: Gabe Black 
---
M src/arch/arm/fastmodel/FastModel.py
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
3 files changed, 39 insertions(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Yu-hsin Wang: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/fastmodel/FastModel.py  
b/src/arch/arm/fastmodel/FastModel.py

index 8a28522..1ea3c5e 100644
--- a/src/arch/arm/fastmodel/FastModel.py
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -108,6 +108,10 @@
 amba = AmbaTargetSocket(64, "AMBA PV target socket")
 tlm = TlmInitiatorSocket(64, "TLM initiator socket")

+set_stream_id = Param.Bool(
+False, "Set this true to forward stream ID to gem5 world"
+)
+

 class AmbaFromTlmBridge64(SystemC_ScModule):
 type = "AmbaFromTlmBridge64"
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc  
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc

index 888e077..2f065fc 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -77,7 +77,8 @@
 targetProxy("target_proxy"),
 initiatorProxy("initiator_proxy"),
 tlmWrapper(initiatorProxy, std::string(name) + ".tlm", -1),
-ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1)
+ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1),
+setStreamId(params.set_stream_id)
 {
 targetProxy.register_b_transport(this, ::bTransport);
 targetProxy.register_get_direct_mem_ptr(
@@ -191,6 +192,10 @@
 control_ex->setSecure(!amba_ex->is_non_secure());
 control_ex->setInstruction(amba_ex->is_instruction());

+if (setStreamId) {
+control_ex->setStreamId(amba_ex->get_id());
+}
+
 if (trans.has_mm()) {
 trans.set_auto_extension(control_ex);
 } else {
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh  
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh

index 176d31f..6729604 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -71,6 +71,7 @@
 AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types>  
initiatorProxy;

 sc_gem5::TlmInitiatorWrapper<64> tlmWrapper;
 AmbaTarget ambaWrapper;
+bool setStreamId;
 };

 } // namespace fastmodel

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I943ce49fde57b0bcfc18b58c7566eec61cc676f4
Gerrit-Change-Number: 67591
Gerrit-PatchSet: 3
Gerrit-Owner: Wei-Han Chen 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Wei-Han Chen 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: change the constructor of bridges

2023-02-03 Thread Wei-Han Chen (Gerrit) via gem5-dev

Wei-Han Chen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67297?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: fastmodel: change the constructor of bridges
..

fastmodel: change the constructor of bridges

This CL changes the construction of bridges between amba and tlm. This
enables us to add parameters when using this bridge.

Change-Id: I4bbbe8fb1c2573a796a3a0a7976adf3553bbaa86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67297
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
4 files changed, 33 insertions(+), 18 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Gabe Black: Looks good to me, approved




diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc  
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc

index 4baf0ef..8db0d6a 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
@@ -37,7 +37,9 @@
 namespace fastmodel
 {

-AmbaFromTlmBridge64::AmbaFromTlmBridge64(const sc_core::sc_module_name&  
name) :

+AmbaFromTlmBridge64::AmbaFromTlmBridge64(
+const AmbaFromTlmBridge64Params ,
+const sc_core::sc_module_name& name) :
 amba_pv::amba_pv_from_tlm_bridge<64>(name),
 targetProxy("target_proxy"),
 initiatorProxy("initiator_proxy"),
@@ -116,11 +118,4 @@
 }

 } // namespace fastmodel
-
-fastmodel::AmbaFromTlmBridge64 *
-AmbaFromTlmBridge64Params::create() const
-{
-return new fastmodel::AmbaFromTlmBridge64(name.c_str());
-}
-
 } // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh  
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh

index 8ea8b8a..11f7b5d 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
@@ -33,6 +33,7 @@
 #include "amba_pv.h"
 #pragma GCC diagnostic pop
 #include "arch/arm/fastmodel/amba_ports.hh"
+#include "params/AmbaFromTlmBridge64.hh"
 #include "systemc/tlm_port_wrapper.hh"

 namespace gem5
@@ -46,7 +47,11 @@
 class AmbaFromTlmBridge64 : public amba_pv::amba_pv_from_tlm_bridge<64>
 {
   public:
-AmbaFromTlmBridge64(const sc_core::sc_module_name );
+AmbaFromTlmBridge64(const AmbaFromTlmBridge64Params ,
+const sc_core::sc_module_name );
+AmbaFromTlmBridge64(const AmbaFromTlmBridge64Params ) :
+  AmbaFromTlmBridge64(params, params.name.c_str())
+{}

 gem5::Port _getPort(const std::string _name, int idx=-1)  
override;


diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc  
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc

index 58f6eea..888e077 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -71,7 +71,8 @@
 namespace fastmodel
 {

-AmbaToTlmBridge64::AmbaToTlmBridge64(const sc_core::sc_module_name& name) :
+AmbaToTlmBridge64::AmbaToTlmBridge64(const AmbaToTlmBridge64Params ,
+ const sc_core::sc_module_name& name) :
 amba_pv::amba_pv_to_tlm_bridge<64>(name),
 targetProxy("target_proxy"),
 initiatorProxy("initiator_proxy"),
@@ -198,11 +199,4 @@
 }

 } // namespace fastmodel
-
-fastmodel::AmbaToTlmBridge64 *
-AmbaToTlmBridge64Params::create() const
-{
-return new fastmodel::AmbaToTlmBridge64(name.c_str());
-}
-
 } // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh  
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh

index addaac6..176d31f 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -33,6 +33,7 @@
 #include "amba_pv.h"
 #pragma GCC diagnostic pop
 #include "arch/arm/fastmodel/amba_ports.hh"
+#include "params/AmbaToTlmBridge64.hh"
 #include "systemc/tlm_port_wrapper.hh"

 namespace gem5
@@ -46,7 +47,11 @@
 class AmbaToTlmBridge64 : public amba_pv::amba_pv_to_tlm_bridge<64>
 {
   public:
-AmbaToTlmBridge64(const sc_core::sc_module_name );
+AmbaToTlmBridge64(const AmbaToTlmBridge64Params ,
+  const sc_core::sc_module_name );
+AmbaToTlmBridge64(const AmbaToTlmBridge64Params ) :
+  AmbaToTlmBridge64(params, params.name.c_str())
+{}

 gem5::Port _getPort(const std::string _name, int idx=-1)  
override;



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4bbbe8fb1c2573a796a3a0a7976adf3553bbaa86
Gerrit-Change-Number: 67297

[gem5-dev] Build failed in Jenkins: compiler-checks #507

2023-02-03 Thread jenkins-no-reply--- via gem5-dev

See 


Changes:

[gabriel.busnot] base: Strengthen safe_cast and make it work for reference types

[gabriel.busnot] tests: Make the GTestException type accessible to unit tests

[gabriel.busnot] mem: Deprecate RequestPort and ResponsePort owner ref member

[gabriel.busnot] mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port 
owner

[gabriel.busnot] sim: Suppress deleted operator= warn in Sys::Threads::const_it

[gabriel.busnot] base: Enable non-copiable types in gem5_assert message 
formatting

[gabriel.busnot] base: Turn all logging.hh macros into expression kind

[gabe.black] arch-riscv: Get rid of redundant reset fault invocation.

[gabe.black] arch: Add a virtual method to the BaseISA to reset its 
ThreadContext.

[gabe.black] arch-riscv: Implement the resetThread method on the ISA object.


--
[...truncated 1.30 KB...]
 > git checkout -f c9719b44a3ce69b65012ce180142c6014127f718 # timeout=10
Commit message: "arch-riscv: Implement the resetThread method on the ISA 
object."
 > git rev-list --no-walk 1b949e975922b03e5366011a646c3a41b298dc51 # timeout=10
[Checks API] No suitable checks publisher found.
[compiler-checks] $ /bin/sh -xe /tmp/jenkins11320208856416589988.sh
+ ./tests/compiler-tests.sh -j 16
Starting build tests with 'gcc-version-12'...
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Starting build tests with 'gcc-version-8'...
  *

[gem5-dev] Re: Build failed in Jenkins: nightly #509

2023-02-03 Thread Bobby Bruce via gem5-dev

Gabriel,

It looks like the nightly tests failed due to some of the ports not being
updated correctly. Do you have time to look into this and fix it?

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Feb 3, 2023 at 8:23 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/509/display/redirect?page=changes>
>
> Changes:
>
> [shunhsingou] dev: terminal: run pollevent in terminal eventq
>
> [gabriel.busnot] base: Strengthen safe_cast and make it work for reference
> types
>
> [gabriel.busnot] tests: Make the GTestException type accessible to unit
> tests
>
> [gabriel.busnot] mem: Deprecate RequestPort and ResponsePort owner ref
> member
>
> [gabriel.busnot] mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base
> port owner
>
> [gabriel.busnot] sim: Suppress deleted operator= warn in
> Sys::Threads::const_it
>
> [gabriel.busnot] base: Enable non-copiable types in gem5_assert message
> formatting
>
> [gabriel.busnot] base: Turn all logging.hh macros into expression kind
>
> [gabe.black] arch-riscv: Get rid of redundant reset fault invocation.
>
> [gabe.black] arch: Add a virtual method to the BaseISA to reset its
> ThreadContext.
>
> [gabe.black] arch-riscv: Implement the resetThread method on the ISA
> object.
>
>
> --
> [...truncated 1.08 MB...]
>  [ TRACING]  -> VEGA_X86/debug/Ruby.cc
>  [ CXX] VEGA_X86/mem/ruby/common/Address.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/BoolVec.cc -> .o
>  [ TRACING]  -> VEGA_X86/debug/Ruby.hh
>  [ CXX] VEGA_X86/debug/Ruby.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/Consumer.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/DataBlock.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/Histogram.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/IntVec.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/NetDest.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/SubBlock.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/common/WriteMask.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/system/GPUCoalescer.py.cc -> .o
>  [SO Param] m5.objects.GPUCoalescer, RubyGPUCoalescer ->
> VEGA_X86/python/_m5/param_RubyGPUCoalescer.cc
>  [ CXX] VEGA_X86/mem/ruby/system/RubySystem.py.cc -> .o
>  [SO Param] m5.objects.RubySystem, RubySystem ->
> VEGA_X86/python/_m5/param_RubySystem.cc
>  [ CXX] VEGA_X86/mem/ruby/system/Sequencer.py.cc -> .o
>  [SO Param] m5.objects.GPUCoalescer, RubyGPUCoalescer ->
> VEGA_X86/params/RubyGPUCoalescer.hh
>  [MAKE INC] VEGA_X86/mem/ruby/slicc_interface/Message.hh ->
> protocol/Message.hh
>  [MAKE INC] VEGA_X86/mem/ruby/slicc_interface/RubyRequest.hh ->
> protocol/RubyRequest.hh
>  [SO Param] m5.objects.RubyCache, RubyCache -> VEGA_X86/params/RubyCache.hh
>  [ CXX] VEGA_X86/python/_m5/param_RubySystem.cc -> .o
>  [SO Param] m5.objects.Sequencer, RubySequencer ->
> VEGA_X86/params/RubySequencer.hh
>  [SO Param] m5.objects.DirectoryMemory, RubyDirectoryMemory ->
> VEGA_X86/params/RubyDirectoryMemory.hh
>  [SO Param] m5.objects.Sequencer, RubyPort ->
> VEGA_X86/python/_m5/param_RubyPort.cc
>  [SO Param] m5.objects.Sequencer, RubyPortProxy ->
> VEGA_X86/python/_m5/param_RubyPortProxy.cc
>  [SO Param] m5.objects.Sequencer, RubySequencer ->
> VEGA_X86/python/_m5/param_RubySequencer.cc
>  [SO Param] m5.objects.Sequencer, RubyHTMSequencer ->
> VEGA_X86/python/_m5/param_RubyHTMSequencer.cc
>  [SO Param] m5.objects.Sequencer, DMASequencer ->
> VEGA_X86/python/_m5/param_DMASequencer.cc
>  [ CXX] VEGA_X86/mem/ruby/system/VIPERCoalescer.py.cc -> .o
>  [ CXX] VEGA_X86/python/_m5/param_RubyGPUCoalescer.cc -> .o
>  [SO Param] m5.objects.VIPERCoalescer, VIPERCoalescer ->
> VEGA_X86/python/_m5/param_VIPERCoalescer.cc
>  [ CXX] VEGA_X86/python/_m5/param_RubyPort.cc -> .o
>  [ CXX] VEGA_X86/python/_m5/param_RubySequencer.cc -> .o
>  [SO Param] m5.objects.Sequencer, RubyHTMSequencer ->
> VEGA_X86/params/RubyHTMSequencer.hh
>  [SO Param] m5.objects.Sequencer, RubyPortProxy ->
> VEGA_X86/params/RubyPortProxy.hh
>  [SO Param] m5.objects.Sequencer, DMASequencer ->
> VEGA_X86/params/DMASequencer.hh
>  [SO Param] m5.objects.VIPERCoalescer, VIPERCoalescer ->
> VEGA_X86/params/VIPERCoalescer.hh
>  [ CXX] VEGA_X86/mem/ruby/system/CacheRecorder.cc -> .o
>  [MAKE INC] VEGA_X86/mem/ruby/common/DataBlock.hh -> protocol/DataBlock.hh
>  [MAKE INC] VEGA_X86/mem/ruby/common/WriteMask.hh -> protocol/WriteMask.hh
>  [ CXX] VEGA_X86/mem/ruby/system/GPUCoalescer.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/system/RubyPort.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/system/HTMSequencer.cc -> .o
>  [ CXX] VEGA_X86/python/_m5/param_RubyPortProxy.cc -> .o
>  [ CXX] VEGA_X86/python/_m5/param_RubyHTMSequencer.cc -> .o
>  [ CXX] VEGA_X86/mem/ruby/system/DMASequencer.cc -> .o
>  [ CXX] VEGA_X86/python/_m5/param_DMASequencer.cc -> .o
>  [ CXX] VEGA_X86/python/_m5/param_VIPERCoalescer.cc -> .o
>

[gem5-dev] Question: Does these code in O3CPU stages is redundant?

2023-02-03 Thread PY D via gem5-dev

Hello, I'm studying on O3CPU, version 22.0.0.2.
And I saw this in rename.Rename::squash(const InstSeqNum _seq_num,
ThreadID tid),
starting from line 368,

 // Squash any instructions from decode.
 for (int i=0; isize; i++) {
 if (fromDecode->insts[i]->threadNumber == tid &&
 fromDecode->insts[i]->seqNum > squash_seq_num) {
 fromDecode->insts[i]->setSquashed();
 wroteToTimeBuffer = true;
 }

 }

 // Clear the instruction list and skid buffer in case they have any
 // insts in them.
 insts[tid].clear();

 // Clear the skid buffer in case it has any data in it.
 skidBuffer[tid].clear();


My question is, the `fromDecode->inst` should already be inserted in
variable `insts` in `sortInsts()`, but the code first set the
fromDecode->insts[I] to squashed() by
`fromDecode->insts[i]->setSquashed();` and clear the `insts` (The
InstQueue), is this for-loop a redundant?

In my opinion, these cleared instructions won't need the "squashed"
information, it doesn't matter.
-- 
Best regards,
DPY
ᐧ
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[gem5-dev] Build failed in Jenkins: nightly #509

2023-02-03 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[shunhsingou] dev: terminal: run pollevent in terminal eventq

[gabriel.busnot] base: Strengthen safe_cast and make it work for reference types

[gabriel.busnot] tests: Make the GTestException type accessible to unit tests

[gabriel.busnot] mem: Deprecate RequestPort and ResponsePort owner ref member

[gabriel.busnot] mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port 
owner

[gabriel.busnot] sim: Suppress deleted operator= warn in Sys::Threads::const_it

[gabriel.busnot] base: Enable non-copiable types in gem5_assert message 
formatting

[gabriel.busnot] base: Turn all logging.hh macros into expression kind

[gabe.black] arch-riscv: Get rid of redundant reset fault invocation.

[gabe.black] arch: Add a virtual method to the BaseISA to reset its 
ThreadContext.

[gabe.black] arch-riscv: Implement the resetThread method on the ISA object.


--
[...truncated 1.08 MB...]
 [ TRACING]  -> VEGA_X86/debug/Ruby.cc
 [ CXX] VEGA_X86/mem/ruby/common/Address.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/BoolVec.cc -> .o
 [ TRACING]  -> VEGA_X86/debug/Ruby.hh
 [ CXX] VEGA_X86/debug/Ruby.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/Consumer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/DataBlock.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/Histogram.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/IntVec.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/NetDest.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/SubBlock.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/WriteMask.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/GPUCoalescer.py.cc -> .o
 [SO Param] m5.objects.GPUCoalescer, RubyGPUCoalescer -> 
VEGA_X86/python/_m5/param_RubyGPUCoalescer.cc
 [ CXX] VEGA_X86/mem/ruby/system/RubySystem.py.cc -> .o
 [SO Param] m5.objects.RubySystem, RubySystem -> 
VEGA_X86/python/_m5/param_RubySystem.cc
 [ CXX] VEGA_X86/mem/ruby/system/Sequencer.py.cc -> .o
 [SO Param] m5.objects.GPUCoalescer, RubyGPUCoalescer -> 
VEGA_X86/params/RubyGPUCoalescer.hh
 [MAKE INC] VEGA_X86/mem/ruby/slicc_interface/Message.hh -> protocol/Message.hh
 [MAKE INC] VEGA_X86/mem/ruby/slicc_interface/RubyRequest.hh -> 
protocol/RubyRequest.hh
 [SO Param] m5.objects.RubyCache, RubyCache -> VEGA_X86/params/RubyCache.hh
 [ CXX] VEGA_X86/python/_m5/param_RubySystem.cc -> .o
 [SO Param] m5.objects.Sequencer, RubySequencer -> 
VEGA_X86/params/RubySequencer.hh
 [SO Param] m5.objects.DirectoryMemory, RubyDirectoryMemory -> 
VEGA_X86/params/RubyDirectoryMemory.hh
 [SO Param] m5.objects.Sequencer, RubyPort -> 
VEGA_X86/python/_m5/param_RubyPort.cc
 [SO Param] m5.objects.Sequencer, RubyPortProxy -> 
VEGA_X86/python/_m5/param_RubyPortProxy.cc
 [SO Param] m5.objects.Sequencer, RubySequencer -> 
VEGA_X86/python/_m5/param_RubySequencer.cc
 [SO Param] m5.objects.Sequencer, RubyHTMSequencer -> 
VEGA_X86/python/_m5/param_RubyHTMSequencer.cc
 [SO Param] m5.objects.Sequencer, DMASequencer -> 
VEGA_X86/python/_m5/param_DMASequencer.cc
 [ CXX] VEGA_X86/mem/ruby/system/VIPERCoalescer.py.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyGPUCoalescer.cc -> .o
 [SO Param] m5.objects.VIPERCoalescer, VIPERCoalescer -> 
VEGA_X86/python/_m5/param_VIPERCoalescer.cc
 [ CXX] VEGA_X86/python/_m5/param_RubyPort.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubySequencer.cc -> .o
 [SO Param] m5.objects.Sequencer, RubyHTMSequencer -> 
VEGA_X86/params/RubyHTMSequencer.hh
 [SO Param] m5.objects.Sequencer, RubyPortProxy -> 
VEGA_X86/params/RubyPortProxy.hh
 [SO Param] m5.objects.Sequencer, DMASequencer -> 
VEGA_X86/params/DMASequencer.hh
 [SO Param] m5.objects.VIPERCoalescer, VIPERCoalescer -> 
VEGA_X86/params/VIPERCoalescer.hh
 [ CXX] VEGA_X86/mem/ruby/system/CacheRecorder.cc -> .o
 [MAKE INC] VEGA_X86/mem/ruby/common/DataBlock.hh -> protocol/DataBlock.hh
 [MAKE INC] VEGA_X86/mem/ruby/common/WriteMask.hh -> protocol/WriteMask.hh
 [ CXX] VEGA_X86/mem/ruby/system/GPUCoalescer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/RubyPort.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/HTMSequencer.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyPortProxy.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyHTMSequencer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/DMASequencer.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_DMASequencer.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_VIPERCoalescer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/RubyPortProxy.cc -> .o
 [SO Param] m5.objects.Network, RubyNetwork -> VEGA_X86/params/RubyNetwork.hh
 [SO Param] m5.objects.BasicLink, BasicExtLink -> 
VEGA_X86/params/BasicExtLink.hh
 [SO Param] m5.objects.BasicLink, BasicIntLink -> 
VEGA_X86/params/BasicIntLink.hh
 [SO Param] m5.objects.BasicLink, BasicLink -> VEGA_X86/params/BasicLink.hh
 [SO Param] m5.objects.BasicRouter, BasicRouter -> 
VEGA_X86/params/BasicRouter.hh
 [ CXX] VEGA_X86/mem/ruby/system/Sequencer.cc -> .o
 [ CXX]

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export the reset signals of the GIC.

[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: forward stream ID to gem5

[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: change the constructor of bridges

[gem5-dev] Build failed in Jenkins: compiler-checks #507

[gem5-dev] Re: Build failed in Jenkins: nightly #509

[gem5-dev] Question: Does these code in O3CPU stages is redundant?

[gem5-dev] Build failed in Jenkins: nightly #509

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