date:20230207

[gem5-dev] [S] Change in gem5/gem5[develop]: sim: handle async events in main thread only

2023-02-07 Thread Earl Ou (Gerrit) via gem5-dev

Earl Ou has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67533?usp=email )


Change subject: sim: handle async events in main thread only
..

sim: handle async events in main thread only

In the current implementation pollqueue is not thread safe. The design
of multi threads handle async events is thus causing issue in parallel
environment. Given the low rate of async events, it should be OK to only
handle them in the main thread to avoid unexpected racing issues.

Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67533
Reviewed-by: Gabe Black 
Reviewed-by: Yu-hsin Wang 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/sim/simulate.cc
1 file changed, 23 insertions(+), 24 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 86d516d..abd2b1d 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -43,7 +43,6 @@
 #include "sim/simulate.hh"

 #include 
-#include 
 #include 

 #include "base/logging.hh"
@@ -274,28 +273,6 @@


 /**
- * Test and clear the global async_event flag, such that each time the
- * flag is cleared, only one thread returns true (and thus is assigned
- * to handle the corresponding async event(s)).
- */
-static bool
-testAndClearAsyncEvent()
-{
-static std::mutex mutex;
-
-bool was_set = false;
-mutex.lock();
-
-if (async_event) {
-was_set = true;
-async_event = false;
-}
-
-mutex.unlock();
-return was_set;
-}
-
-/**
  * The main per-thread simulation loop. This loop is executed by all
  * simulation threads (the main thread and the subordinate threads) in
  * parallel.
@@ -307,6 +284,8 @@
 curEventQueue(eventq);
 eventq->handleAsyncInsertions();

+bool mainQueue = eventq == getEventQueue(0);
+
 while (1) {
 // there should always be at least one event (the SimLoopExitEvent
 // we just scheduled) in the queue
@@ -314,7 +293,8 @@
 assert(curTick() <= eventq->nextTick() &&
"event scheduled in the past");

-if (async_event && testAndClearAsyncEvent()) {
+if (mainQueue && async_event) {
+async_event = false;
 // Take the event queue lock in case any of the service
 // routines want to schedule new events.
 std::lock_guard lock(*eventq);

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iddd512235e84e9d77f60985bb1771aa4cc693004
Gerrit-Change-Number: 67533
Gerrit-PatchSet: 7
Gerrit-Owner: Earl Ou 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: use default backdoor behavior for thread_bridge

2023-02-07 Thread Earl Ou (Gerrit) via gem5-dev

Earl Ou has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67531?usp=email )


Change subject: mem: use default backdoor behavior for thread_bridge
..

mem: use default backdoor behavior for thread_bridge

The original backdoor implementation is incorrect. We use simply
fallback to default (disable backdoor) as backdoor across threads is not
thread-safe in most of cases.

Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67531
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
---
M src/mem/thread_bridge.cc
M src/mem/thread_bridge.hh
2 files changed, 17 insertions(+), 18 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved




diff --git a/src/mem/thread_bridge.cc b/src/mem/thread_bridge.cc
index 0090e42..5af2a59 100644
--- a/src/mem/thread_bridge.cc
+++ b/src/mem/thread_bridge.cc
@@ -64,12 +64,6 @@

 // AtomicResponseProtocol
 Tick
-ThreadBridge::IncomingPort::recvAtomicBackdoor(PacketPtr pkt,
-   MemBackdoorPtr )
-{
-panic("ThreadBridge only supports atomic/functional access.");
-}
-Tick
 ThreadBridge::IncomingPort::recvAtomic(PacketPtr pkt)
 {
 EventQueue::ScopedMigration migrate(device_.eventQueue());
@@ -84,14 +78,6 @@
 device_.out_port_.sendFunctional(pkt);
 }

-void
-ThreadBridge::IncomingPort::recvMemBackdoorReq(const MemBackdoorReq ,
-   MemBackdoorPtr )
-{
-EventQueue::ScopedMigration migrate(device_.eventQueue());
-device_.out_port_.sendMemBackdoorReq(req, backdoor);
-}
-
 ThreadBridge::OutgoingPort::OutgoingPort(const std::string ,
  ThreadBridge )
 : RequestPort(name), device_(device)
diff --git a/src/mem/thread_bridge.hh b/src/mem/thread_bridge.hh
index 92cb078..8a253fd 100644
--- a/src/mem/thread_bridge.hh
+++ b/src/mem/thread_bridge.hh
@@ -55,14 +55,10 @@
 void recvRespRetry() override;

 // AtomicResponseProtocol
-Tick recvAtomicBackdoor(PacketPtr pkt,
-MemBackdoorPtr ) override;
 Tick recvAtomic(PacketPtr pkt) override;

 // FunctionalResponseProtocol
 void recvFunctional(PacketPtr pkt) override;
-void recvMemBackdoorReq(const MemBackdoorReq ,
-MemBackdoorPtr ) override;

   private:
 ThreadBridge _;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia39be0dda4f16917cc3565eb5b012270e6d7697a
Gerrit-Change-Number: 67531
Gerrit-PatchSet: 5
Gerrit-Owner: Earl Ou 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: compiler-checks #511

2023-02-07 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:


--
[...truncated 1.03 KB...]
 > git checkout -f a513e06a1baf762d65d1d8c6dc0297542460e8f6 # timeout=10
Commit message: "fastmodel: Export the reset signals of the GIC."
 > git rev-list --no-walk a513e06a1baf762d65d1d8c6dc0297542460e8f6 # timeout=10
[Checks API] No suitable checks publisher found.
[compiler-checks] $ /bin/sh -xe /tmp/jenkins11270150041483943372.sh
+ ./tests/compiler-tests.sh -j 16
Starting build tests with 'gcc-version-12'...
'gcc-version-12' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'NULL.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-12'...
Done.
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Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-12'...
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Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-12'...
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  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-12'...
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  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-12'...
  ! Failed with exit code 2.
  * Building target 'GCN3_X86.fast' with 'gcc-version-12'...
  ! Failed with exit code 2.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-12'...
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  * Building target 'X86.opt' with 'gcc-version-12'...
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Starting build tests with 'gcc-version-11'...
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-11'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-11'...
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Starting build tests with 'gcc-version-10'...
  * Building target 'RISCV.opt' with 'gcc-version-10'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-10'...
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Starting build tests with 'gcc-version-9'...
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-9'...
Done.
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Starting build tests with 'gcc-version-8'...
  * Building target 'RISCV.opt' with 'gcc-version-8'...
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Starting build tests with 'gcc-version-7'...
  * Building target 'RISCV.opt' with 'gcc-version-7'...
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Starting build tests with 'clang-version-14'...
'clang-version-14' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'clang-version-14'...
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  * Building target 'ARM_MOESI_hammer.opt' with

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the CSR instruction behavior.

2023-02-07 Thread chengyong zhong (Gerrit) via gem5-dev

chengyong zhong has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67717?usp=email )



Change subject: arch-riscv: Fix the CSR instruction behavior.
..

arch-riscv: Fix the CSR instruction behavior.

The RISC-V spec clarifies the CSR instruction operation, some of them
shall not read or write CSR by the hints of RD/RS1/uimm, but the
original version use the 'data != oldData' condition to determine
whether write or not, and always read CSR first.
See CSR instruction in spec:
Section 9.1 Page 56 of  
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf


Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 40 insertions(+), 7 deletions(-)



diff --git a/src/arch/riscv/insts/standard.hh  
b/src/arch/riscv/insts/standard.hh

index 5b0e8c2..afcfd7a 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -91,18 +91,33 @@
   protected:
 uint64_t csr;
 uint64_t uimm;
+bool read;
+bool write;

 /// Constructor
 CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 : RiscvStaticInst(mnem, _machInst, __opClass),
-csr(FUNCT12), uimm(CSRIMM)
+csr(FUNCT12), uimm(CSRIMM), read(true), write(true)
 {
 if (csr == CSR_SATP) {
 flags[IsSquashAfter] = true;
 }
+if (strcmp(mnemonic, "csrrw") == 0 ||
+strcmp(mnemonic, "csrrwi") == 0) {
+  if (RD == 0){
+read = false;
+  }
+} else if (strcmp(mnemonic, "csrrs") == 0 ||
+   strcmp(mnemonic, "csrrc") == 0 ||
+   strcmp(mnemonic, "csrrsi") == 0 ||
+   strcmp(mnemonic, "csrrci") == 0 ){
+  if (RS1 == 0) {
+write = false;
+  }
+}
 }

-std::string generateDisassembly(
+  std::string generateDisassembly(
 Addr pc, const loader::SymbolTable *symtab) const override;
 };

diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index bb500f5..1bd431a 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
 %(op_decl)s;
 %(op_rd)s;

-RegVal data, olddata;
+RegVal data = 0, olddata = 0;
 auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
 if (pm < lowestAllowedMode) {
@@ -380,11 +380,13 @@
 break;
 }

-if (csr == CSR_FCSR) {
+if (read) {
+  if (csr == CSR_FCSR) {
 olddata = xc->readMiscReg(MISCREG_FFLAGS) |
-  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
+  (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+  } else {
 olddata = xc->readMiscReg(midx);
+  }
 }
 olddata = rvZext(olddata);
 auto olddata_all = olddata;
@@ -396,7 +398,7 @@
 %(code)s;

 data &= maskVal;
-if (data != olddata) {
+if (write) {
 if (bits(csr, 11, 10) == 0x3) {
 return std::make_shared(
 csprintf("CSR %s is read-only\n", csrName),  
machInst);


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e7a43cf639474ae76c19a1f430d314b4634ce62
Gerrit-Change-Number: 67717
Gerrit-PatchSet: 1
Gerrit-Owner: chengyong zhong 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: sim: Possible bug found relating simulate function.

2023-02-07 Thread Gerrit

Álvaro Moreno has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67697?usp=email )



Change subject: sim: Possible bug found relating simulate function.
..

sim: Possible bug found relating simulate function.

This commits try to solve an unexpected behaviour
observed related with the RubySystem::MemWriteback
function in RubySystem.cc (lines 241-244).
With te current status of the simulate function
is not possible to validate the assert in
doSimLoop checking that the event queue is not empty.
For solving this problem I tried to reschedule the
event to MaxTick in case of an event being already
in the queue and not num_cycles is specified as
it was done in the previous gem5 version.

Change-Id: I5cd76f1b07040d7e774823d1ec694d9f2eeac89e
---
M src/sim/simulate.cc
1 file changed, 27 insertions(+), 6 deletions(-)



diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 86d516d..b90bb09 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -184,12 +184,9 @@
  * via the 'set_max_tick' function prior. This function is exported to  
Python.

  * @return The SimLoopExitEvent that caused the loop to exit.
  */
-GlobalSimLoopExitEvent *global_exit_event= nullptr;
 GlobalSimLoopExitEvent *
 simulate(Tick num_cycles)
 {
-if (global_exit_event)//cleaning last global exit event
-global_exit_event->clean();
 std::unique_ptr quantum_event;

 inform("Entering event queue @ %d.  Starting simulation...\n",  
curTick());

@@ -198,11 +195,16 @@
 simulatorThreads.reset(new SimulatorThreads(numMainEventQueues));

 if (!simulate_limit_event) {
+
 // If the simulate_limit_event is not set, we set it to MaxTick.
 set_max_tick(MaxTick);
+}else if (num_cycles == -1){
+simulate_limit_event->reschedule(MaxTick);
 }

+
 if (num_cycles != -1) {
+
 // If the user has specified an exit event after X cycles, do so  
here.
 // Note: This will override any prior set max_tick behaviour (such  
as

 // that above when it is set to MAxTick).
@@ -212,6 +214,7 @@
 // This is kept to `set_max_tick` instead of `schedule_tick_exit`  
to
 // preserve backwards functionality. It may be better to deprecate  
this

 // behaviour at some point in favor of `schedule_tick_exit`.
+
 set_max_tick(max_tick);
 }

@@ -236,10 +239,9 @@
 BaseGlobalEvent *global_event = local_event->globalEvent();
 assert(global_event);

-global_exit_event =
+GlobalSimLoopExitEvent *global_exit_event =
 dynamic_cast(global_event);
 assert(global_exit_event);
-
 return global_exit_event;
 }

@@ -306,7 +308,6 @@
 // set the per thread current eventq pointer
 curEventQueue(eventq);
 eventq->handleAsyncInsertions();
-
 while (1) {
 // there should always be at least one event (the SimLoopExitEvent
 // we just scheduled) in the queue

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[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Patch forgotten port after mem port owner deprecation

2023-02-07 Thread Gabriel B. (Gerrit) via gem5-dev

Gabriel B. has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67631?usp=email )


Change subject: dev-amdgpu: Patch forgotten port after mem port owner  
deprecation

..

dev-amdgpu: Patch forgotten port after mem port owner deprecation

Change-Id: I82f88b8962d9f04521e549ca1383c42f2b5b3ffc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67631
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
2 files changed, 18 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/mem/ruby/system/GPUCoalescer.cc  
b/src/mem/ruby/system/GPUCoalescer.cc

index a0808fa..8bde3f7 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -190,7 +190,7 @@
  false, Event::Progress_Event_Pri),
   uncoalescedTable(this),
   deadlockCheckEvent([this]{ wakeup(); }, "GPUCoalescer deadlock  
check"),

-  gmTokenPort(name() + ".gmTokenPort", this)
+  gmTokenPort(name() + ".gmTokenPort")
 {
 m_store_waiting_on_load_cycles = 0;
 m_store_waiting_on_store_cycles = 0;
diff --git a/src/mem/ruby/system/GPUCoalescer.hh  
b/src/mem/ruby/system/GPUCoalescer.hh

index 1120947..dd28855 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -216,9 +216,9 @@
 class GMTokenPort : public TokenResponsePort
 {
   public:
-GMTokenPort(const std::string& name, ClockedObject *owner,
+GMTokenPort(const std::string& name,
 PortID id = InvalidPortID)
-: TokenResponsePort(name, owner, id)
+: TokenResponsePort(name, id)
 { }
 ~GMTokenPort() { }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82f88b8962d9f04521e549ca1383c42f2b5b3ffc
Gerrit-Change-Number: 67631
Gerrit-PatchSet: 2
Gerrit-Owner: Gabriel B. 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabriel B. 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix incorrect trap value of instruction fault

2023-02-07 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67677?usp=email )



Change subject: arch-riscv: Fix incorrect trap value of instruction fault
..

arch-riscv: Fix incorrect trap value of instruction fault

As we add rv_type bit in machInst at 62, It will get the machine
code with rv_type specification if we just return machInst. We
only need return machine code for handling instruction fault.

Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
---
M src/arch/riscv/faults.hh
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index e664767..f687fd6 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -173,7 +173,7 @@
 : RiscvFault(n, FaultType::OTHERS, INST_ILLEGAL), _inst(inst)
 {}

-RegVal trap_value() const override { return _inst; }
+RegVal trap_value() const override { return bits(_inst, 31, 0); }
 };

 class UnknownInstFault : public InstFault

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Gerrit-Change-Number: 67677
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: nightly #513

2023-02-07 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:


--
[...truncated 1.08 MB...]
 [ TRACING]  -> VEGA_X86/debug/Ruby.hh
 [ CXX] VEGA_X86/debug/RubyResourceStalls.cc -> .o
 [ CXX] VEGA_X86/debug/RubyHitMiss.cc -> .o
 [ CXX] VEGA_X86/debug/Ruby.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/BoolVec.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/Consumer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/DataBlock.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/Histogram.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/IntVec.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/NetDest.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/SubBlock.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/common/WriteMask.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/GPUCoalescer.py.cc -> .o
 [SO Param] m5.objects.GPUCoalescer, RubyGPUCoalescer -> 
VEGA_X86/python/_m5/param_RubyGPUCoalescer.cc
 [ CXX] VEGA_X86/mem/ruby/system/RubySystem.py.cc -> .o
 [SO Param] m5.objects.RubySystem, RubySystem -> 
VEGA_X86/python/_m5/param_RubySystem.cc
 [ CXX] VEGA_X86/mem/ruby/system/Sequencer.py.cc -> .o
 [SO Param] m5.objects.GPUCoalescer, RubyGPUCoalescer -> 
VEGA_X86/params/RubyGPUCoalescer.hh
 [ CXX] VEGA_X86/python/_m5/param_RubySystem.cc -> .o
 [MAKE INC] VEGA_X86/mem/ruby/slicc_interface/Message.hh -> protocol/Message.hh
 [SO Param] m5.objects.RubyCache, RubyCache -> VEGA_X86/params/RubyCache.hh
 [MAKE INC] VEGA_X86/mem/ruby/slicc_interface/RubyRequest.hh -> 
protocol/RubyRequest.hh
 [SO Param] m5.objects.Sequencer, RubySequencer -> 
VEGA_X86/params/RubySequencer.hh
 [SO Param] m5.objects.DirectoryMemory, RubyDirectoryMemory -> 
VEGA_X86/params/RubyDirectoryMemory.hh
 [SO Param] m5.objects.Sequencer, RubyPort -> 
VEGA_X86/python/_m5/param_RubyPort.cc
 [SO Param] m5.objects.Sequencer, RubyPortProxy -> 
VEGA_X86/python/_m5/param_RubyPortProxy.cc
 [SO Param] m5.objects.Sequencer, RubySequencer -> 
VEGA_X86/python/_m5/param_RubySequencer.cc
 [SO Param] m5.objects.Sequencer, RubyHTMSequencer -> 
VEGA_X86/python/_m5/param_RubyHTMSequencer.cc
 [SO Param] m5.objects.Sequencer, DMASequencer -> 
VEGA_X86/python/_m5/param_DMASequencer.cc
 [ CXX] VEGA_X86/mem/ruby/system/VIPERCoalescer.py.cc -> .o
 [SO Param] m5.objects.VIPERCoalescer, VIPERCoalescer -> 
VEGA_X86/python/_m5/param_VIPERCoalescer.cc
 [ CXX] VEGA_X86/python/_m5/param_RubyGPUCoalescer.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyPort.cc -> .o
 [SO Param] m5.objects.Sequencer, RubyPortProxy -> 
VEGA_X86/params/RubyPortProxy.hh
 [ CXX] VEGA_X86/python/_m5/param_RubySequencer.cc -> .o
 [SO Param] m5.objects.Sequencer, RubyHTMSequencer -> 
VEGA_X86/params/RubyHTMSequencer.hh
 [SO Param] m5.objects.Sequencer, DMASequencer -> 
VEGA_X86/params/DMASequencer.hh
 [SO Param] m5.objects.VIPERCoalescer, VIPERCoalescer -> 
VEGA_X86/params/VIPERCoalescer.hh
 [ CXX] VEGA_X86/mem/ruby/system/CacheRecorder.cc -> .o
 [MAKE INC] VEGA_X86/mem/ruby/common/DataBlock.hh -> protocol/DataBlock.hh
 [MAKE INC] VEGA_X86/mem/ruby/common/WriteMask.hh -> protocol/WriteMask.hh
 [ CXX] VEGA_X86/mem/ruby/system/GPUCoalescer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/RubyPort.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyPortProxy.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/HTMSequencer.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_DMASequencer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/DMASequencer.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyHTMSequencer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/RubyPortProxy.cc -> .o
 [SO Param] m5.objects.Network, RubyNetwork -> VEGA_X86/params/RubyNetwork.hh
 [ CXX] VEGA_X86/python/_m5/param_VIPERCoalescer.cc -> .o
 [SO Param] m5.objects.BasicLink, BasicExtLink -> 
VEGA_X86/params/BasicExtLink.hh
 [SO Param] m5.objects.BasicLink, BasicIntLink -> 
VEGA_X86/params/BasicIntLink.hh
 [SO Param] m5.objects.BasicLink, BasicLink -> VEGA_X86/params/BasicLink.hh
 [SO Param] m5.objects.BasicRouter, BasicRouter -> 
VEGA_X86/params/BasicRouter.hh
 [ CXX] VEGA_X86/mem/ruby/system/Sequencer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/VIPERCoalescer.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/structures/RubyCache.py.cc -> .o
 [SO Param] m5.objects.RubyCache, RubyCache -> 
VEGA_X86/python/_m5/param_RubyCache.cc
 [ CXX] VEGA_X86/mem/ruby/structures/DirectoryMemory.py.cc -> .o
 [SO Param] m5.objects.DirectoryMemory, RubyDirectoryMemory -> 
VEGA_X86/python/_m5/param_RubyDirectoryMemory.cc
 [ CXX] VEGA_X86/mem/ruby/structures/RubyPrefetcher.py.cc -> .o
 [ CXX] VEGA_X86/mem/ruby/system/RubySystem.cc -> .o
 [SO Param] m5.objects.RubyPrefetcher, RubyPrefetcher -> 
VEGA_X86/python/_m5/param_RubyPrefetcher.cc
 [ CXX] VEGA_X86/python/_m5/param_RubyCache.cc -> .o
 [ CXX] VEGA_X86/python/_m5/param_RubyDirectoryMemory.cc -> .o
 [SO Param] m5.objects.RubyPrefetcher, RubyPrefetcher -> 
VEGA_X86/params/RubyPrefetcher.hh
 [ CXX] VEGA_X86/mem/ruby/structures/WireBuffer.py.cc ->

[gem5-dev] [S] Change in gem5/gem5[develop]: sim: handle async events in main thread only

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: use default backdoor behavior for thread_bridge

[gem5-dev] Build failed in Jenkins: compiler-checks #511

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix the CSR instruction behavior.

[gem5-dev] [S] Change in gem5/gem5[develop]: sim: Possible bug found relating simulate function.

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Patch forgotten port after mem port owner deprecation

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: Fix incorrect trap value of instruction fault

[gem5-dev] Build failed in Jenkins: nightly #513

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