[gem5-dev] [XS] Change in gem5/gem5[develop]: base: Fix VNC initilization

2023-04-12 Thread Yen-lin Lai (Gerrit) via gem5-dev 
Yen-lin Lai has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69757?usp=email )



Change subject: base: Fix VNC initilization
..

base: Fix VNC initilization

In a previous commit, the initialization of dataFd to -1 is removed.
Add it back so VNC server can properly accept connection.

Fixes: 52775185b2 ("base,cpu,dev,sim: Pull common logic into  
ListenSocket::listen().")

Change-Id: I4246d1fddc766cb190a04d4f984fc1ce73af3fb0
---
M src/base/vnc/vncserver.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc
index f342419..4b1ddae 100644
--- a/src/base/vnc/vncserver.cc
+++ b/src/base/vnc/vncserver.cc
@@ -117,7 +117,7 @@
  */
 VncServer::VncServer(const Params &p)
 : VncInput(p), listenEvent(NULL), dataEvent(NULL), number(p.number),
-  listener(p.port.build(p.name)),
+  dataFd(-1), listener(p.port.build(p.name)),
   sendUpdate(false), supportsRawEnc(false), supportsResizeEnc(false)
 {
 if (p.port)

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4246d1fddc766cb190a04d4f984fc1ce73af3fb0
Gerrit-Change-Number: 69757
Gerrit-PatchSet: 1
Gerrit-Owner: Yen-lin Lai 
Gerrit-MessageType: newchange
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Insert symbol table of bootloader into debug symbol table...

2023-04-12 Thread Roger Chang (Gerrit) via gem5-dev 
Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69697?usp=email )


Change subject: arch-riscv: Insert symbol table of bootloader into debug  
symbol table in bare metal workload

..

arch-riscv: Insert symbol table of bootloader into debug symbol table
in bare metal workload

Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69697
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Yu-hsin Wang 
---
M src/arch/riscv/bare_metal/fs_workload.cc
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Yu-hsin Wang: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/riscv/bare_metal/fs_workload.cc  
b/src/arch/riscv/bare_metal/fs_workload.cc

index 4f7adb3..574c944 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -47,6 +47,8 @@
 fatal_if(!bootloader, "Could not load bootloader file %s.",  
p.bootloader);

 _resetVect = bootloader->entryPoint();
 bootloaderSymtab = bootloader->symtab();
+
+loader::debugSymbolTable.insert(bootloaderSymtab);
 }

 BareMetal::~BareMetal()

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
Gerrit-Change-Number: 69697
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #573

2023-04-12 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[gabe.black] mem: Use HostSocket in the SharedMemoryServer.

[rogerycchang] arch-riscv: Fix the address check of pmp

[rogerycchang] arch-riscv: Refactor the shouldCheckPMP function

[gabe.black] base,python: Add a param type for host sockets.

[gabe.black] base: Remove the now unused UnixSocketAddr class and associated 
code.

[gabe.black] arch,base,dev,sim: Convert objects to use the HostSocket param 
type.


--
[...truncated 4.44 MB...]
 [SO Param] m5.objects.QemuFwCfg, QemuFwCfgMmio -> 
RISCV/python/_m5/param_QemuFwCfgMmio.cc
 [ TRACING]  -> RISCV/debug/QemuFwCfg.hh
 [ TRACING]  -> RISCV/debug/QemuFwCfgVerbose.hh
 [ TRACING]  -> RISCV/debug/QemuFwCfg.cc
 [ TRACING]  -> RISCV/debug/QemuFwCfgVerbose.cc
 [   SHCXX] RISCV/dev/serial/Serial.py.cc -> .os
 [   SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os
 [   SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os
 [SO Param] m5.objects.Serial, SerialDevice -> 
RISCV/python/_m5/param_SerialDevice.cc
 [   SHCXX] RISCV/debug/QemuFwCfg.cc -> .os
 [   SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os
 [SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh
 [SO Param] m5.objects.Serial, SerialNullDevice -> 
RISCV/python/_m5/param_SerialNullDevice.cc
 [   SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os
 [   SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os
 [SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc
 [ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc
 [   SHCXX] RISCV/dev/serial/Uart.py.cc -> .os
 [SO Param] m5.objects.Serial, SerialNullDevice -> 
RISCV/params/SerialNullDevice.hh
 [ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh
 [SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh
 [   SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os
 [   SHCXX] RISCV/enums/TerminalDump.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os
 [SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc
 [SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh
 [   SHCXX] RISCV/python/_m5/param_Uart.cc -> .os
 [SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc
 [SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh
 [   SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os
 [SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc
 [SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh
 [   SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os
 [   SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os
 [   SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os
 [ TRACING]  -> RISCV/debug/Terminal.hh
 [ TRACING]  -> RISCV/debug/TerminalVerbose.hh
 [   SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os
 [   SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os
 [ TRACING]  -> RISCV/debug/Uart.hh
 [   SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os
 [ TRACING]  -> RISCV/debug/Terminal.cc
 [ TRACING]  -> RISCV/debug/TerminalVerbose.cc
 [   SHCXX] RISCV/debug/Terminal.cc -> .os
 [   SHCXX] RISCV/debug/TerminalVerbose.cc -> .os
 [ TRACING]  -> RISCV/debug/Uart.cc
 [   SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os
 [   SHCXX] RISCV/debug/Uart.cc -> .os
 [SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc
 [SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc
 [SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh
 [SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh
 [   SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os
 [SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc
 [SO Param] m5.objects.PciDevice, PciBarNone -> 
RISCV/python/_m5/param_PciBarNone.cc
 [SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc
 [   SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os
 [   SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os
 [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> 
RISCV/python/_m5/param_PciLegacyIoBar.cc
 [   SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os
 [SO Param] m5.objects.PciDevice, PciMemBar -> 
RISCV/python/_m5/param_PciMemBar.cc
 [SO Param] m5.objects.PciDevice, PciMemUpperBar -> 
RISCV/python/_m5/param_PciMemUpperBar.cc
 [   SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os
 [SO Param] m5.objects.PciDevice, PciDevice -> 
RISCV/python/_m5/param_PciDevice.cc
 [ TRACING]  -> RISCV/debug/PciDevice.hh
 [ TRACING]  -> RISCV/debug/PciDevice.cc
 [   SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os
 [   SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os
 [   SHCXX] RISCV/de

[gem5-dev] Re: Build failed in Jenkins: nightly #571

2023-04-12 Thread Bobby Bruce via gem5-dev 
The following patch should fix this nightly bug: 
https://gem5-review.googlesource.com/c/public/gem5/+/69717

There was a small bug introduced where header files were not being added to the 
“build” directory. This broke the SST compilation as it uses the “build” 
directory as a include path.

In addition, this patch will also fix the SST Makefile to not use the headers 
in the “build” directory. I think this is bad practice:
https://gem5-review.googlesource.com/c/public/gem5/+/69718

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616
 
web: https://www.bobbybruce.net

> On Apr 10, 2023, at 3:34 PM, jenkins-no-reply--- via gem5-dev 
>  wrote:
> 
> See 
> 
> Changes:
> 
> [gabe.black] base: Add support for unix domain sockets in ListenSocket.
> 
> 
> --
> [...truncated 4.44 MB...]
> [SO Param] m5.objects.QemuFwCfg, QemuFwCfgMmio -> 
> RISCV/python/_m5/param_QemuFwCfgMmio.cc
> [   SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os
> [ TRACING]  -> RISCV/debug/QemuFwCfg.hh
> [ TRACING]  -> RISCV/debug/QemuFwCfgVerbose.hh
> [ TRACING]  -> RISCV/debug/QemuFwCfg.cc
> [   SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os
> [ TRACING]  -> RISCV/debug/QemuFwCfgVerbose.cc
> [   SHCXX] RISCV/debug/QemuFwCfg.cc -> .os
> [   SHCXX] RISCV/dev/serial/Serial.py.cc -> .os
> [   SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os
> [SO Param] m5.objects.Serial, SerialDevice -> 
> RISCV/python/_m5/param_SerialDevice.cc
> [SO Param] m5.objects.Serial, SerialNullDevice -> 
> RISCV/python/_m5/param_SerialNullDevice.cc
> [SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh
> [SO Param] m5.objects.Serial, SerialNullDevice -> 
> RISCV/params/SerialNullDevice.hh
> [   SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os
> [SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc
> [ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc
> [   SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os
> [   SHCXX] RISCV/dev/serial/Uart.py.cc -> .os
> [   SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os
> [ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh
> [SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh
> [   SHCXX] RISCV/enums/TerminalDump.cc -> .os
> [   SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os
> [SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc
> [SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh
> [   SHCXX] RISCV/python/_m5/param_Uart.cc -> .os
> [SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc
> [SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh
> [   SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os
> [SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc
> [SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh
> [   SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os
> [   SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os
> [   SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os
> [ TRACING]  -> RISCV/debug/Terminal.hh
> [ TRACING]  -> RISCV/debug/TerminalVerbose.hh
> [   SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os
> [   SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os
> [ TRACING]  -> RISCV/debug/Uart.hh
> [ TRACING]  -> RISCV/debug/Terminal.cc
> [   SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os
> [   SHCXX] RISCV/debug/Terminal.cc -> .os
> [ TRACING]  -> RISCV/debug/TerminalVerbose.cc
> [   SHCXX] RISCV/debug/TerminalVerbose.cc -> .os
> [ TRACING]  -> RISCV/debug/Uart.cc
> [   SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os
> [   SHCXX] RISCV/debug/Uart.cc -> .os
> [SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc
> [SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc
> [SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh
> [SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh
> [   SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os
> [SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc
> [SO Param] m5.objects.PciDevice, PciBarNone -> 
> RISCV/python/_m5/param_PciBarNone.cc
> [   SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os
> [   SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os
> [   SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os
> [   SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os
> [   SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os
> [SO Param] m5.objects.PciDevice, PciIoBar -> 
> RISCV/python/_m5/param_PciIoBar.cc
> [   SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os
> [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> 
> RISCV/python/_m5/param_PciLegacyIoBar.cc
> [   SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os
> [SO Param] m5.objects.PciDevice, PciMemBar -> 
> RISCV/python/_m5/param_PciMemBar.cc
> [SO Param] m5.object

[gem5-dev] [XS] Change in gem5/gem5[develop]: ext: Update SST Makefile to use "src" for gem5 includes

2023-04-12 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69718?usp=email )



Change subject: ext: Update SST Makefile to use "src" for gem5 includes
..

ext: Update SST Makefile to use "src" for gem5 includes

Using the include files from the "build" directory can result in a
complication failure if gem5 is compiled with "no-duplicate-sources" as
header files are not copied to "build".

To fix this, this Makefile now includes headers from the "src"
directory.

Change-Id: Ia01c2c97944b7538e3e944aa288099dee40820ff
---
M ext/sst/Makefile
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/ext/sst/Makefile b/ext/sst/Makefile
index 9213d26..42d3be5 100644
--- a/ext/sst/Makefile
+++ b/ext/sst/Makefile
@@ -4,7 +4,7 @@
 OFLAG=3

 LDFLAGS=-shared -fno-common ${shell pkg-config ${SST_VERSION} --libs}  
-L../../build/${ARCH}/ -Wl,-rpath ../../build/${ARCH}
-CXXFLAGS=-std=c++17 -g -O${OFLAG} -fPIC ${shell pkg-config ${SST_VERSION}  
--cflags} ${shell python3-config --includes} -I../../build/${ARCH}/  
-I../../ext/pybind11/include/ -I../../build/softfloat/ -I../../ext
+CXXFLAGS=-std=c++17 -g -O${OFLAG} -fPIC ${shell pkg-config ${SST_VERSION}  
--cflags} ${shell python3-config --includes} -I../../src/  
-I../../ext/pybind11/include/ -I../../ext/softfloat/ -I../../ext

 CPPFLAGS+=-MMD -MP
 SRC=$(wildcard *.cc)


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia01c2c97944b7538e3e944aa288099dee40820ff
Gerrit-Change-Number: 69718
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Fix "no-duplicate-sources" to include .hh when not set

2023-04-12 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69717?usp=email )



Change subject: scons: Fix "no-duplicate-sources" to include .hh when not  
set

..

scons: Fix "no-duplicate-sources" to include .hh when not set

A flag, introduced in this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/68518
allowed users to pass "no-duplicate-sources" to a gem5 compilation to
not simlink sources in the build directory.

In this patch "src" was added as a shared top-level header directory.
This means that the header files are not copied to the "build" directory
whether or not "no-duplicate-sources" is set.

This patch ensures the "src" directory is only added as a shared
top-level headers directory in the case where "no-duplicate-sources" is
set.

In addition, the "duplicate_sources" parameter (the destination for the
"no-duplicate-sources" was "None" by default, and only set to False when
the flag was used. `default=True` has been added so "duplicate_sources"
can be used as a boolean.

This bug was a cause of a Nightly build error:
https://jenkins.gem5.org/job/nightly/570

In this error, building ext/sst resulted in an error as the Makefile
depends on adding "build/RISCV" to the include path. Without the header
files in the "build" directory, building SST failed. Though, ext/stt
should probably not be using header files in the "build/RISCV"
directory. This will be fixed in another change.

Change-Id: I786486a177fe17a67f3b939c539eecdcbfcaeaf2
---
M SConstruct
1 file changed, 3 insertions(+), 2 deletions(-)



diff --git a/SConstruct b/SConstruct
index e91e700..7e8f177 100755
--- a/SConstruct
+++ b/SConstruct
@@ -145,7 +145,7 @@
   help='Enable support for the gprof profiler')
 AddOption('--pprof', action='store_true',
   help='Enable support for the pprof profiler')
-AddOption('--no-duplicate-sources', action='store_false',
+AddOption('--no-duplicate-sources', action='store_false', default=True,
   dest='duplicate_sources',
   help='Do not create symlinks to sources in the build directory')

@@ -267,7 +267,8 @@

 # Add shared top-level headers
 main.Prepend(CPPPATH=Dir('include'))
-main.Prepend(CPPPATH=Dir('src'))
+if not GetOption('duplicate_sources'):
+main.Prepend(CPPPATH=Dir('src'))


 

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I786486a177fe17a67f3b939c539eecdcbfcaeaf2
Gerrit-Change-Number: 69717
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: compiler-checks #573

2023-04-12 Thread jenkins-no-reply--- via gem5-dev 
See 


Changes:

[gabe.black] mem: Use HostSocket in the SharedMemoryServer.

[rogerycchang] arch-riscv: Fix the address check of pmp

[rogerycchang] arch-riscv: Refactor the shouldCheckPMP function

[gabe.black] base,python: Add a param type for host sockets.

[gabe.black] base: Remove the now unused UnixSocketAddr class and associated 
code.

[gabe.black] arch,base,dev,sim: Convert objects to use the HostSocket param 
type.


--
[...truncated 1.03 KB...]
 > git checkout -f 716c154b51a24c7af0ad2334c9337d9fc7f8a5c0 # timeout=10
Commit message: "arch,base,dev,sim: Convert objects to use the HostSocket param 
type."
 > git rev-list --no-walk e79d6616ddb97f0ca37fd5095f1cbe44fe9759c9 # timeout=10
[Checks API] No suitable checks publisher found.
[compiler-checks] $ /bin/sh -xe /tmp/jenkins5135098657923954423.sh
+ ./tests/compiler-tests.sh -j 16
Starting build tests with 'gcc-version-12'...
'gcc-version-12' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-12'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-12'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'ALL.opt' with 'gcc-version-12'...
Done.
  * Building target 'ALL.fast' with 'gcc-version-12'...
Done.
Starting build tests with 'gcc-version-11'...
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-11'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'MIPS.opt' with 'gcc-version-9'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-8'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-8'...
Done.
Starting build tests with 'gcc-version-7'...
  * Building target 'ALL.opt' with 'gcc-version-7'...
  ! Failed with exit code 2.
  * Building target 'ALL.fast' with 'gcc-version-7'...
  ! Failed with exit code 2.
Starting build tests with 'clang-version-14'...
'clang-ve

[gem5-dev] Re: how to use gfx900 in gpu-fs

2023-04-12 Thread Sinclair, Matthew via gem5-dev 
[AMD Official Use Only - General]

Hi Xiang,

What is the concern with the Vega 10?  Is it failing when you run the gfx900 
code?

Setting that aside, Matt P (CC'd) will have to confirm for GPUFS but I believe 
if you specify -gfx-version=gfx900 on the command for both GPUSE and GPUFS it 
should run gfx900 code.

Thanks,
Matt S.

From: Xiang Li via gem5-dev 
Sent: Wednesday, April 12, 2023 1:54 AM
To: gem5-dev@gem5.org
Cc: Xiang Li 
Subject: [gem5-dev] how to use gfx900 in gpu-fs

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.

Hi, I'm trying to run gpu-fs. I saw a file in gem5-resouces, which said`docker 
run --rm -v ${PWD}:${PWD} -w ${PWD} gcr.io/gem5-test/gpu-fs:latest bash -c 
'make clean; HCC_AMDGPU_TARGET=gfx900 make'`
but when I try to run the square, it saids it's using vega 10 XTX. How can I 
use the gfx900 to run my own application? Thanks a lot.
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[gem5-dev] [S] Change in gem5/gem5[develop]: base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

2023-04-12 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69677?usp=email )


Change subject: base: fatal() if a socket path doesn't fit in  
sockaddr_un.sun_path.

..

base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

Normally this would just generate a warning, but a warning is easy to
miss, and truncating the path to fit would be surprising. Since the max
length isn't likely to change, a path which has to be truncated is
essentially fundementally wrong, and could be defined as something
else which is short enough before being used in the config.

Note that this only applies to either the abstract path which is just
a string, or the file name and not the directory path on a file based
socket.

Change-Id: I8702cf02c03053b5d0b6133f25b0e588de666f15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69677
Maintainer: Gabe Black 
Reviewed-by: Earl Ou 
Tested-by: kokoro 
---
M src/base/socket.cc
M src/base/socket.hh
2 files changed, 10 insertions(+), 13 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass
  Earl Ou: Looks good to me, approved




diff --git a/src/base/socket.cc b/src/base/socket.cc
index 76dc73f..62f2071 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -261,15 +261,12 @@
 });
 }

-std::string
-ListenSocketUnix::truncate(const std::string &original, size_t max_len)
+void
+ListenSocketUnix::checkPathLength(const std::string &original, size_t  
max_len)

 {
-if (original.size() <= max_len)
-return original;
-
-std::string truncated = original.substr(0, max_len);
-warn("%s: Truncated \"%s\" to \"%s\"", name(), original, truncated);
-return truncated;
+fatal_if(original.size() > max_len,
+"Length of socket path '%s' is %d, greater than max %d.",
+original, original.size(), max_len);
 }

 void
@@ -303,9 +300,9 @@

 ListenSocketUnixFile::ListenSocketUnixFile(const std::string &_name,
 const std::string &_dir, const std::string &_fname) :
-ListenSocketUnix(_name), dir(_dir),
-fname(truncate(_fname, sizeof(sockaddr_un::sun_path) - 1))
+ListenSocketUnix(_name), dir(_dir), fname(_fname)
 {
+checkPathLength(fname, sizeof(sockaddr_un::sun_path) - 1);
 }

 ListenSocketUnixFile::~ListenSocketUnixFile()
@@ -385,9 +382,9 @@

 ListenSocketUnixAbstract::ListenSocketUnixAbstract(
 const std::string &_name, const std::string &_path) :
-ListenSocketUnix(_name),
-path(truncate(_path, sizeof(sockaddr_un::sun_path) - 1))
+ListenSocketUnix(_name), path(_path)
 {
+checkPathLength(path, sizeof(sockaddr_un::sun_path) - 1);
 }

 void
diff --git a/src/base/socket.hh b/src/base/socket.hh
index b8828e7..bc17213 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -162,7 +162,7 @@
   protected:
 virtual size_t prepSockaddrUn(sockaddr_un &addr) const = 0;

-std::string truncate(const std::string &original, size_t max_len);
+void checkPathLength(const std::string &original, size_t max_len);

 ListenSocketUnix(const std::string &_name) : ListenSocket(_name) {}


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8702cf02c03053b5d0b6133f25b0e588de666f15
Gerrit-Change-Number: 69677
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Chia-You Chen 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jesse Pai 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Insert symbol table of into debug symbol table

2023-04-12 Thread Roger Chang (Gerrit) via gem5-dev 
Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69697?usp=email )



Change subject: arch-riscv: Insert symbol table of into debug symbol table
..

arch-riscv: Insert symbol table of into debug symbol table

Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
---
M src/arch/riscv/bare_metal/fs_workload.cc
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/bare_metal/fs_workload.cc  
b/src/arch/riscv/bare_metal/fs_workload.cc

index 4f7adb3..574c944 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -47,6 +47,8 @@
 fatal_if(!bootloader, "Could not load bootloader file %s.",  
p.bootloader);

 _resetVect = bootloader->entryPoint();
 bootloaderSymtab = bootloader->symtab();
+
+loader::debugSymbolTable.insert(bootloaderSymtab);
 }

 BareMetal::~BareMetal()

--
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Gerrit-Change-Id: Iea2ded4e72070b7b3b588000e1082180269e9e5e
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[gem5-dev] [XS] Change in gem5/gem5[develop]: cpu: Fix assignment to lastActivate in SimpleThread::suspend()

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69689?usp=email )



Change subject: cpu: Fix assignment to lastActivate in  
SimpleThread::suspend()

..

cpu: Fix assignment to lastActivate in SimpleThread::suspend()

Remove the assignment to lastActivate in SimpleThread::suspend();
This appears to be a copy-and-paste error that escaped notice.

Change-Id: I44461b38b0f09d309d821531409b460216e07131
---
M src/cpu/simple_thread.cc
1 file changed, 1 insertion(+), 2 deletions(-)



diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index c28359a..655d989 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, 2020 ARM Limited
+ * Copyright (c) 2018, 2020, 2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -146,7 +146,6 @@
 if (status() == ThreadContext::Suspended)
 return;

-lastActivate = curTick();
 lastSuspend = curTick();
 _status = ThreadContext::Suspended;
 baseCpu->suspendContext(_threadId);

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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Add --exit-on-uart-eot flag to Arm baremetal.py config

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69688?usp=email )



Change subject: configs: Add --exit-on-uart-eot flag to Arm baremetal.py  
config

..

configs: Add --exit-on-uart-eot flag to Arm baremetal.py config

Many benchmarks signal their termination by writing an EOT character
to the UART. This change adds an option to the Arm `baremetal.py`
example script to exit the simulation when an EOT character is
detected on any of the UARTs.

Change-Id: Ibfce9800c47090714258dbdbc5d6cee5ee6fb952
---
M configs/example/arm/baremetal.py
1 file changed, 11 insertions(+), 1 deletion(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index ab24fd3..c52afcc 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017,2019-2022 Arm Limited
+# Copyright (c) 2016-2017,2019-2023 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -157,6 +157,10 @@
 workload_class = workloads.workload_list.get(args.workload)
 system.workload = workload_class(object_file, system)

+if args.exit_on_uart_eot:
+for uart in system.realview.uart:
+uart.end_on_eot = True
+
 return system


@@ -254,6 +258,12 @@
 help="Destination for the Tarmac trace output. [Default:  
stdoutput]",

 )
 parser.add_argument(
+"--exit-on-uart-eot",
+action="store_true",
+help="Exit simulation if any of the UARTs receive an EOT. Many "
+ "workloads signal termination by sending an EOT character."
+)
+parser.add_argument(
 "--dtb-gen",
 action="store_true",
 help="Doesn't run simulation, it generates a DTB only",

--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69682?usp=email )



Change subject: dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn
..

dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn

Writes to the GICD_IGROUPRn registers are currently applied using the
`|=` operator, allowing bits to be set but not cleared. According to
the specification [1] this register should allow direct writes.

This patch changes the logic to write the new value directly to the
register.

[1] https://developer.arm.com/documentation/ihi0048/latest/

Change-Id: Ia5f17d05530263d7e918ff33576daaf8165c25c2
---
M src/dev/arm/gic_v2.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 6def222..e0e92ac 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -509,7 +509,7 @@
 DPRINTF(GIC,
 "gic distributor write GICD_IGROUPR%d (%#x) size %#x value %#x  
\n",

 ix, daddr, data_sz, data);
-getIntGroup(ctx, ix) |= data;
+getIntGroup(ctx, ix) = data;
 return;
 }


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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix formatting of v8 Tarmac Register records

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69680?usp=email )



Change subject: arch-arm: Fix formatting of v8 Tarmac Register records
..

arch-arm: Fix formatting of v8 Tarmac Register records

The Tarmac v8 Register ("R") record serialisation formats the
underlying 64-bit storage using a format string field width specifier.
This sets a minimum number of hex characters for the value, rather
than a maximum number of characters.

Because of this, when formatting a narrowed view of a larger
register (e.g. the 32-bit w0 view of the 64-bit x0 register), if any
of the upper bits in the underlying storage are set, then the number
of hex characters used will be the minimum number required to
represent the full value. This could result in irregular formatting,
for example an odd number of hex characters.

This irregular formatting can cause parsing warnings or failures in
some Tarmac tools, for example the Arm Tarmac Trace Utilities [1].

This patch modifies the "R" record formatting to first mask off the
upper bits of the value in the underlying storage to ensure that the
correct number of hex characters are used for the size of the register
being serialised.

[1] https://github.com/ARM-software/tarmac-trace-utilities

Change-Id: Idbd80553d3bcdb56fa9e48440ab7d4dff073
---
M src/arch/arm/tracers/tarmac_record_v8.cc
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc  
b/src/arch/arm/tracers/tarmac_record_v8.cc

index 29606c3..a3850b3 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019 ARM Limited
+ * Copyright (c) 2017-2019, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -293,8 +293,9 @@
 TarmacTracerRecordV8::TraceRegEntryV8::formatReg() const
 {
 if (regWidth <= 64) {
-// Register width is < 64 bit (scalar register).
-return csprintf("%0*x", regWidth / 4, values[Lo]);
+// Register width is <= 64 bit (scalar register).
+const auto regValue = values[Lo] & mask(regWidth);
+return csprintf("%0*x", regWidth / 4, regValue);
 } else {

 // Register width is > 64 bit (vector).  Iterate over every vector

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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add more detailed debug messages to GICv2.

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69681?usp=email )



Change subject: arch-arm: Add more detailed debug messages to GICv2.
..

arch-arm: Add more detailed debug messages to GICv2.

Converted the generic DPRINTF messages for the GICv2 register reads
and writes (showing only the memory mapped address) to finer grained
DPRINTF messages showing the names of the mapped registers being
accessed.

This change is intended to make it easier to debug the GIC setup from
the gem5 debug trace.

Change-Id: Ic418b2ea8438fed6a5a810ebc0b686cd4c891cb0
---
M src/dev/arm/gic_v2.cc
1 file changed, 76 insertions(+), 9 deletions(-)



diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 7dc001e..6def222 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -199,8 +199,6 @@
 const Addr daddr = pkt->getAddr() - distRange.start();
 const ContextID ctx = pkt->req->contextId();

-DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
-
 const uint32_t resp = readDistributor(ctx, daddr, pkt->getSize());

 switch (pkt->getSize()) {
@@ -228,42 +226,53 @@
 if (GICD_IGROUPR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_IGROUPR%d (%#x)\n", ix,  
daddr);

 return getIntGroup(ctx, ix);
 }

 if (GICD_ISENABLER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ISENABLER%d (%#x)\n",
+ix, daddr);
 return getIntEnabled(ctx, ix);
 }

 if (GICD_ICENABLER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ICENABLER%d (%#x)\n",
+ix, daddr);
 return getIntEnabled(ctx, ix);
 }

 if (GICD_ISPENDR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ISPENDR%d (%#x)\n", ix,  
daddr);

 return getPendingInt(ctx, ix);
 }

 if (GICD_ICPENDR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ICPENDR%d (%#x)\n", ix,  
daddr);

 return getPendingInt(ctx, ix);
 }

 if (GICD_ISACTIVER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ISACTIVER%d (%#x)\n",
+ix, daddr);
 return getActiveInt(ctx, ix);
 }

 if (GICD_ICACTIVER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ICACTIVER%d (%#x)\n",
+ix, daddr);
 return getActiveInt(ctx, ix);
 }

@@ -310,30 +319,38 @@

 if (GICD_ICFGR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
+DPRINTF(GIC, "gic distributor read GICD_ICFGR%d (%#x)\n", ix,  
daddr);

 return getIntConfig(ctx, ix);
 }

 switch(daddr) {
   case GICD_CTLR:
+DPRINTF(GIC, "gic distributor read GICD_CTLR (%#x)\n", daddr);
 return enabled;
   case GICD_TYPER:
 /* The 0x100 is a made-up flag to show that gem5 extensions
  * are available,
  * write 0x200 to this register to enable it.  */
+DPRINTF(GIC, "gic distributor read GICD_TYPER (%#x)\n", daddr);
 return (((sys->threads.numRunning() - 1) << 5) |
 (itLines/INT_BITS_MAX -1) |
 (haveGem5Extensions ? 0x100 : 0x0));
   case GICD_PIDR0:
 //ARM defined DevID
+DPRINTF(GIC, "gic distributor read GICD_PIDR0 (%#x)\n", daddr);
 return (gicdPIDR & 0xFF);
   case GICD_PIDR1:
+DPRINTF(GIC, "gic distributor read GICD_PIDR1 (%#x)\n", daddr);
 return ((gicdPIDR >> 8) & 0xFF);
   case GICD_PIDR2:
+DPRINTF(GIC, "gic distributor read GICD_PIDR2 (%#x)\n", daddr);
 return ((gicdPIDR >> 16) & 0xFF);
   case GICD_PIDR3:
+DPRINTF(GIC, "gic distributor read GICD_PIDR3 (%#x)\n", daddr);
 return ((gicdPIDR >> 24) & 0xFF);
   case GICD_IIDR:
  /* revision id is resorted to 1 and variant to 0*/
+DPRINTF(GIC, "gic distributor read GICD_IIDR (%#x)\n", daddr);
 return gicdIIDR;
   default:
 panic("Tried to read Gic distributor at offset %#x\n", daddr);
@@ -350,8 +367,6 @@
 const ContextID ctx = pkt->req->contextId();
 assert(ctx < sys->threads.numRunning());

-DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,  
ctx);

-
 pkt->setLE(readCpu(ctx,

[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add Tarmac tracing option to the simple Arm configs

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69684?usp=email )



Change subject: configs: Add Tarmac tracing option to the simple Arm configs
..

configs: Add Tarmac tracing option to the simple Arm configs

gem5 supports Tarmac trace generation for Arm simulations, but there
are no examples of how to use this feature.

This patch adds a `--tarmac-gen` option to three of the simple Arm
configs. Tarmac generation is useful for out-of-the-box users, and
this patch also provides an example of how to use the Tarmac
generation feature.

Change-Id: I0d3c523b5c0bb6d94de93bc502e4451622fb635d
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M src/cpu/CpuCluster.py
5 files changed, 117 insertions(+), 18 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 0072c1d..4af1ff1 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017,2019-2021 ARM Limited
+# Copyright (c) 2016-2017,2019-2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -123,7 +123,13 @@
 # Add CPU clusters to the system
 system.cpu_cluster = [
 devices.ArmCpuCluster(
-system, args.num_cores, args.cpu_freq, "1.0V",  
*cpu_types[args.cpu]

+system,
+args.num_cores,
+args.cpu_freq,
+"1.0V",
+*cpu_types[args.cpu],
+tarmac_gen=args.tarmac_gen,
+tarmac_dest=args.tarmac_dest,
 )
 ]

@@ -231,6 +237,17 @@
 parser.add_argument("--checkpoint", action="store_true")
 parser.add_argument("--restore", type=str, default=None)
 parser.add_argument(
+"--tarmac-gen",
+action="store_true",
+help="Write a Tarmac trace.",
+)
+parser.add_argument(
+"--tarmac-dest",
+choices=TarmacDump.vals,
+default="stdoutput",
+help="Destination for the Tarmac trace output. [Default:  
stdoutput]",

+)
+parser.add_argument(
 "--dtb-gen",
 action="store_true",
 help="Doesn't run simulation, it generates a DTB only",
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 3f005a4..bf1f6ba 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -106,6 +106,8 @@
 l1i_type,
 l1d_type,
 l2_type,
+tarmac_gen=False,
+tarmac_dest=None,
 ):
 super().__init__()
 self._cpu_type = cpu_type
@@ -120,7 +122,7 @@
 clock=cpu_clock, voltage_domain=self.voltage_domain
 )

-self.generate_cpus(cpu_type, num_cpus)
+self.generate_cpus(cpu_type, num_cpus, tarmac_gen, tarmac_dest)

 system.addCpuCluster(self)

@@ -177,23 +179,54 @@


 class AtomicCluster(ArmCpuCluster):
-def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [
-ObjectList.cpu_list.get("AtomicSimpleCPU"),
-None,
-None,
-None,
-]
-super().__init__(system, num_cpus, cpu_clock, cpu_voltage,  
*cpu_config)

+def __init__(
+self,
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage="1.0V",
+tarmac_gen=False,
+tarmac_dest=None,
+):
+super().__init__(
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage,
+cpu_type=ObjectList.cpu_list.get("AtomicSimpleCPU"),
+l1i_type=None,
+l1d_type=None,
+l2_type=None,
+tarmac_gen=tarmac_gen,
+tarmac_dest=tarmac_dest,
+)

 def addL1(self):
 pass


 class KvmCluster(ArmCpuCluster):
-def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,  
None]
-super().__init__(system, num_cpus, cpu_clock, cpu_voltage,  
*cpu_config)

+def __init__(
+self,
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage="1.0V",
+tarmac_gen=False,
+tarmac_dest=None,
+):
+super().__init__(
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage,
+cpu_type=ObjectList.cpu_list.get("ArmV8KvmCPU"),
+l1i_type=None,
+l1d_type=None,
+l2_type=None,
+tarmac_gen=tarmac_gen,
+tarmac_dest=tarmac_dest,
+)

 def addL1(self):
 pass
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index 48cbbdb..cc5f63f 100644
--- a/configs/example/arm/starter_fs.py
+++ b

[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Update Arm starter_se.py for new CpuCluster abstraction

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69679?usp=email )



Change subject: configs: Update Arm starter_se.py for new CpuCluster  
abstraction

..

configs: Update Arm starter_se.py for new CpuCluster abstraction

Changeset [1] introduced a new CpuCluster abstraction. This requires
some changes to the Arm `starter_se.py` and `devices.py`
configurations to accommodate the new structure.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/65891

Change-Id: I55fdd383c96286d179724e0f50771e2b5daaa6d7
---
M configs/example/arm/starter_se.py
1 file changed, 5 insertions(+), 5 deletions(-)



diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index ccdbe4f..6b4dce9 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017 ARM Limited
+# Copyright (c) 2016-2017, 2023 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -95,7 +95,7 @@

 # Add CPUs to the system. A cluster of CPUs typically have
 # private L1 caches and a shared L2 cache.
-self.cpu_cluster = devices.CpuCluster(
+self.cpu_cluster = devices.ArmCpuCluster(
 self, args.num_cores, args.cpu_freq, "1.2V",  
*cpu_types[args.cpu]

 )

@@ -114,11 +114,11 @@
 def numCpuClusters(self):
 return len(self._clusters)

-def addCpuCluster(self, cpu_cluster, num_cpus):
+def addCpuCluster(self, cpu_cluster):
 assert cpu_cluster not in self._clusters
-assert num_cpus > 0
+assert len(cpu_cluster) > 0
 self._clusters.append(cpu_cluster)
-self._num_cpus += num_cpus
+self._num_cpus += len(cpu_cluster)

 def numCpus(self):
 return self._num_cpus

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I55fdd383c96286d179724e0f50771e2b5daaa6d7
Gerrit-Change-Number: 69679
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Cooper 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an option to use 64-bit PMU counters

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69683?usp=email )



Change subject: arch-arm: Add an option to use 64-bit PMU counters
..

arch-arm: Add an option to use 64-bit PMU counters

Add support for 64-bit PMU counter registers (PMEVCNTR_EL0), as
specified in Armv8-A.

The counter registers are 32-bit by default, but 64-bit counters can
be chosen using the `ArmPMU.use64bitCounters` parameter.

Change-Id: Idb838a7438c7711438a7e078278bed21710049af
---
M src/arch/arm/ArmPMU.py
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
3 files changed, 16 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index f21aaff..61afe29 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -1,5 +1,5 @@
 # -*- mode:python -*-
-# Copyright (c) 2009-2014, 2017, 2020 ARM Limited
+# Copyright (c) 2009-2014, 2017, 2020, 2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -215,3 +215,5 @@
 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 eventCounters = Param.Int(31, "Number of supported PMU counters")
 interrupt = Param.ArmInterruptPin("PMU interrupt")
+use64bitCounters = Param.Bool(False, "Choose whether to use 64-bit or "
+  "32-bit PMEVCNTR_EL0 registers.")
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index f0ab978..89dc2c8 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2011-2014, 2017-2019, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,12 +56,13 @@

 PMU::PMU(const ArmPMUParams &p)
 : SimObject(p), BaseISADevice(),
+  use64bitCounters(p.use64bitCounters),
   reg_pmcnten(0), reg_pmcr(0),
   reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
   reg_pmceid0(0),reg_pmceid1(0),
   clock_remainder(0),
   maximumCounterCount(p.eventCounters),
-  cycleCounter(*this, maximumCounterCount),
+  cycleCounter(*this, maximumCounterCount, p.use64bitCounters),
   cycleCounterEventId(p.cycleEventId),
   swIncrementEvent(nullptr),
   reg_pmcr_conf(0),
@@ -175,7 +176,7 @@
 // at this stage all probe configurations are done
 // counters can be configured
 for (uint32_t index = 0; index < maximumCounterCount-1; index++) {
-counters.emplace_back(*this, index);
+counters.emplace_back(*this, index, use64bitCounters);
 }

 std::shared_ptr event = getEvent(cycleCounterEventId);
@@ -685,6 +686,7 @@
 {
 DPRINTF(Checkpoint, "Serializing Arm PMU\n");

+SERIALIZE_SCALAR(use64bitCounters);
 SERIALIZE_SCALAR(reg_pmcr);
 SERIALIZE_SCALAR(reg_pmcnten);
 SERIALIZE_SCALAR(reg_pmselr);
@@ -705,6 +707,7 @@
 {
 DPRINTF(Checkpoint, "Unserializing Arm PMU\n");

+UNSERIALIZE_SCALAR(use64bitCounters);
 UNSERIALIZE_SCALAR(reg_pmcr);
 UNSERIALIZE_SCALAR(reg_pmcnten);
 UNSERIALIZE_SCALAR(reg_pmselr);
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 46b10d0..ec60c6b 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2017-2018 ARM Limited
+ * Copyright (c) 2011-2014, 2017-2018, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -413,9 +413,10 @@
 /** State of a counter within the PMU. **/
 struct CounterState : public Serializable
 {
-CounterState(PMU &pmuReference, uint64_t counter_id)
+CounterState(PMU &pmuReference, uint64_t counter_id,
+ const bool is_64_bit)
 : eventId(0), filter(0), enabled(false),
-  overflow64(false), sourceEvent(nullptr),
+  overflow64(is_64_bit), sourceEvent(nullptr),
   counterId(counter_id), value(0), resetValue(false),
   pmu(pmuReference) {}

@@ -572,6 +573,9 @@
 void updateAllCounters();

   protected: /* State that needs to be serialized */
+/** Determine whether to use 64-bit or 32-bit counters. */
+bool use64bitCounters;
+
 /** Performance Monitor Count Enable Register */
 RegVal reg_pmcnten;


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Gerrit-Change-Number: 69683
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[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Add the O3 CPU as an option to baremetal.py

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69686?usp=email )



Change subject: configs: Add the O3 CPU as an option to baremetal.py
..

configs: Add the O3 CPU as an option to baremetal.py

Adds the O3_ARM_v7a CPU model as an extra option for the `--cpu-type`
to `configs/example/arm/baremetal.py`.

Change-Id: I717b168945bec22fb5ae17e37c2854df844bcb4f
---
M configs/example/arm/baremetal.py
1 file changed, 7 insertions(+), 0 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 345596d..9caab9d 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -52,6 +52,7 @@
 from common import MemConfig
 from common import ObjectList
 from common.cores.arm import HPI
+from common.cores.arm import O3_ARM_v7a

 import devices
 import workloads
@@ -63,6 +64,12 @@
 "atomic": (AtomicSimpleCPU, None, None, None),
 "minor": (MinorCPU, devices.L1I, devices.L1D, devices.L2),
 "hpi": (HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, HPI.HPI_L2),
+"o3": (
+O3_ARM_v7a.O3_ARM_v7a_3,
+O3_ARM_v7a.O3_ARM_v7a_ICache,
+O3_ARM_v7a.O3_ARM_v7a_DCache,
+O3_ARM_v7a.O3_ARM_v7aL2,
+),
 }



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[gem5-dev] [XS] Change in gem5/gem5[develop]: cpu: Add CpuCluster method to allow querying the number of CPUs.

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69678?usp=email )



Change subject: cpu: Add CpuCluster method to allow querying the number of  
CPUs.

..

cpu: Add CpuCluster method to allow querying the number of CPUs.

Add a `__len__` method to `CpuCluster` to allow clients to query the
number of CPUs.

Change-Id: I6fe680423ed6fc301faaf75b8685b080a4774fef
---
M src/cpu/CpuCluster.py
1 file changed, 4 insertions(+), 1 deletion(-)



diff --git a/src/cpu/CpuCluster.py b/src/cpu/CpuCluster.py
index 31fdc49..42a7112 100644
--- a/src/cpu/CpuCluster.py
+++ b/src/cpu/CpuCluster.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2022 Arm Limited
+# Copyright (c) 2022-2023 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -51,6 +51,9 @@
 def __iter__(self):
 return iter(self.cpus)

+def __len__(self):
+return len(self.cpus)
+
 def generate_cpus(self, cpu_type: "BaseCPU", num_cpus: int):
 """
 Instantiates the cpus within the cluster provided

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[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Make the configuration of the gicv4 parameter robust

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69685?usp=email )



Change subject: configs: Make the configuration of the gicv4 parameter  
robust

..

configs: Make the configuration of the gicv4 parameter robust

Only the GICv3 model has a `gicv4` parameter, causing the current
`baremetal.py` config to throw an exception when used with the
VExpress_GEM5_V1 platform containing a GICv2.

This patch checks for the existence of the `gicv4` parameter, allowing
all VExpress platforms to be used.

Change-Id: I72667a9caee64fa497bda516217cd424050eb242
---
M configs/example/arm/baremetal.py
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 4af1ff1..345596d 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -142,7 +142,8 @@
 system.auto_reset_addr = True

 # Using GICv3
-system.realview.gic.gicv4 = False
+if hasattr(system.realview.gic, "gicv4"):
+system.realview.gic.gicv4 = False

 system.highest_el_is_64 = True


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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Update Arm simple configs to enable --interactive option

2023-04-12 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69687?usp=email )



Change subject: configs: Update Arm simple configs to enable --interactive  
option

..

configs: Update Arm simple configs to enable --interactive option

Removed the calls to `sys.exit()` from the Arm simple configs. These
calls terminate gem5's embedded Python interpreter and gem5 at the end
of the config script, preventing gem5 from dropping into the
interactive IPython shell when the `--interactive` option has been
specified.

Change-Id: I0c350b0d107f297691255361d25c566c889f9469
---
M configs/example/arm/baremetal.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
3 files changed, 3 insertions(+), 9 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 9caab9d..ab24fd3 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -174,11 +174,9 @@
 m5.checkpoint(os.path.join(cpt_dir))
 print("Checkpoint done.")
 else:
-print(exit_msg, " @ ", m5.curTick())
+print(f"{exit_msg} ({event.getCode()}) @ {m5.curTick()}")
 break

-sys.exit(event.getCode())
-

 def main():
 parser = argparse.ArgumentParser(epilog=__doc__)
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index cc5f63f..f1e1983 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -194,12 +194,9 @@
 m5.checkpoint(os.path.join(cpt_dir))
 print("Checkpoint done.")
 else:
-print(exit_msg, " @ ", m5.curTick())
+print(f"{exit_msg} ({event.getCode()}) @ {m5.curTick()}")
 break

-sys.exit(event.getCode())
-
-
 def main():
 parser = argparse.ArgumentParser(epilog=__doc__)

diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index 33514c7..f21f399 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -257,8 +257,7 @@
 # Print the reason for the simulation exit. Some exit codes are
 # requests for service (e.g., checkpoints) from the simulation
 # script. We'll just ignore them here and exit.
-print(event.getCause(), " @ ", m5.curTick())
-sys.exit(event.getCode())
+print(f"{event.getCause()} ({event.getCode()}) @ {m5.curTick()}")


 if __name__ == "__m5_main__":

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0c350b0d107f297691255361d25c566c889f9469
Gerrit-Change-Number: 69687
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Cooper 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

2023-04-12 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69677?usp=email )



Change subject: base: fatal() if a socket path doesn't fit in  
sockaddr_un.sun_path.

..

base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

Normally this would just generate a warning, but a warning is easy to
miss, and truncating the path to fit would be surprising. Since the max
length isn't likely to change, a path which has to be truncated is
essentially fundementally wrong, and could be defined as something
else which is short enough before being used in the config.

Note that this only applies to either the abstract path which is just
a string, or the file name and not the directory path on a file based
socket.

Change-Id: I8702cf02c03053b5d0b6133f25b0e588de666f15
---
M src/base/socket.cc
M src/base/socket.hh
2 files changed, 10 insertions(+), 13 deletions(-)



diff --git a/src/base/socket.cc b/src/base/socket.cc
index 76dc73f..62f2071 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -261,15 +261,12 @@
 });
 }

-std::string
-ListenSocketUnix::truncate(const std::string &original, size_t max_len)
+void
+ListenSocketUnix::checkPathLength(const std::string &original, size_t  
max_len)

 {
-if (original.size() <= max_len)
-return original;
-
-std::string truncated = original.substr(0, max_len);
-warn("%s: Truncated \"%s\" to \"%s\"", name(), original, truncated);
-return truncated;
+fatal_if(original.size() > max_len,
+"Length of socket path '%s' is %d, greater than max %d.",
+original, original.size(), max_len);
 }

 void
@@ -303,9 +300,9 @@

 ListenSocketUnixFile::ListenSocketUnixFile(const std::string &_name,
 const std::string &_dir, const std::string &_fname) :
-ListenSocketUnix(_name), dir(_dir),
-fname(truncate(_fname, sizeof(sockaddr_un::sun_path) - 1))
+ListenSocketUnix(_name), dir(_dir), fname(_fname)
 {
+checkPathLength(fname, sizeof(sockaddr_un::sun_path) - 1);
 }

 ListenSocketUnixFile::~ListenSocketUnixFile()
@@ -385,9 +382,9 @@

 ListenSocketUnixAbstract::ListenSocketUnixAbstract(
 const std::string &_name, const std::string &_path) :
-ListenSocketUnix(_name),
-path(truncate(_path, sizeof(sockaddr_un::sun_path) - 1))
+ListenSocketUnix(_name), path(_path)
 {
+checkPathLength(path, sizeof(sockaddr_un::sun_path) - 1);
 }

 void
diff --git a/src/base/socket.hh b/src/base/socket.hh
index b8828e7..bc17213 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -162,7 +162,7 @@
   protected:
 virtual size_t prepSockaddrUn(sockaddr_un &addr) const = 0;

-std::string truncate(const std::string &original, size_t max_len);
+void checkPathLength(const std::string &original, size_t max_len);

 ListenSocketUnix(const std::string &_name) : ListenSocket(_name) {}


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8702cf02c03053b5d0b6133f25b0e588de666f15
Gerrit-Change-Number: 69677
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: newchange
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