[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: write device tree after setting up bootloader in ARMBoard

2023-04-20 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70017?usp=email )



Change subject: stdlib: write device tree after setting up bootloader in  
ARMBoard

..

stdlib: write device tree after setting up bootloader in ARMBoard

The generation of the device tree in an arm system requires knowing
cpu-release-addr property, which is only available after setting up
the bootloader.

cpu-release-addr specifies where the secondary CPUs spin/sleep(?) before
being waken up by the kernel.

The incorrect cpu-release-addr causes booting an arm system using the
standard library with the arm's provided bootloader+linux_kernel to
fail to regconize more than 1 core.

Change-Id: Ice0e38492e2f77020b0e30c42dd4e8b7ee58e598
Signed-off-by: Hoa Nguyen 
---
M src/python/gem5/components/boards/arm_board.py
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/python/gem5/components/boards/arm_board.py  
b/src/python/gem5/components/boards/arm_board.py

index 10e2c0e..b439edf 100644
--- a/src/python/gem5/components/boards/arm_board.py
+++ b/src/python/gem5/components/boards/arm_board.py
@@ -320,10 +320,6 @@
 # The workload needs to know the dtb_file.
 self.workload.dtb_filename = self._get_dtb_filename()

-# Calling generateDtb from class ArmSystem to add memory  
information to

-# the dtb file.
-self.generateDtb(self._get_dtb_filename())
-
 # Finally we need to setup the bootloader for the ArmBoard. An ARM
 # system requires three inputs to simulate a full system: a disk  
image,

 # the kernel file and the bootloader file(s).
@@ -331,6 +327,10 @@
 self, self._get_dtb_filename(), self._bootloader
 )

+# Calling generateDtb from class ArmSystem to add memory  
information to

+# the dtb file.
+self.generateDtb(self._get_dtb_filename())
+
 def _get_dtb_filename(self) -> str:
 """Returns the dtb file location.


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[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Patch for not building PcCountTracker when ISA is NULL

2023-04-20 Thread Zhantong Qiu (Gerrit) via gem5-dev 
Zhantong Qiu has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69998?usp=email )



Change subject: cpu: Patch for not building PcCountTracker when ISA is NULL
..

cpu: Patch for not building PcCountTracker when ISA is NULL

This commit modified the SConscript for PcCountTracker and
PcCountTrackerManager to not build when the simulation ISA is NULL

Change-Id: Ica640973aee7eb53a1683620e7cd2ce57d62447d
---
M src/cpu/probes/SConscript
1 file changed, 8 insertions(+), 7 deletions(-)



diff --git a/src/cpu/probes/SConscript b/src/cpu/probes/SConscript
index 9f43317..3629d2a 100644
--- a/src/cpu/probes/SConscript
+++ b/src/cpu/probes/SConscript
@@ -26,11 +26,12 @@

 Import("*")

-SimObject(
-"PcCountTracker.py",
-sim_objects=["PcCountTracker", "PcCountTrackerManager"],
-)
-Source("pc_count_tracker.cc")
-Source("pc_count_tracker_manager.cc")
+if not env['CONF']['USE_NULL_ISA']:
+SimObject(
+"PcCountTracker.py",
+sim_objects=["PcCountTracker", "PcCountTrackerManager"],
+)
+Source("pc_count_tracker.cc")
+Source("pc_count_tracker_manager.cc")

-DebugFlag("PcCountTracker")
+DebugFlag("PcCountTracker")

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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Patch to fix restoring with LoopPoint resource

2023-04-20 Thread Zhantong Qiu (Gerrit) via gem5-dev 
Zhantong Qiu has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69997?usp=email )



Change subject: stdlib: Patch to fix restoring with LoopPoint resource
..

stdlib: Patch to fix restoring with LoopPoint resource

This patch added a new variable _restore in the Looppoint class to only
take the relative count for either both the start and end or only the
end of the simulation region in the restoring region depending on if
there exists a warmup region or not.

Change-Id: I9827971f1dc608305004673b24d5d672e807efcb
---
M src/python/gem5/resources/looppoint.py
1 file changed, 39 insertions(+), 3 deletions(-)



diff --git a/src/python/gem5/resources/looppoint.py  
b/src/python/gem5/resources/looppoint.py

index 684faef..f09f466 100644
--- a/src/python/gem5/resources/looppoint.py
+++ b/src/python/gem5/resources/looppoint.py
@@ -70,6 +70,10 @@
 """Returns the PcCountPair for this Region PC value."""
 return PcCountPair(self.get_pc(), self.get_global())

+def get_relative_pc_count_pair(self) -> PcCountPair:
+"""Returns the relative PcCountPair for this Region PC value."""
+return PcCountPair(self.get_pc(), self.get_relative())
+
 def update_relative_count(self, manager: PcCountTrackerManager) ->  
None:

 """Updates the relative count."""
 self._relative = int(
@@ -164,6 +168,14 @@
 self.get_end().get_pc_count_pair(),
 ]

+def get_relative_pc_count_pairs(self) -> List[PcCountPair]:
+"""Returns the relative PC count pairs for the start and
+end LoopointRegionPCs."""
+return [
+self.get_start().get_relative_pc_count_pair(),
+self.get_end().get_relative_pc_count_pair(),
+]
+
 def update_relatives_counts(
 self, manager: PcCountTrackerManager, include_start: bool = False
 ) -> None:
@@ -229,6 +241,19 @@
 pc_count_pairs.extend(self.get_warmup().get_pc_count_pairs())
 return pc_count_pairs

+def get_relative_pc_count_pairs(self) -> List[PcCountPair]:
+"""Returns the relative PC count pairs for this Looppoint region.
+If the region has warmup region, then returns the relative PC count
+pair of both start and end of the simulation region, otherwise,
+only return the relative PC count pair of the end of the simulation
+region."""
+relative_pc_count_pairs = (
+self.get_simulation().get_relative_pc_count_pairs()
+)
+if not self.get_warmup():
+return [relative_pc_count_pairs[1]]
+return relative_pc_count_pairs
+
 def update_relatives_counts(self, manager: PcCountTrackerManager) ->  
None:

 """Updates the relative counds of this Looppoint region."""
 self.get_simulation().update_relatives_counts(
@@ -262,6 +287,7 @@
 :param regions: A dictionary mapping the region_ids with the
 LooppointRegions.
 """
+self._restore = False
 self._regions = regions
 self._manager = PcCountTrackerManager()
 self._manager.targets = self.get_targets()
@@ -271,6 +297,8 @@
 structure containing a single target region via its ID. This  
function

 will remove all irrelevant regions."""

+self._restore = True
+
 if region_id not in self._regions:
 raise Exception(f"Region ID '{region_id}' cannot be found.")

@@ -345,10 +373,18 @@
 def get_targets(self) -> List[PcCountPair]:
 """Returns the complete list of target PcCountPairs. That is, the
 PcCountPairs each region starts with as well as the relevant warmup
-intervals."""
+intervals.
+If it is restoring, it returns the relative PC Count pairs of the
+simulation region."""
 targets = []
-for rid in self.get_regions():
-targets.extend(self.get_regions()[rid].get_pc_count_pairs())
+if self._restore:
+for rid in self.get_regions():
+targets.extend(
+self.get_regions()[rid].get_relative_pc_count_pairs()
+)
+else:
+for rid in self.get_regions():
+ 
targets.extend(self.get_regions()[rid].get_pc_count_pairs())


 return targets


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[gem5-dev] Build failed in Jenkins: compiler-checks #581

2023-04-20 Thread jenkins-no-reply--- via gem5-dev 
See 


Changes:

[yenlinlai] base: Fix VNC server initialization

[melissakjost] base: Use  include for GCC v7


--
[...truncated 1.03 KB...]
 > git checkout -f c127a38f485ff22adabe07015dd201cf5a110f9b # timeout=10
Commit message: "base: Use  include for GCC v7"
 > git rev-list --no-walk 09023d4158703a33f483593ffa76001a805d015b # timeout=10
[Checks API] No suitable checks publisher found.
[compiler-checks] $ /bin/sh -xe /tmp/jenkins4542544372075181696.sh
+ ./tests/compiler-tests.sh -j 16
Starting build tests with 'gcc-version-12'...
'gcc-version-12' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-12'...
Done.
  * Building target 'ALL.opt' with 'gcc-version-12'...
Done.
  * Building target 'ALL.fast' with 'gcc-version-12'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-12'...
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  * Building target 'POWER.fast' with 'gcc-version-12'...
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  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-12'...
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  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-12'...
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  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-12'...
Done.
Starting build tests with 'gcc-version-11'...
  * Building target 'ALL.opt' with 'gcc-version-11'...
Done.
  * Building target 'ALL.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-10'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-9'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'X86.opt' with 'gcc-version-8'...
Done.
  * Building target 'X86.fast' with 'gcc-version-8'...
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Starting build tests with 'gcc-version-7'...
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-7'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-7'...
Done.
Starting build tests with 'clang-version-14'...
'clang-version-14' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'POWER.opt' with 'clang-version-14'...
Done.
  * Building target 'POWER.fast' with 'clang-version-14'...
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  * Building target 'NULL.opt' with 'clang-version-14'...
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  * Building target 'ARM_MESI_Three_Level_HTM.opt'

[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Add simple check for valid GPU MMIO trace

2023-04-20 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69978?usp=email )



Change subject: configs: Add simple check for valid GPU MMIO trace
..

configs: Add simple check for valid GPU MMIO trace

This file is a required input to the simulator for GPUFS. There seems to
be confusion from several users who are not providing this input. This
usually results in the amdgpu driver failing to load, leading to the
application under test exiting along with it.

This changeset adds a simple md5 hashsum check to compare against the
known good MMIO trace located in the gem5-resources repository.

Change-Id: I59819fc795a6bc4bc6badbd4d120db1246498987
---
M configs/example/gpufs/runfs.py
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/configs/example/gpufs/runfs.py b/configs/example/gpufs/runfs.py
index 4a28068a..52b79ab 100644
--- a/configs/example/gpufs/runfs.py
+++ b/configs/example/gpufs/runfs.py
@@ -30,6 +30,7 @@
 # System includes
 import argparse
 import math
+import hashlib

 # gem5 related
 import m5
@@ -145,6 +146,11 @@
 math.ceil(float(n_cu) / args.cu_per_scalar_cache)
 )

+# Verify MMIO trace is valid
+mmio_md5 =  
hashlib.md5(open(args.gpu_mmio_trace, "rb").read()).hexdigest()

+if mmio_md5 != "c4ff3326ae8a036e329b8b595c83bd6d":
+m5.util.panic("MMIO file does not match gem5 resources")
+
 system = makeGpuFSSystem(args)

 root = Root(

--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Allow other CPU types in GPUFS

2023-04-20 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69979?usp=email )



Change subject: configs: Allow other CPU types in GPUFS
..

configs: Allow other CPU types in GPUFS

Previously the CPU type and memory modes were hardcoded for KVM, because
there was a deadlock bug. After some recent testing, this deadlock bug
no longer exists with the simple CPU models. Thus, changing the configs
to allow for other CPU models as a first step toward lifting the KVM
requirement from GPUFS.

Change-Id: Ib616c3ef60f173871421b55a8bb73b25ce2990b5
---
M configs/example/gpufs/system/system.py
1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/configs/example/gpufs/system/system.py  
b/configs/example/gpufs/system/system.py

index a1b59ef..93f0194 100644
--- a/configs/example/gpufs/system/system.py
+++ b/configs/example/gpufs/system/system.py
@@ -61,7 +61,9 @@
 panic("Need at least 2GB of system memory to load amdgpu module")

 # Use the common FSConfig to setup a Linux X86 System
-(TestCPUClass, test_mem_mode, FutureClass) =  
Simulation.setCPUClass(args)

+(TestCPUClass, test_mem_mode) = Simulation.getCPUClass(args.cpu_type)
+if test_mem_mode == "atomic":
+test_mem_mode = "atomic_noncaching"
 disks = [args.disk_image]
 if args.second_disk is not None:
 disks.extend([args.second_disk])
@@ -91,10 +93,11 @@

 # Create specified number of CPUs. GPUFS really only needs one.
 system.cpu = [
-X86KvmCPU(clk_domain=system.cpu_clk_domain, cpu_id=i)
+TestCPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
 for i in range(args.num_cpus)
 ]
-system.kvm_vm = KvmVM()
+if ObjectList.is_kvm_cpu(TestCPUClass):
+system.kvm_vm = KvmVM()

 # Create AMDGPU and attach to southbridge
 shader = createGPU(system, args)

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[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Use higher dmesg level for GPUFS

2023-04-20 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69977?usp=email )



Change subject: configs: Use higher dmesg level for GPUFS
..

configs: Use higher dmesg level for GPUFS

The dmesg level is currently set to 3 which will not display errors if
the amdgpu driver fails to load. Changing to level 8 will show errors in
the gem5 terminal and is not too spammy. This will help GPUFS developers
with bug reports since we would actually be able to observe an error.
Currently if the driver fails to load, there is no way to detect it and
applications will attempt to run, usually failing on getting device
properties.

Change-Id: I56b9581c1a12a8ce329066d18d6a072d006c096d
---
M configs/example/gpufs/hip_cookbook.py
M configs/example/gpufs/hip_rodinia.py
M configs/example/gpufs/hip_samples.py
M configs/example/gpufs/vega10_kvm.py
4 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/configs/example/gpufs/hip_cookbook.py  
b/configs/example/gpufs/hip_cookbook.py

index 87c7547..6a7bb42 100644
--- a/configs/example/gpufs/hip_cookbook.py
+++ b/configs/example/gpufs/hip_cookbook.py
@@ -42,7 +42,7 @@
 cookbook_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0
-dmesg -n3
+dmesg -n8
 dd if=/root/roms/vega10.rom of=/dev/mem bs=1k seek=768 count=128
 if [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then
 echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5."
diff --git a/configs/example/gpufs/hip_rodinia.py  
b/configs/example/gpufs/hip_rodinia.py

index 8ed951b..b8a7858 100644
--- a/configs/example/gpufs/hip_rodinia.py
+++ b/configs/example/gpufs/hip_rodinia.py
@@ -43,7 +43,7 @@
 rodinia_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0
-dmesg -n3
+dmesg -n8
 dd if=/root/roms/vega10.rom of=/dev/mem bs=1k seek=768 count=128
 if [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then
 echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5."
diff --git a/configs/example/gpufs/hip_samples.py  
b/configs/example/gpufs/hip_samples.py

index ccc1719..9f83c25 100644
--- a/configs/example/gpufs/hip_samples.py
+++ b/configs/example/gpufs/hip_samples.py
@@ -42,7 +42,7 @@
 samples_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0
-dmesg -n3
+dmesg -n8
 dd if=/root/roms/vega10.rom of=/dev/mem bs=1k seek=768 count=128
 if [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then
 echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5."
diff --git a/configs/example/gpufs/vega10_kvm.py  
b/configs/example/gpufs/vega10_kvm.py

index 54253be..9c7e457 100644
--- a/configs/example/gpufs/vega10_kvm.py
+++ b/configs/example/gpufs/vega10_kvm.py
@@ -44,7 +44,7 @@
 demo_runscript = """\
 export LD_LIBRARY_PATH=/opt/rocm/lib:$LD_LIBRARY_PATH
 export HSA_ENABLE_INTERRUPT=0
-dmesg -n3
+dmesg -n8
 dd if=/root/roms/vega10.rom of=/dev/mem bs=1k seek=768 count=128
 if [ ! -f /lib/modules/`uname -r`/updates/dkms/amdgpu.ko ]; then
 echo "ERROR: Missing DKMS package for kernel `uname -r`. Exiting gem5."

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[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add `--with-pmu` option to the simple Arm FS configs

2023-04-20 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69957?usp=email )



Change subject: configs: Add `--with-pmu` option to the simple Arm FS  
configs

..

configs: Add `--with-pmu` option to the simple Arm FS configs

Add an option to add a PMU to the CPUs in `starter_fs.py` and
`baremetal.py`. By default PMUs will not be added.

Also adds an `--arm-ppi-number` option. Each PMU will be connected to
its core using the specified PPI.

Change-Id: I9cfb5781f211338919550f2320a7133d88801f6a
---
M configs/example/arm/baremetal.py
M configs/example/arm/starter_fs.py
2 files changed, 52 insertions(+), 0 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 8ffd2b4..be72ebe 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -157,6 +157,11 @@
 workload_class = workloads.workload_list.get(args.workload)
 system.workload = workload_class(object_file, system)

+if args.with_pmu:
+for cluster in system.cpu_cluster:
+interrupt_numbers = [args.pmu_ppi_number] * len(cluster)
+cluster.addPMUs(interrupt_numbers)
+
 if args.exit_on_uart_eot:
 for uart in system.realview.uart:
 uart.end_on_eot = True
@@ -182,6 +187,15 @@
 break


+def arm_ppi_arg(int_num: int) -> int:
+"""Argparse argument parser for valid Arm PPI numbers."""
+# PPIs (1056 <= int_num <= 1119) are not yet supported by gem5
+int_num = int(int_num)
+if 16 <= int_num <= 31:
+return int_num
+raise ValueError(f"{int_num} is not a valid Arm PPI number")
+
+
 def main():
 parser = argparse.ArgumentParser(epilog=__doc__)

@@ -258,6 +272,18 @@
 help="Destination for the Tarmac trace output. [Default:  
stdoutput]",

 )
 parser.add_argument(
+"--with-pmu",
+action="store_true",
+help="Add a PMU to each core in the cluster.",
+)
+parser.add_argument(
+"--pmu-ppi-number",
+type=arm_ppi_arg,
+default=23,
+help="The number of the PPI to use to connect each PMU to its  
core. "

+"Must be an integer and a valid PPI number (16 <= int_num <= 31).",
+)
+parser.add_argument(
 "--exit-on-uart-eot",
 action="store_true",
 help="Exit simulation if any of the UARTs receive an EOT. Many "
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index ebed188..07280bd 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -177,6 +177,11 @@
 ]
 system.workload.command_line = " ".join(kernel_cmd)

+if args.with_pmu:
+for cluster in system.cpu_cluster:
+interrupt_numbers = [args.pmu_ppi_number] * len(cluster)
+cluster.addPMUs(interrupt_numbers)
+
 return system


@@ -198,6 +203,15 @@
 break


+def arm_ppi_arg(int_num: int) -> int:
+"""Argparse argument parser for valid Arm PPI numbers."""
+# PPIs (1056 <= int_num <= 1119) are not yet supported by gem5
+int_num = int(int_num)
+if 16 <= int_num <= 31:
+return int_num
+raise ValueError(f"{int_num} is not a valid Arm PPI number")
+
+
 def main():
 parser = argparse.ArgumentParser(epilog=__doc__)

@@ -272,6 +286,18 @@
 default="stdoutput",
 help="Destination for the Tarmac trace output. [Default:  
stdoutput]",

 )
+parser.add_argument(
+"--with-pmu",
+action="store_true",
+help="Add a PMU to each core in the cluster.",
+)
+parser.add_argument(
+"--pmu-ppi-number",
+type=arm_ppi_arg,
+default=23,
+help="The number of the PPI to use to connect each PMU to its  
core. "

+"Must be an integer and a valid PPI number (16 <= int_num <= 31).",
+)
 parser.add_argument("--checkpoint", action="store_true")
 parser.add_argument("--restore", type=str, default=None)


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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Add baremetal.py option to dump stats on PMU interrupt.

2023-04-20 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69959?usp=email )



Change subject: configs: Add baremetal.py option to dump stats on PMU  
interrupt.

..

configs: Add baremetal.py option to dump stats on PMU interrupt.

Add an option to baremetal.py to optionally enable the PMU
`dumpStatsOnInterrupt` feature.

Change-Id: Ie2ffe11c6aa1f3a57a58425ccec3681c780065c8
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
2 files changed, 15 insertions(+), 2 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index be72ebe..c45b416 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -160,7 +160,10 @@
 if args.with_pmu:
 for cluster in system.cpu_cluster:
 interrupt_numbers = [args.pmu_ppi_number] * len(cluster)
-cluster.addPMUs(interrupt_numbers)
+cluster.addPMUs(
+interrupt_numbers,
+dump_stats_on_interrupt=args.pmu_dump_stats_on_interrupt,
+)

 if args.exit_on_uart_eot:
 for uart in system.realview.uart:
@@ -284,6 +287,11 @@
 "Must be an integer and a valid PPI number (16 <= int_num <= 31).",
 )
 parser.add_argument(
+"--pmu-dump-stats-on-interrupt",
+action="store_true",
+help="Dump and reset gem5 stats on PMU interrupt.",
+)
+parser.add_argument(
 "--exit-on-uart-eot",
 action="store_true",
 help="Exit simulation if any of the UARTs receive an EOT. Many "
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 02574d2..c444a1d 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -147,7 +147,7 @@
 cpu.connectCachedPorts(self.toL2Bus.cpu_side_ports)
 self.toL2Bus.mem_side_ports = self.l2.cpu_side

-def addPMUs(self, ints, events=[]):
+def addPMUs(self, ints, events=[], dump_stats_on_interrupt=False):
 """
 Instantiates 1 ArmPMU per PE. The method is accepting a list of
 interrupt numbers (ints) used by the PMU and a list of events to
@@ -159,12 +159,17 @@
 :type ints: List[int]
 :param events: Additional events to be measured by the PMUs
 :type events: List[Union[ProbeEvent, SoftwareIncrement]]
+:param dump_stats_on_interrupt: If true, then dump the gem5  
statistics

+when a PMU interrupt is triggered.
+:type dump_stats_on_interrupt: bool
+
 """
 assert len(ints) == len(self.cpus)
 for cpu, pint in zip(self.cpus, ints):
 int_cls = ArmPPI if pint < 32 else ArmSPI
 for isa in cpu.isa:
 isa.pmu = ArmPMU(interrupt=int_cls(num=pint))
+isa.pmu.dumpStatsOnInterrupt = dump_stats_on_interrupt
 isa.pmu.addArchEvents(
 cpu=cpu,
 itb=cpu.mmu.itb,

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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add option to dump & reset stats on Arm PMU interrupt

2023-04-20 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69958?usp=email )



Change subject: arch-arm: Add option to dump & reset stats on Arm PMU  
interrupt

..

arch-arm: Add option to dump & reset stats on Arm PMU interrupt

Add an option `dumpStatsOnInterrupt` to ArmPMU.

This feature allows the PMU to be used to control the run of sampled
workloads which must run for a specified number of warmup and live
instructions. The stats will be reset when the PMU interrupts used to
count the instructions stream are triggered.

Change-Id: Ife02fe8e467dec91a2d4fda3f7dc9540a092f1ec
---
M src/arch/arm/ArmPMU.py
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
3 files changed, 14 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 3eaed07..13c2e0b 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -221,5 +221,9 @@
 # full implementation of FEAT_PMUv3p5.
 use64bitCounters = Param.Bool(
 False,
-"Choose whether to use 64-bit or " "32-bit PMEVCNTR_EL0  
registers.",
+"Choose whether to use 64-bit or 32-bit PMEVCNTR_EL0  
registers.",

+)
+
+dumpStatsOnInterrupt = Param.Bool(
+False, "Dump and reset staticstics on PMU interrupt."
 )
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 89dc2c8..b2c3147 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -46,6 +46,7 @@
 #include "dev/arm/base_gic.hh"
 #include "dev/arm/generic_timer.hh"
 #include "params/ArmPMU.hh"
+#include "sim/stat_control.hh"

 namespace gem5
 {
@@ -57,6 +58,7 @@
 PMU::PMU(const ArmPMUParams )
 : SimObject(p), BaseISADevice(),
   use64bitCounters(p.use64bitCounters),
+  dumpStatsOnInterrupt(p.dumpStatsOnInterrupt),
   reg_pmcnten(0), reg_pmcr(0),
   reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
   reg_pmceid0(0),reg_pmceid1(0),
@@ -660,6 +662,10 @@
 void
 PMU::raiseInterrupt()
 {
+if (dumpStatsOnInterrupt) {
+// Dump stats, with reset, at curTick(), no-repeat
+statistics::schedStatEvent(true, true, curTick(), false);
+}
 if (interrupt) {
 DPRINTF(PMUVerbose, "Delivering PMU interrupt.\n");
 interrupt->raise();
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index ec60c6b..3594e8e 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -576,6 +576,9 @@
 /** Determine whether to use 64-bit or 32-bit counters. */
 bool use64bitCounters;

+/** Dump and reset statistics on PMU interrupt. */
+bool dumpStatsOnInterrupt;
+
 /** Performance Monitor Count Enable Register */
 RegVal reg_pmcnten;


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