date:20230425

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: refactor bitfields of insts

2023-04-25 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68417?usp=email )


Change subject: arch-riscv: refactor bitfields of insts
..

arch-riscv: refactor bitfields of insts

+ move bitfields of ExtMachInst defined in bitfields.hh
  to types.hh

Change-Id: Ic25e2fd1a887f87231268a4449d8755593919a0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68417
Maintainer: Bobby Bruce 
Tested-by: kokoro 
Reviewed-by: Hoa Nguyen 
Reviewed-by: Roger Chang 
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/insts/amo.cc
D src/arch/riscv/insts/bitfields.hh
M src/arch/riscv/insts/mem.cc
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/insts/unknown.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/types.hh
M util/m5/src/abi/riscv/m5op.S
10 files changed, 151 insertions(+), 55 deletions(-)

Approvals:
  Roger Chang: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Hoa Nguyen: Looks good to me, approved




diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index b816c17..7faa310 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -42,6 +42,7 @@
 {
 aligned = true;
 mid = false;
+machInst = 0;
 emi = 0;
 }

@@ -58,20 +59,20 @@

 bool aligned = pc.instAddr() % sizeof(machInst) == 0;
 if (aligned) {
-emi = inst;
-if (compressed(emi))
-emi = bits(emi, mid_bit, 0);
+emi.instBits = inst;
+if (compressed(inst))
+emi.instBits = bits(inst, mid_bit, 0);
 outOfBytes = !compressed(emi);
 instDone = true;
 } else {
 if (mid) {
-assert(bits(emi, max_bit, mid_bit + 1) == 0);
-replaceBits(emi, max_bit, mid_bit + 1, inst);
+assert(bits(emi.instBits, max_bit, mid_bit + 1) == 0);
+replaceBits(emi.instBits, max_bit, mid_bit + 1, inst);
 mid = false;
 outOfBytes = false;
 instDone = true;
 } else {
-emi = bits(inst, max_bit, mid_bit + 1);
+emi.instBits = bits(inst, max_bit, mid_bit + 1);
 mid = !compressed(emi);
 outOfBytes = true;
 instDone = compressed(emi);
@@ -83,7 +84,7 @@
 Decoder::decode(ExtMachInst mach_inst, Addr addr)
 {
 DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
-mach_inst, addr);
+mach_inst.instBits, addr);

 StaticInstPtr  = instMap[mach_inst];
 if (!si)
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index d845c91..052586e 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -32,7 +32,6 @@
 #include 
 #include 

-#include "arch/riscv/insts/bitfields.hh"
 #include "arch/riscv/utility.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
@@ -49,7 +48,7 @@
 Addr pc, const loader::SymbolTable *symtab) const
 {
 std::stringstream ss;
-ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
+ss << csprintf("0x%08x", machInst.instBits) << ' ' << mnemonic;
 return ss.str();
 }

@@ -66,14 +65,14 @@
 {
 std::stringstream ss;
 ss << mnemonic;
-if (AQ || RL)
+if (machInst.aq || machInst.rl)
 ss << '_';
-if (AQ)
+if (machInst.aq)
 ss << "aq";
-if (RL)
+if (machInst.rl)
 ss << "rl";
-ss << ' ' << registerName(intRegClass[RD]) << ", ("
-<< registerName(intRegClass[RS1]) << ')';
+ss << ' ' << registerName(intRegClass[machInst.rd]) << ", ("
+<< registerName(intRegClass[machInst.rs1]) << ')';
 return ss.str();
 }

@@ -94,15 +93,15 @@
 {
 std::stringstream ss;
 ss << mnemonic;
-if (AQ || RL)
+if (machInst.aq || machInst.rl)
 ss << '_';
-if (AQ)
+if (machInst.aq)
 ss << "aq";
-if (RL)
+if (machInst.rl)
 ss << "rl";
-ss << ' ' << registerName(intRegClass[RD]) << ", "
-<< registerName(intRegClass[RS2]) << ", ("
-<< registerName(intRegClass[RS1]) << ')';
+ss << ' ' << registerName(intRegClass[machInst.rd]) << ", "
+<< registerName(intRegClass[machInst.rs2]) << ", ("
+<< registerName(intRegClass[machInst.rs1]) << ')';
 return ss.str();
 }

@@ -124,15 +123,15 @@
 {
 std::stringstream ss;
 ss << mnemonic;
-if (AQ || RL)
+if (machInst.aq || machInst.rl)
 ss << '_';
-if (AQ)
+if (machInst.aq)
 ss << "aq";
-if (RL)
+if (machInst.rl)
 ss << "rl";
-ss << ' ' << registerName(intRegClass[RD]) << ", "
-<< registerName(intRegClass[RS2]) << ", ("
-<< registerName(intRegClass[RS1]) << ')';
+ss << ' ' << registerName(intRegClass[machInst.rd]) << ", "
+<< registerName(intRegClass[machInst.rs2]) << ", ("
+<<

[gem5-dev] [S] Change in gem5/gem5[develop]: arch: Add vector function unit and OpClass enums

2023-04-25 Thread Roger Chang (Gerrit) via gem5-dev

Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/67293?usp=email )


Change subject: arch: Add vector function unit and OpClass enums
..

arch: Add vector function unit and OpClass enums

These enums are needed for risc-v vector extension

Change-Id: Ia61682c43c89ac2043fb9d1d5c349dfd646fb88d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67293
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Hoa Nguyen 
Reviewed-by: Roger Chang 
---
M src/cpu/FuncUnit.py
M src/cpu/op_class.hh
2 files changed, 43 insertions(+), 0 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved
  kokoro: Regressions pass
  Roger Chang: Looks good to me, approved




diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 4a2733a..a1050de 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -98,6 +98,25 @@
 "FloatMemWrite",
 "IprAccess",
 "InstPrefetch",
+"VectorUnitStrideLoad",
+"VectorUnitStrideStore",
+"VectorUnitStrideMaskLoad",
+"VectorUnitStrideMaskStore",
+"VectorStridedLoad",
+"VectorStridedStore",
+"VectorIndexedLoad",
+"VectorIndexedStore",
+"VectorUnitStrideFaultOnlyFirstLoad",
+"VectorWholeRegisterLoad",
+"VectorWholeRegisterStore",
+"VectorIntegerArith",
+"VectorFloatArith",
+"VectorFloatConvert",
+"VectorIntegerReduce",
+"VectorFloatReduce",
+"VectorMisc",
+"VectorIntegerExtension",
+"VectorConfig",
 ]


diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 4de018f..94d2794 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -108,6 +108,30 @@
 static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
 static const OpClass IprAccessOp = enums::IprAccess;
 static const OpClass InstPrefetchOp = enums::InstPrefetch;
+static const OpClass VectorUnitStrideLoadOp = enums::VectorUnitStrideLoad;
+static const OpClass VectorUnitStrideStoreOp =  
enums::VectorUnitStrideStore;

+static const OpClass VectorUnitStrideMaskLoadOp
+ = enums::VectorUnitStrideMaskLoad;
+static const OpClass VectorUnitStrideMaskStoreOp
+ = enums::VectorUnitStrideMaskStore;
+static const OpClass VectorStridedLoadOp = enums::VectorStridedLoad;
+static const OpClass VectorStridedStoreOp = enums::VectorStridedStore;
+static const OpClass VectorIndexedLoadOp = enums::VectorIndexedLoad;
+static const OpClass VectorIndexedStoreOp = enums::VectorIndexedStore;
+static const OpClass VectorUnitStrideFaultOnlyFirstLoadOp
+ = enums::VectorUnitStrideFaultOnlyFirstLoad;
+static const OpClass VectorWholeRegisterLoadOp
+ = enums::VectorWholeRegisterLoad;
+static const OpClass VectorWholeRegisterStoreOp
+ = enums::VectorWholeRegisterStore;
+static const OpClass VectorIntegerArithOp = enums::VectorIntegerArith;
+static const OpClass VectorFloatArithOp = enums::VectorFloatArith;
+static const OpClass VectorFloatConvertOp = enums::VectorFloatConvert;
+static const OpClass VectorIntegerReduceOp = enums::VectorIntegerReduce;
+static const OpClass VectorFloatReduceOp = enums::VectorFloatReduce;
+static const OpClass VectorMiscOp = enums::VectorMisc;
+static const OpClass VectorIntegerExtensionOp =  
enums::VectorIntegerExtension;

+static const OpClass VectorConfigOp = enums::VectorConfig;
 static const OpClass Num_OpClasses = enums::Num_OpClass;

 } // namespace gem5

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/67293?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia61682c43c89ac2043fb9d1d5c349dfd646fb88d
Gerrit-Change-Number: 67293
Gerrit-PatchSet: 8
Gerrit-Owner: 轩胡 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Roger Chang 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] Jenkins build is back to normal : compiler-checks #586

2023-04-25 Thread jenkins-no-reply--- via gem5-dev

See 

___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits

2023-04-25 Thread Nikos Nikoleris (Gerrit) via gem5-dev

Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70057?usp=email )



Change subject: base: Use the MSB rather than the LSB in  
AddrRange:removeIntlvBits

..

base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits

In many cases, the LSB (as constrained by the masks) of an interleaved
address range falls within the virtual page offset. For typical
workloads, the page offset and the least significant bits have more
entropy than the most significant bits. Consequently, removing a
bit closer to the MSB preserves bits tends to provide a more uniform
utilization of resources.

Change-Id: I361d8130d080a1be23f85de12afef0432efcd11e
Signed-off-by: Nikos Nikoleris 
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 14 insertions(+), 13 deletions(-)



diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index 11fb1cd..40545ba 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -523,17 +523,17 @@
 }

 // Get the LSB set from each mask
-int masks_lsb[masks.size()];
+int masks_msb[masks.size()];
 for (unsigned int i = 0; i < masks.size(); i++) {
-masks_lsb[i] = ctz64(masks[i]);
+masks_msb[i] = sizeof(Addr) * 8 - clz64(masks[i]) - 1;
 }

 // we need to sort the list of bits we will discard as we
 // discard them one by one starting.
-std::sort(masks_lsb, masks_lsb + masks.size());
+std::sort(masks_msb, masks_msb + masks.size());

 for (unsigned int i = 0; i < masks.size(); i++) {
-const int intlv_bit = masks_lsb[i];
+const int intlv_bit = masks_msb[i];
 if (intlv_bit > 0) {
 // on every iteration we remove one bit from the input
 // address, and therefore the lowest invtl_bit has
@@ -562,15 +562,15 @@
 }

 // Get the LSB set from each mask
-int masks_lsb[masks.size()];
+int masks_msb[masks.size()];
 for (unsigned int i = 0; i < masks.size(); i++) {
-masks_lsb[i] = ctz64(masks[i]);
+masks_msb[i] = sizeof(Addr) * CHAR_BIT - clz64(masks[i]) - 1;
 }

 // Add bits one-by-one from the LSB side.
-std::sort(masks_lsb, masks_lsb + masks.size());
+std::sort(masks_msb, masks_msb + masks.size());
 for (unsigned int i = 0; i < masks.size(); i++) {
-const int intlv_bit = masks_lsb[i];
+const int intlv_bit = masks_msb[i];
 if (intlv_bit > 0) {
 // on every iteration we add one bit from the input
 // address, but the lowest invtl_bit in the iteration is
@@ -583,7 +583,7 @@
 }

 for (unsigned int i = 0; i < masks.size(); i++) {
-const int lsb = ctz64(masks[i]);
+const int lsb = sizeof(Addr) * CHAR_BIT - clz64(masks[i]) - 1;
 const Addr intlv_bit = bits(intlvMatch, i);
 // Calculate the mask ignoring the LSB
 const Addr masked = a & masks[i] & ~(1 << lsb);
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 1e86154..bf7d2f7 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -743,16 +743,17 @@
 uint8_t intlv_match = 1;
 AddrRange r(start, end, masks, intlv_match);

-Addr input = (1 << 9) | (1 << 8) | 1;
+Addr input = (1 << 10) | (1 << 9) | (1 << 3);
 /*
  * (1 << 8) and 1 are interleaving bits to be removed.
  */
 Addr output = r.removeIntlvBits(input);

 /*
- * The bit, formally at position 9, is now at 7.
+ * The bit, previously at position 10, is now at 9 and the bit
+ * previously at position 9, is now at 8 and bit 3 has been discarded.
  */
-EXPECT_EQ((1 << 7), output);
+EXPECT_EQ((1 << 9) | (1 << 8), output);

 /*
  * Re-adding the interleaving.
@@ -826,7 +827,7 @@
 uint8_t intlv_match = 0;
 AddrRange r(start, end, masks, intlv_match);

-Addr value = ((1 << 10) | (1 << 9) | (1 <<  8) | (1 << 2) | (1 << 1) |  
1);
+Addr value = ((1 << 10) | (1 << 9) | (1 <<  8) | (1 << 4) | (1 << 1) |  
1);

 Addr value_interleaving_bits_removed =
 ((1 << 9) | (1 << 8) | (1 << 7) | (1 << 1) |  
1);



--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70057?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I361d8130d080a1be23f85de12afef0432efcd11e
Gerrit-Change-Number: 70057
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv: refactor bitfields of insts

[gem5-dev] [S] Change in gem5/gem5[develop]: arch: Add vector function unit and OpClass enums

[gem5-dev] Jenkins build is back to normal : compiler-checks #586

[gem5-dev] [S] Change in gem5/gem5[develop]: base: Use the MSB rather than the LSB in AddrRange:removeIntlvBits

4 matches

Site Navigation

Mail list logo

Footer information