[gem5-users] Request for Guidance: Extracting Detailed Information for Floating-Point Instructions
Dear gem5 Community, I am currently using the gem5 simulator for my research work and I find it a powerful and insightful tool for studying and understanding the inner workings of computer architectures. I am particularly interested in exploring and understanding the behavior of floating-point instructions within certain benchmarking suites. For my study, I need to extract detailed information about each floating-point instruction that is executed, such as the Program Counter (PC), source register, and destination register. Despite my efforts, I am having difficulty obtaining this data. I have been trying to use the trace functionality, but it seems I may be missing some key steps or perhaps there is a better approach. Could anyone guide me on how to accomplish this task? Specifically, I would appreciate it if you could share any scripts, changes in the source code, configuration options, or any other method that would allow me to collect the information I need. Your assistance in this matter would be greatly appreciated. I look forward to the possibility of learning from your collective experience and expertise. Thank you for your time and consideration. Best regards, David Alexandra ___ gem5-users mailing list -- gem5-us...@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Assistance Required - Assertion Failure in RegFile
Dear gem5 Community, I am currently using the gem5 simulator version 22.1.0.0, compiled on June 14, 2023, for my research work and I have encountered an issue that I need help with. During the simulation, the program aborts with an assertion failure in the register file. The error message is: cCopy code gem5.opt: build/ARM/cpu/regfile.hh:75: const Reg& gem5::RegFile::reg(size_t) const [with Reg = long unsigned int; size_t = long unsigned int]: Assertion `sizeof(Reg) == _regBytes && idx < _size' failed. Program aborted at tick 94517000 The command that I used to run the simulation is: bashCopy code ./build/ARM/gem5.opt --debug-flags=MinorExecuteOp --debug-file=fadd1.txt configs/example/arm/starter_se.py --cpu="hpi" --num-cores=1 "/home/david1136/ARM/se-benchmarks/FloatMM" I have tried to diagnose the problem myself, but I haven't been able to identify the root cause. I believe this issue might be related to an incorrect register access, although I am not entirely certain. I have checked my configuration and my setup, and everything appears to be correct. Could you provide me with some guidance on how to troubleshoot this problem, or indicate whether this is a known issue that could be resolved with a patch or an update to the gem5 version I am using? Any help you can provide would be greatly appreciated. ___ gem5-users mailing list -- gem5-us...@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Extract Instructions
I tried to extract the fmul type instructions and display them in the
format:
[image: image.png]
I have these functions in execute.cc
// Cod adaugat
std::string disassembledInst =
inst->staticInst->disassemble(inst->pc->instAddr(),
::debugSymbolTable);
if(inst->staticInst->opClass()==FloatMultOp){
if (disassembledInst.find("fmul") != std::string::npos) {
// Instruction details
DPRINTF(MinorExecuteOp, "Exec inst: %s\n", *inst);
// Op Class
DPRINTF(MinorExecuteOp, " Op Class inst: %s\n",
enums::OpClassStrings[inst->staticInst->opClass()]);
// Op Dissasembled
DPRINTF(MinorExecuteOp, "Dissasembled: %s\n",
inst->staticInst->disassemble(inst->pc->instAddr(),
::debugSymbolTable));
// Cast from StaticInstPtr to StaticInst
StaticInst* leInst = inst->staticInst.get();
// Print source register values
for (int i = 0; i < leInst->numSrcRegs(); i++) {
RegId regId = leInst->srcRegIdx(i);
float regValue;
context.getFloatRegOperand(leInst, i, );
DPRINTF(MinorExecuteOp, " SrcReg%d=%d (%s)\n",/*i,
regValue,*/ printRegName(regId));
}
// Print destination register values
for (int i = 0; i < leInst->numDestRegs(); i++) {
RegId regId = leInst->destRegIdx(i);
float regValue;
context.getFloatRegOperand(leInst, i, );
DPRINTF(MinorExecuteOp, " DestReg%d=%d (%s)\n", /*i,
regValue,*/ printRegName(regId));
}
}
}
fault = inst->staticInst->execute(,
inst->traceData);
/*Set the predicate for tracing and dump*/
if(inst->traceData){
inst->traceData->setPredicate(context.readPredicate());
}
// Cod adaugat
// Print destination register values
if(inst->staticInst->opClass()==FloatMultOp){
if (disassembledInst.find("fmul") != std::string::npos) {
// Cast from StaticInstPtr to StaticInst
StaticInst* leInst = inst->staticInst.get();
for (int i = 0; i < leInst->numDestRegs(); i++) {
RegId regId = leInst->destRegIdx(i);
float regValue;
context.getFloatRegOperand(leInst, i, );
DPRINTF(MinorExecuteOp, " DestReg%d=%d (%s)\n", /*i,
regValue,*/ printRegName(regId));
}
}
}
// Cod adaugat
and the getFloatRegOperand looks like this
[image: image.png]
has anyone tried to do this before and can help me?
Thank you very much! Have a nice day!
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