[gem5-dev] Change in gem5/gem5[master]: tests: Increase jenkins test timeout to 4 hours.

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23463 )


Change subject: tests: Increase jenkins test timeout to 4 hours.
..

tests: Increase jenkins test timeout to 4 hours.

Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23463
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Giacomo Travaglini 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/jenkins/presubmit.cfg
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/jenkins/presubmit.cfg b/tests/jenkins/presubmit.cfg
index 742a6fc..6c9296e 100644
--- a/tests/jenkins/presubmit.cfg
+++ b/tests/jenkins/presubmit.cfg
@@ -2,3 +2,5 @@

 # Location of the continuous batch script in repository.
 build_file: "jenkins-gem5-prod/tests/jenkins/presubmit.sh"
+
+timeout_mins: 240

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23463
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Gerrit-Change-Number: 23463
Gerrit-PatchSet: 3
Gerrit-Owner: Rahul Thakur 
Gerrit-Assignee: Bobby Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Rahul Thakur 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby Bruce 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: tests: Incrase jenkins test timeout to 4 hours.

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23463 )



Change subject: tests: Incrase jenkins test timeout to 4 hours.
..

tests: Incrase jenkins test timeout to 4 hours.

Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
---
M tests/jenkins/presubmit.cfg
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/tests/jenkins/presubmit.cfg b/tests/jenkins/presubmit.cfg
index 742a6fc..6c9296e 100644
--- a/tests/jenkins/presubmit.cfg
+++ b/tests/jenkins/presubmit.cfg
@@ -2,3 +2,5 @@

 # Location of the continuous batch script in repository.
 build_file: "jenkins-gem5-prod/tests/jenkins/presubmit.sh"
+
+timeout_mins: 240

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23463
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Gerrit-Change-Number: 23463
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Continuous integration is live!

[Rahul Thakur]

Hi Jason,

The kokoro environment provides many installed software including clang
toolchain. If you need a more complete list of available SW, LMK.

/usr/bin $ ls -l clang*
lrwxrwxrwx 1 root root 25 Feb 12  2015 clang-3.5 ->
../lib/llvm-3.5/bin/clang
lrwxrwxrwx 1 root root 27 Feb 12  2015 clang++-3.5 ->
../lib/llvm-3.5/bin/clang++
lrwxrwxrwx 1 root root 25 Jul 23  2018 clang-3.6 ->
../lib/llvm-3.6/bin/clang
lrwxrwxrwx 1 root root 27 Jul 23  2018 clang++-3.6 ->
../lib/llvm-3.6/bin/clang++
lrwxrwxrwx 1 root root 25 Jul 18  2017 clang-3.8 ->
../lib/llvm-3.8/bin/clang
lrwxrwxrwx 1 root root 27 Jul 18  2017 clang++-3.8 ->
../lib/llvm-3.8/bin/clang++
lrwxrwxrwx 1 root root 25 Jul 26  2017 clang-3.9 ->
../lib/llvm-3.9/bin/clang
lrwxrwxrwx 1 root root 27 Jul 26  2017 clang++-3.9 ->
../lib/llvm-3.9/bin/clang++
lrwxrwxrwx 1 root root 44 Feb 12  2015 clang-apply-replacements-3.5 ->
../lib/llvm-3.5/bin/clang-apply-replacements
lrwxrwxrwx 1 root root 44 Jul 23  2018 clang-apply-replacements-3.6 ->
../lib/llvm-3.6/bin/clang-apply-replacements
lrwxrwxrwx 1 root root 44 Jul 18  2017 clang-apply-replacements-3.8 ->
../lib/llvm-3.8/bin/clang-apply-replacements
lrwxrwxrwx 1 root root 44 Jul 26  2017 clang-apply-replacements-3.9 ->
../lib/llvm-3.9/bin/clang-apply-replacements
lrwxrwxrwx 1 root root 31 Feb 12  2015 clang-check-3.5 ->
../lib/llvm-3.5/bin/clang-check
lrwxrwxrwx 1 root root 31 Jul 23  2018 clang-check-3.6 ->
../lib/llvm-3.6/bin/clang-check
lrwxrwxrwx 1 root root 31 Jul 18  2017 clang-check-3.8 ->
../lib/llvm-3.8/bin/clang-check
lrwxrwxrwx 1 root root 31 Jul 26  2017 clang-check-3.9 ->
../lib/llvm-3.9/bin/clang-check
lrwxrwxrwx 1 root root 28 Jul 18  2017 clang-cl-3.8 ->
../lib/llvm-3.8/bin/clang-cl
lrwxrwxrwx 1 root root 28 Jul 26  2017 clang-cl-3.9 ->
../lib/llvm-3.9/bin/clang-cl
lrwxrwxrwx 1 root root 39 Jul 26  2017 clang-include-fixer-3.9 ->
../lib/llvm-3.9/bin/clang-include-fixer
lrwxrwxrwx 1 root root 31 Feb 12  2015 clang-query-3.5 ->
../lib/llvm-3.5/bin/clang-query
lrwxrwxrwx 1 root root 31 Jul 23  2018 clang-query-3.6 ->
../lib/llvm-3.6/bin/clang-query
lrwxrwxrwx 1 root root 31 Jul 18  2017 clang-query-3.8 ->
../lib/llvm-3.8/bin/clang-query
lrwxrwxrwx 1 root root 31 Jul 26  2017 clang-query-3.9 ->
../lib/llvm-3.9/bin/clang-query
lrwxrwxrwx 1 root root 32 Jul 23  2018 clang-rename-3.6 ->
../lib/llvm-3.6/bin/clang-rename
lrwxrwxrwx 1 root root 32 Jul 18  2017 clang-rename-3.8 ->
../lib/llvm-3.8/bin/clang-rename
lrwxrwxrwx 1 root root 32 Jul 26  2017 clang-rename-3.9 ->
../lib/llvm-3.9/bin/clang-rename
lrwxrwxrwx 1 root root 32 Feb 12  2015 clang-tblgen-3.5 ->
../lib/llvm-3.5/bin/clang-tblgen
lrwxrwxrwx 1 root root 32 Jul 23  2018 clang-tblgen-3.6 ->
../lib/llvm-3.6/bin/clang-tblgen
lrwxrwxrwx 1 root root 32 Jul 26  2017 clang-tblgen-3.9 ->
../lib/llvm-3.9/bin/clang-tblgen
lrwxrwxrwx 1 root root 30 Feb 12  2015 clang-tidy-3.5 ->
../lib/llvm-3.5/bin/clang-tidy
lrwxrwxrwx 1 root root 30 Jul 23  2018 clang-tidy-3.6 ->
../lib/llvm-3.6/bin/clang-tidy


FYI, kokoro can use custom VM images or docker (via GCR) if there is need
to change environment.
I can grant limited users (only from gem5-admins ACL) access to a
test-debug VM to check the kokoro GCP Ubuntu platform/env. Please email me
your ssh public key.

Thanks,
Rahul.


On Fri, May 3, 2019 at 9:53 AM Jason Lowe-Power  wrote:

> Thanks for the info, Rahul!
>
> Is there any way to specify a different compiler (e.g., clang) when
> building on kokoro?
>
> Thanks,
> Jason
>
> On Fri, May 3, 2019 at 9:12 AM Rahul Thakur  wrote:
>
>> Hi Giacomo, Jason,
>>
>> Sorry for late reply.
>> Re: tool chain - scons and python are available in the test environment
>> AFAIK.
>> Re: test throughput - How long does kokoro take to finish current
>> presubmit test?
>>
>> If you have much longer tests to run at periodic frequency, say once in a
>> few days, on HEAD, kokoro also has a periodic continuous build mode. Such
>> test will send out email report, serving as a pulse check for ToT.
>> Presubmit jobs will not be influenced. I can look in to periodic builds if
>> it fits for gem5 long regression use case.
>>
>> RT
>>
>> On Fri, May 3, 2019 at 6:17 AM Giacomo Travaglini <
>> giacomo.travagl...@arm.com> wrote:
>>
>>> Hi Jason,
>>>
>>> I have seen patches being under review for a long time, and IMHO adding
>>> an extra 10-30 mins is not the real bottleneck.
>>> I'd rather wait a little bit more but being sure I am not breaking
>>> anything...
>>>
>>> about ruby protocols, let me say that we (in arm) are relatively happy
>>> with the current setup:
>>>
>>> 1) Quick regressions are run on a commit base (your presubmit.sh). This
>&g

Re: [gem5-dev] Continuous integration is live!

[Rahul Thakur]

Hi Giacomo, Jason,

Sorry for late reply.
Re: tool chain - scons and python are available in the test environment
AFAIK.
Re: test throughput - How long does kokoro take to finish current presubmit
test?

If you have much longer tests to run at periodic frequency, say once in a
few days, on HEAD, kokoro also has a periodic continuous build mode. Such
test will send out email report, serving as a pulse check for ToT.
Presubmit jobs will not be influenced. I can look in to periodic builds if
it fits for gem5 long regression use case.

RT

On Fri, May 3, 2019 at 6:17 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hi Jason,
>
> I have seen patches being under review for a long time, and IMHO adding an
> extra 10-30 mins is not the real bottleneck.
> I'd rather wait a little bit more but being sure I am not breaking
> anything...
>
> about ruby protocols, let me say that we (in arm) are relatively happy
> with the current setup:
>
> 1) Quick regressions are run on a commit base (your presubmit.sh). This
> means it won't take a lot of time/computation
> 2) Long regressions (ruby protocols are tested here) are run every night
> on a batch of MERGED commits.
> Which means at a certain point we just checkout origin/HEAD and we run
> long regressions.
>
> This is the setup I would actually recommend: a sanity suite (quick) being
> run on a commit base, and more serious tests
> (long) being run periodically. If you are scared about overloading the
> framework, you can always scale down our ambition
> and run long regressions every two nights.
> Running less frequently is better than not running at all 
>
> Please let me know what you think about this; other devs are welcome to
> comment as well,
>
> Giacomo
>
>
> ------
> *From:* Jason Lowe-Power 
> *Sent:* 02 May 2019 22:59
> *To:* Giacomo Travaglini; Rahul Thakur
> *Cc:* gem5 Developer List
> *Subject:* Re: [gem5-dev] Continuous integration is live!
>
> Hi Giacomo,
>
> In tests/main.py we call scons and use the current environment defaults to
> build gem5. I don't know if the kokoro infrastructure supports other
> compilers. This might be something that Rahul can address.
>
> I'm also not sure if we can find a way to run more compilations in
> parallel on Kokoro. I'm happy to refactor the test scripts to do this.
> However, as it is, we are currently compiling at least 4 binaries mostly
> sequentially, which is making the testing take a significant amount of
> time. If we add more compilers (and more Ruby protocols), this is going to
> begin to get out of hand. It would also be good to compile .fast, .opt, and
> .debug, but I believe we're only compiling .opt right now.
>
> Cheers,
> Jason
>
> On Thu, May 2, 2019 at 5:53 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi Jason,
>
> I understand; Another thing I would like to ask:
>
> Which script is building gem5 in jenkins? Ideally it would be nice to
> build with BOTH gcc and clang (so that we avoid
> periodic "fix clang build" patches. I would also make the version
> configurable/visible from the script so that
> we can track changes in compiler support and people can compare failures
> in case they managed to build
> seamlessly on their local workspace
>
> Giacomo
> --
> *From:* Jason Lowe-Power 
> *Sent:* 26 April 2019 17:49
> *To:* Giacomo Travaglini
> *Cc:* gem5 Developer List
> *Subject:* Re: [gem5-dev] Continuous integration is live!
>
> Hi Giacomo,
>
> You *do* have permission :). Anyone can modify tests/jenkins/presubmit.cfg
> and presubmit.sh. In fact, if you look at the history of the presubmit.sh,
> it *was* running the old tests. See
> https://gem5-review.googlesource.com/c/testing/jenkins-gem5-prod/+/18028,
> for instance.
>
> The problem is that we can't distribute most of the binaries (e.g., SPEC
> binaries). We could probably upload them to a private location on the
> Google Cloud and have jenkins consume them that way, but I believe that
> will be more work than it's worth.
>
> I personally believe that putting effort into porting tests is more worth
> everyone's time than trying to get the old tests to run, but that's just
> my opinion. I'm happy to merge changes to run the old tests. I personally
> believe we should only merge tests into the verification tester which
> everyone can run locally, but I'm open to proprietary tests, especially in
> the short term if we have a plan to make them not proprietary.
>
> Cheers,
> Jason
>
> On Fri, Apr 26, 2019 at 9:36 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi Jason,
>
> It's really amazing

[gem5-dev] Change in gem5/gem5[refs/meta/config]: Review access change

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18088 )


Change subject: Review access change
..

Review access change

Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18088
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Rahul Thakur 
---
A groups
M project.config
2 files changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Rahul Thakur: Looks good to me, approved



diff --git a/groups b/groups
new file mode 100644
index 000..16dba15
--- /dev/null
+++ b/groups
@@ -0,0 +1,4 @@
+# UUID Group Name
+#
+mdb:kokoro mdb/kokoro
+mdb:kokoro-dedicated   mdb/kokoro-dedicated
diff --git a/project.config b/project.config
index 9617eda..876c893 100644
--- a/project.config
+++ b/project.config
@@ -2,3 +2,9 @@
inheritFrom = public
 [submit]
action = rebase always
+[access "refs/*"]
+   read = group mdb/kokoro
+   read = group mdb/kokoro-dedicated
+[access "refs/heads/*"]
+   label-Verified = -1..+1 group mdb/kokoro
+   label-Verified = -1..+1 group mdb/kokoro-dedicated

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18088
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: refs/meta/config
Gerrit-Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
Gerrit-Change-Number: 18088
Gerrit-PatchSet: 2
Gerrit-Owner: Rahul Thakur 
Gerrit-Assignee: Jason Lowe-Power 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Rahul Thakur 
Gerrit-MessageType: merged
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[refs/meta/config]: Review access change

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18088



Change subject: Review access change
..

Review access change

Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
---
A groups
M project.config
2 files changed, 10 insertions(+), 0 deletions(-)



diff --git a/groups b/groups
new file mode 100644
index 000..16dba15
--- /dev/null
+++ b/groups
@@ -0,0 +1,4 @@
+# UUID Group Name
+#
+mdb:kokoro mdb/kokoro
+mdb:kokoro-dedicated   mdb/kokoro-dedicated
diff --git a/project.config b/project.config
index 9617eda..876c893 100644
--- a/project.config
+++ b/project.config
@@ -2,3 +2,9 @@
inheritFrom = public
 [submit]
action = rebase always
+[access "refs/*"]
+   read = group mdb/kokoro
+   read = group mdb/kokoro-dedicated
+[access "refs/heads/*"]
+   label-Verified = -1..+1 group mdb/kokoro
+   label-Verified = -1..+1 group mdb/kokoro-dedicated

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18088
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: refs/meta/config
Gerrit-Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
Gerrit-Change-Number: 18088
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur 
Gerrit-MessageType: newchange
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: mem: Fix uncacheable write snoop flow

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/8681



Change subject: mem: Fix uncacheable write snoop flow
..

mem: Fix uncacheable write snoop flow

Earlier patches fixed handling of uncacheable IO WriteReq snoops hit in
caches by allowing in-place modification of cache block.

This patch proposes a few fixes in that:
1. Update upstream snoop packet with current snoop pkt data
2. Update mshr and cache block for WriteReq and additionally
   WriteLineReq which was previously left out.

Change-Id: Ia6fbdf53e92427f8e6ec74028b73769accc27562
---
M src/mem/cache/cache.cc
M src/mem/cache/mshr.cc
M src/mem/packet.hh
3 files changed, 49 insertions(+), 3 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 1821f18..9cdc490 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -2069,6 +2069,15 @@
 // there is a snoop hit in upper levels
 Packet snoopPkt(pkt, true, true);
 snoopPkt.setExpressSnoop();
+
+// Set data for the upstream snoop pkt from the current pkt
+// which is write transaction and carries modified data
+if ((pkt->cmd == MemCmd::WriteReq ||
+ pkt->cmd == MemCmd::WriteLineReq) && !alreadyResponded) {
+assert(pkt->req->isUncacheable());
+snoopPkt.setData(pkt->getConstPtr());
+}
+
 // the snoop packet does not need to wait any additional
 // time
 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
@@ -2211,6 +2220,18 @@
 // we already called setHasSharers above
 }

+// For uncacheable write, update the dirty data
+if (pkt->cmd == MemCmd::WriteReq || pkt->cmd ==  
MemCmd::WriteLineReq) {

+assert(pkt->req->isUncacheable());
+// write the partial line to the right part of the block
+pkt->writeDataToBlock(blk->data, blkSize);
+
+// the block is not going to end up with a cache
+// allocation, but set the flag to indicate that there are
+// sharers, also to avoid the panic below
+pkt->setHasSharers();
+}
+
 // if we are returning a writable and dirty (Modified) line,
 // we should be invalidating the line
 panic_if(!invalidate && !pkt->hasSharers(),
@@ -2356,6 +2377,19 @@
 pkt->setResponderHadWritable();
 }

+// partial line uncacheable write, update the dirty data
+if (pkt->cmd == MemCmd::WriteReq ||
+pkt->cmd == MemCmd::WriteLineReq) {
+assert(pkt->req->isUncacheable());
+// write the partial line to the right part of the
+// writeback packet
+pkt->writeDataToBlock(wb_pkt->getPtr(), blkSize);
+
+// not strictly necessary, but set the flag indicating
+// that the packet has sharers
+pkt->setHasSharers();
+}
+
 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr(),
false, false);
 }
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 493b7f0..5af4f6a 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -425,8 +425,19 @@
 // the latter case the cache is responsible for deleting both
 // the packet and the request as part of handling the deferred
 // snoop.
-PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
-new Packet(new Request(*pkt->req), pkt->cmd, blkSize, pkt->id);
+PacketPtr cp_pkt = nullptr;
+if (will_respond) {
+cp_pkt = new Packet(pkt, true, true);
+//  Update the data if request is write carrying updated data
+if (pkt->cmd == MemCmd::WriteReq ||
+pkt->cmd == MemCmd::WriteLineReq) {
+assert(pkt->req->isUncacheable());
+cp_pkt->allocate();
+cp_pkt->setData(pkt->getConstPtr());
+}
+} else {
+cp_pkt = new Packet(new Request(*pkt->req), pkt->cmd, blkSize);
+}

 if (will_respond) {
 // we are the ordering point, and will consequently
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 66625b3..1f481db 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -530,7 +530,8 @@
 // look at the hasSharers flag (if not set, the response is to
 // be considered writable)
 assert(isRequest());
-return cmd.needsWritable();
+// ignore the needsWritable flag if the packet is uncacheable
+return cmd.needsWritable() && !req->isUncacheable();
 }
 bool needsResponse() co

[gem5-dev] clang-format tool for C++ code auto-formatting

[Rahul Thakur]

Hi all,

Re:
misc: Add .clang-format for C++ autoformat tools
https://gem5-review.googlesource.com/#/c/3382/

Gabe uploaded this change set which is an internal version of .clang-format
configuration which IMO formats closest to gem5 style guide definitions.

I have happily used clang-format for ~2 years now (still learning) and it
has saved me time developing C++ code and humiliating code reviews.
So I start this discussion, hopefully we can mutually agree if and how we
can adopt clang-format for gem5 project.

It seems folks agree that there is considerable advantage of using
clang-format for C++ code auto-formatting but there exist some specific C++
code in gem5 that is incompatible. I list a few known issues and possible
remedy.
1) BitUnion or any other macros:
The ideal solution is to implement support for macro in clang-format but
IMO this is quite complicated and unlikely to happen without significantly
changing clang-format tool itself.
A simple work around for this issue is to use:
https://clang.llvm.org/docs/ClangFormatStyleOptions.html#disabling-formatting-on-a-piece-of-code

2) switch case label indentation:
Since switch case indentation has many observed rules depending on
different SW project, we can define the gem5 style guide to either keep
case label indentation same as switch statement or 4 spaces indented. Both
these are programmable in clang-format configuration via IndentCaseLabels
parameter.

3) clang-format doesn't check "naming" convention:
This is out of scope of clang-format
Internally at Google we use cpplint
 and gem5 style
checker can incorporate checking naming convention.

4) Accepting on a certain .clang-format configuration for gem5 and then
revising the gem5 code base:
e.g. following a specific rule on how constructor initialization list is
formatted and revising existing code base to comply with agreed upon
.clang-format configuration

Thanks,
Rahul.
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2261 )


Change subject: arm, kvm: enable running 32-bit Guest under ARM KVM64
..

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Reviewed-on: https://gem5-review.googlesource.com/2261
Maintainer: Rahul Thakur <rjtha...@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 10 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Rahul Thakur: Looks good to me, approved



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 08b9011..67e2e46 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -268,7 +268,13 @@
 for (int i = 0; i < NUM_XREGS; ++i) {
 const auto value(getOneRegU64(kvmXReg(i)));
 DPRINTF(KvmContext, "  X%i := 0x%x\n", i, value);
-tc->setIntReg(INTREG_X0 + i, value);
+// KVM64 returns registers in 64-bit layout. If we are in aarch32
+// mode, we need to map these to banked ARM32 registers.
+if (inAArch64(tc)) {
+tc->setIntReg(INTREG_X0 + i, value);
+} else {
+tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
+}
 }

 for (const auto  : intRegMap) {
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index e511fd6..e25112c 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -79,6 +79,9 @@
 memset(_config, 0, sizeof(target_config));

 vm.kvmArmPreferredTarget(target_config);
+if (!((ArmSystem *)system)->highestELIs64()) {
+target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
+}
 kvmArmVCpuInit(target_config);
 }


--
To view, visit https://gem5-review.googlesource.com/2261
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Gerrit-Change-Number: 2261
Gerrit-PatchSet: 4
Gerrit-Owner: Rahul Thakur <rjtha...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Rahul Thakur <rjtha...@google.com>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2261

to look at the new patch set (#3).

Change subject: arm, kvm: enable running 32-bit Guest under ARM KVM64
..

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 10 insertions(+), 1 deletion(-)


--
To view, visit https://gem5-review.googlesource.com/2261
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Gerrit-Change-Number: 2261
Gerrit-PatchSet: 3
Gerrit-Owner: Rahul Thakur <rjtha...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Rahul Thakur <rjtha...@google.com>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, kvm: fix saving/restoring conditional flags in ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2260 )


Change subject: arm, kvm: fix saving/restoring conditional flags in ARM  
KVM64

..

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Reviewed-on: https://gem5-review.googlesource.com/2260
Reviewed-by: Rahul Thakur <rjtha...@google.com>
Maintainer: Rahul Thakur <rjtha...@google.com>
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 28 insertions(+), 3 deletions(-)

Approvals:
  Rahul Thakur: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index e8a77b0..08b9011 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -102,7 +102,6 @@
 };

 const std::vector ArmV8KvmCPU::miscRegMap = {
-MiscRegInfo(INT_REG(regs.pstate), MISCREG_CPSR, "PSTATE"),
 MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]),  
MISCREG_SPSR_EL1, "SPSR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]),  
MISCREG_SPSR_ABT, "SPSR(ABT)"),

@@ -135,6 +134,8 @@

 for (const auto  : intRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
+
+inform("  %s: %s\n", "PSTATE",  
getAndFormatOneReg(INT_REG(regs.pstate)));


 for (const auto  : miscRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
@@ -188,6 +189,20 @@
 ArmV8KvmCPU::updateKvmState()
 {
 DPRINTF(KvmContext, "In updateKvmState():\n");
+
+// update pstate register state
+CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
+cpsr.nz = tc->readCCReg(CCREG_NZ);
+cpsr.c = tc->readCCReg(CCREG_C);
+cpsr.v = tc->readCCReg(CCREG_V);
+if (cpsr.width) {
+cpsr.ge = tc->readCCReg(CCREG_GE);
+} else {
+cpsr.ge = 0;
+}
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr);
+setOneReg(INT_REG(regs.pstate), cpsr);
+
 for (const auto  : miscRegMap) {
 const uint64_t value(tc->readMiscReg(ri.idx));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
@@ -231,7 +246,18 @@
 {
 DPRINTF(KvmContext, "In updateThreadContext():\n");

-// Update core misc regs first as they (particularly PSTATE/CPSR)
+// Update pstate thread context
+const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr);
+tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr);
+tc->setCCReg(CCREG_NZ, cpsr.nz);
+tc->setCCReg(CCREG_C, cpsr.c);
+tc->setCCReg(CCREG_V, cpsr.v);
+if (cpsr.width) {
+tc->setCCReg(CCREG_GE, cpsr.ge);
+}
+
+// Update core misc regs first as they
 // affect how other registers are mapped.
 for (const auto  : miscRegMap) {
 const auto value(getOneRegU64(ri.kvm));
@@ -266,7 +292,6 @@
 tc->setMiscRegNoEffect(ri.idx, value);
 }

-const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
 PCState pc(getOneRegU64(INT_REG(regs.pc)));
 pc.aarch64(inAArch64(tc));
 pc.thumb(cpsr.t);

--
To view, visit https://gem5-review.googlesource.com/2260
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Gerrit-Change-Number: 2260
Gerrit-PatchSet: 3
Gerrit-Owner: Rahul Thakur <rjtha...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Rahul Thakur <rjtha...@google.com>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, kvm: fix saving/restoring conditional flags in ARM KVM64

[Rahul Thakur (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2260

to look at the new patch set (#2).

Change subject: arm, kvm: fix saving/restoring conditional flags in ARM  
KVM64

..

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 28 insertions(+), 3 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/2260
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Gerrit-Change-Number: 2260
Gerrit-PatchSet: 2
Gerrit-Owner: Rahul Thakur <rjtha...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Rahul Thakur <rjtha...@google.com>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, kvm: fix saving/restoring conditional flags in ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/2260



Change subject: arm, kvm: fix saving/restoring conditional flags in ARM  
KVM64

..

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 29 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index e8a77b0..5145fba 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -102,7 +102,6 @@
 };

 const std::vector ArmV8KvmCPU::miscRegMap = {
-MiscRegInfo(INT_REG(regs.pstate), MISCREG_CPSR, "PSTATE"),
 MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]),  
MISCREG_SPSR_EL1, "SPSR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]),  
MISCREG_SPSR_ABT, "SPSR(ABT)"),

@@ -135,6 +134,8 @@

 for (const auto  : intRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
+
+inform("  %s: %s\n", "PSTATE",  
getAndFormatOneReg(INT_REG(regs.pstate)));


 for (const auto  : miscRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
@@ -188,6 +189,20 @@
 ArmV8KvmCPU::updateKvmState()
 {
 DPRINTF(KvmContext, "In updateKvmState():\n");
+
+// update pstate register state
+CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
+cpsr.nz = tc->readCCReg(CCREG_NZ);
+cpsr.c = tc->readCCReg(CCREG_C);
+cpsr.v = tc->readCCReg(CCREG_V);
+if (cpsr.width) {
+cpsr.ge = tc->readCCReg(CCREG_GE);
+} else {
+cpsr.ge = 0;
+}
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr);
+setOneReg(INT_REG(regs.pstate), cpsr);
+
 for (const auto  : miscRegMap) {
 const uint64_t value(tc->readMiscReg(ri.idx));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
@@ -231,7 +246,19 @@
 {
 DPRINTF(KvmContext, "In updateThreadContext():\n");

-// Update core misc regs first as they (particularly PSTATE/CPSR)
+// Update pstate thread context
+const auto cpsr_value(getOneRegU64(INT_REG(regs.pstate)));
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr_value);
+tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr_value);
+const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
+tc->setCCReg(CCREG_NZ, cpsr.nz);
+tc->setCCReg(CCREG_C, cpsr.c);
+tc->setCCReg(CCREG_V, cpsr.v);
+if (cpsr.width) {
+tc->setCCReg(CCREG_GE, cpsr.ge);
+}
+
+// Update core misc regs first as they
 // affect how other registers are mapped.
 for (const auto  : miscRegMap) {
 const auto value(getOneRegU64(ri.kvm));
@@ -266,7 +293,6 @@
 tc->setMiscRegNoEffect(ri.idx, value);
 }

-const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
 PCState pc(getOneRegU64(INT_REG(regs.pc)));
 pc.aarch64(inAArch64(tc));
 pc.thumb(cpsr.t);

--
To view, visit https://gem5-review.googlesource.com/2260
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Gerrit-Change-Number: 2260
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur <rjtha...@google.com>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in public/gem5[master]: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/2261



Change subject: arm, kvm: enable running 32-bit Guest under ARM KVM64
..

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 5145fba..af99cbe 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -269,7 +269,13 @@
 for (int i = 0; i < NUM_XREGS; ++i) {
 const auto value(getOneRegU64(kvmXReg(i)));
 DPRINTF(KvmContext, "  X%i := 0x%x\n", i, value);
-tc->setIntReg(INTREG_X0 + i, value);
+// KVM64 returns registers in 64-bit layout. If we are in aarch32
+// mode, we need to map these to banked ARM32 registers.
+if (inAArch64(tc)) {
+tc->setIntReg(INTREG_X0 + i, value);
+} else {
+tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
+}
 }

 for (const auto  : intRegMap) {
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index e511fd6..e25112c 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -79,6 +79,9 @@
 memset(_config, 0, sizeof(target_config));

 vm.kvmArmPreferredTarget(target_config);
+if (!((ArmSystem *)system)->highestELIs64()) {
+target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
+}
 kvmArmVCpuInit(target_config);
 }


--
To view, visit https://gem5-review.googlesource.com/2261
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Gerrit-Change-Number: 2261
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur <rjtha...@google.com>
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3817: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3817/
---

(Updated Feb. 25, 2017, 1:24 a.m.)


Review request for Default.


Summary (updated)
-

arm, kvm: enable running 32-bit Guest under ARM KVM64


Repository: gem5


Description (updated)
---

Changeset 11874:85949465c50b
---
arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I20d138276f6cc5aff7a855988c2e30dccef5affc


Diffs (updated)
-

  src/arch/arm/kvm/armv8_cpu.cc ba90ffa751b6 
  src/arch/arm/kvm/base_cpu.cc ba90ffa751b6 

Diff: http://reviews.gem5.org/r/3817/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3816: commit 70469eba20cdcf091d66cf2ef463318203c7cc71

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3816/
---

(Updated Feb. 23, 2017, 7:17 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11873:f1d504c8ede4
---
commit 70469eba20cdcf091d66cf2ef463318203c7cc71
Author: Slava Malyugin <slav...@google.com>
Date:   Wed Dec 2 19:01:12 2015 -0800

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I9f0a685f8667c581cdef7d8c234604a3135d9402


Diffs (updated)
-

  src/arch/arm/kvm/armv8_cpu.cc ba90ffa751b6 

Diff: http://reviews.gem5.org/r/3816/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3817: commit 2873a1ea3720e638ba1bb4f7c69b43b98bc4d72a

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3817/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11874:ceed3b2698f6
---
commit 2873a1ea3720e638ba1bb4f7c69b43b98bc4d72a
Author: Slava Malyugin <slav...@google.com>
Date:   Wed Dec 2 19:41:24 2015 -0800

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

3) Set R15 when PC is changed

4) Map MISCREG_SPSR_EL1 to MISCREG_SPSR_SVC in 32-bit mode.

TEST: built build/ARM/gem5.opt on ARM and x86
  tested with KVM64 on Cortex-A57, restored KVM checkpoint in atomic 
mode
BUG: none

Change-Id: I20d138276f6cc5aff7a855988c2e30dccef5affc


Diffs
-

  src/arch/arm/kvm/armv8_cpu.cc ba90ffa751b6 
  src/arch/arm/kvm/base_cpu.cc ba90ffa751b6 

Diff: http://reviews.gem5.org/r/3817/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3816: commit 70469eba20cdcf091d66cf2ef463318203c7cc71

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3816/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11873:6069fbdacba5
---
commit 70469eba20cdcf091d66cf2ef463318203c7cc71
Author: Slava Malyugin <slav...@google.com>
Date:   Wed Dec 2 19:01:12 2015 -0800

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I9f0a685f8667c581cdef7d8c234604a3135d9402


Diffs
-

  src/arch/arm/kvm/armv8_cpu.cc ba90ffa751b6 

Diff: http://reviews.gem5.org/r/3816/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in gem5: mem: Refactor CommMonitor stats, add basic at...

[Rahul Thakur]

changeset 220375a47eeb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=220375a47eeb
description:
mem: Refactor CommMonitor stats, add basic atomic mode stats

Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>

diffstat:

 src/mem/comm_monitor.cc |  236 
 src/mem/comm_monitor.hh |   24 +++-
 2 files changed, 134 insertions(+), 126 deletions(-)

diffs (truncated from 358 to 300 lines):

diff -r 4f04a6593119 -r 220375a47eeb src/mem/comm_monitor.cc
--- a/src/mem/comm_monitor.cc   Fri Jan 27 14:58:15 2017 -0600
+++ b/src/mem/comm_monitor.cc   Fri Jan 27 14:58:16 2017 -0600
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2012-2013, 2015 ARM Limited
- * All rights reserved
+ * Copyright (c) 2016 Google Inc.
+ * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
  * not be construed as granting a license to any other intellectual
@@ -36,6 +37,7 @@
  *
  * Authors: Thomas Grass
  *  Andreas Hansson
+ *  Rahul Thakur
  */
 
 #include "mem/comm_monitor.hh"
@@ -51,8 +53,6 @@
   samplePeriodicEvent(this),
   samplePeriodTicks(params->sample_period),
   samplePeriod(params->sample_period / SimClock::Float::s),
-  readAddrMask(params->read_addr_mask),
-  writeAddrMask(params->write_addr_mask),
   stats(params)
 {
 DPRINTF(CommMonitor,
@@ -113,13 +113,119 @@
 slavePort.sendFunctionalSnoop(pkt);
 }
 
+void
+CommMonitor::MonitorStats::updateReqStats(
+const ProbePoints::PacketInfo& pkt_info, bool is_atomic,
+bool expects_response)
+{
+if (pkt_info.cmd.isRead()) {
+// Increment number of observed read transactions
+if (!disableTransactionHists)
+++readTrans;
+
+// Get sample of burst length
+if (!disableBurstLengthHists)
+readBurstLengthHist.sample(pkt_info.size);
+
+// Sample the masked address
+if (!disableAddrDists)
+readAddrDist.sample(pkt_info.addr & readAddrMask);
+
+if (!disableITTDists) {
+// Sample value of read-read inter transaction time
+if (timeOfLastRead != 0)
+ittReadRead.sample(curTick() - timeOfLastRead);
+timeOfLastRead = curTick();
+
+// Sample value of req-req inter transaction time
+if (timeOfLastReq != 0)
+ittReqReq.sample(curTick() - timeOfLastReq);
+timeOfLastReq = curTick();
+}
+if (!is_atomic && !disableOutstandingHists && expects_response)
+++outstandingReadReqs;
+
+} else if (pkt_info.cmd.isWrite()) {
+// Same as for reads
+if (!disableTransactionHists)
+++writeTrans;
+
+if (!disableBurstLengthHists)
+writeBurstLengthHist.sample(pkt_info.size);
+
+// Update the bandwidth stats on the request
+if (!disableBandwidthHists) {
+writtenBytes += pkt_info.size;
+totalWrittenBytes += pkt_info.size;
+}
+
+// Sample the masked write address
+if (!disableAddrDists)
+writeAddrDist.sample(pkt_info.addr & writeAddrMask);
+
+if (!disableITTDists) {
+// Sample value of write-to-write inter transaction time
+if (timeOfLastWrite != 0)
+ittWriteWrite.sample(curTick() - timeOfLastWrite);
+timeOfLastWrite = curTick();
+
+// Sample value of req-to-req inter transaction time
+if (timeOfLastReq != 0)
+ittReqReq.sample(curTick() - timeOfLastReq);
+timeOfLastReq = curTick();
+}
+
+if (!is_atomic && !disableOutstandingHists && expects_response)
+++outstandingWriteReqs;
+}
+}
+
+void
+CommMonitor::MonitorStats::updateRespStats(
+const ProbePoints::PacketInfo& pkt_info, Tick latency, bool is_atomic)
+{
+if (pkt_info.cmd.isRead()) {
+// Decrement number of outstanding read requests
+if (!is_atomic && !disableOutstandingHists) {
+assert(outstandingReadReqs != 0);
+--outstandingReadReqs;
+}
+
+if (!disableLatencyHists)
+readLatencyHist.sample(latency);
+
+// Update the bandwidth stats based on responses for reads
+if (!disableBandwidthHists) {
+readBytes += pkt_info.size;
+totalReadBytes += pkt_info.size;
+}
+
+} else if (pkt_info.cmd.isWrite()) {
+// Decrement number of outstanding write requests
+if (!is_atomic && !disableOutstandingHists) {
+assert(outstandingWriteReqs != 0);
+--outstandingWriteReqs;
+}
+
+if (!disableLatencyHists)
+writeLatencyHist.sample(latency);
+}
+}
+
 Tick
 CommMonitor::recvAtomic(PacketPtr pkt)
 {
+const bool expects_response(pkt->

[gem5-dev] changeset in gem5: mem: Add memory footprint probe

[Rahul Thakur]

changeset 4f04a6593119 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4f04a6593119
description:
mem: Add memory footprint probe

Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>

diffstat:

 COPYING |1 +
 configs/dram/lat_mem_rd.py  |1 +
 src/mem/probes/MemFootprintProbe.py |   48 +
 src/mem/probes/SConscript   |3 +
 src/mem/probes/mem_footprint.cc |  132 
 src/mem/probes/mem_footprint.hh |   97 ++
 6 files changed, 282 insertions(+), 0 deletions(-)

diffs (truncated from 321 to 300 lines):

diff -r be62996c95d1 -r 4f04a6593119 COPYING
--- a/COPYING   Fri Jan 27 12:40:01 2017 +
+++ b/COPYING   Fri Jan 27 14:58:15 2017 -0600
@@ -45,3 +45,4 @@
 Copyright (c) 1993-1994 Christopher G. Demetriou
 Copyright (c) 1997-2002 Makoto Matsumoto and Takuji Nishimura
 Copyright (c) 1998,2001 Manuel Bouyer.
+Copyright (c) 2016 Google Inc.
diff -r be62996c95d1 -r 4f04a6593119 configs/dram/lat_mem_rd.py
--- a/configs/dram/lat_mem_rd.pyFri Jan 27 12:40:01 2017 +
+++ b/configs/dram/lat_mem_rd.pyFri Jan 27 14:58:15 2017 -0600
@@ -252,6 +252,7 @@
 
 # add a communication monitor
 system.monitor = CommMonitor()
+system.monitor.footprint = MemFootprintProbe()
 
 # connect the traffic generator to the system
 system.tgen.port = system.monitor.slave
diff -r be62996c95d1 -r 4f04a6593119 src/mem/probes/MemFootprintProbe.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/src/mem/probes/MemFootprintProbe.py   Fri Jan 27 14:58:15 2017 -0600
@@ -0,0 +1,48 @@
+# Copyright (c) 2016 Google Inc.
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and
+# shall not be construed as granting a license to any other
+# intellectual property including but not limited to intellectual
+# property relating to a hardware implementation of the
+# functionality of the software licensed hereunder.  You may use the
+# software subject to the license terms below provided that you
+# ensure that this notice is replicated unmodified and in its
+# entirety in all distributions of the software, modified or
+# unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Rahul Thakur
+
+from m5.params import *
+from m5.proxy import *
+from BaseMemProbe import BaseMemProbe
+
+class MemFootprintProbe(BaseMemProbe):
+type = "MemFootprintProbe"
+cxx_header = "mem/probes/mem_footprint.hh"
+system = Param.System(Parent.any,
+  "System pointer to get cache line and mem size")
+page_size = Param.Unsigned(4096, "Page size for page-level footprint")
diff -r be62996c95d1 -r 4f04a6593119 src/mem/probes/SConscript
--- a/src/mem/probes/SConscript Fri Jan 27 12:40:01 2017 +
+++ b/src/mem/probes/SConscript Fri Jan 27 14:58:15 2017 -0600
@@ -45,6 +45,9 @@
 SimObject('StackDistProbe.py')
 Source('stack_dist.cc')
 
+SimObject('MemFootprintProbe.py')
+Source('mem_footprint.cc')
+
 # Packet tracing requires protobuf support
 if env['HAVE_PROTOBUF']:
 SimObject('MemTraceProbe.py')
diff -r be62996c95d1 -r 4f04a6593119 src/mem/probes/mem_footprint.cc
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/src/mem/probes/mem_footprint.cc   Fri Jan 27 14:58:15 2017 -0600
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2016 Google Inc.
+ * All rights reserved.
+ *
+ * The license below

[gem5-dev] Commit changes

[Rahul Thakur]

Hi,

Requesting folks with commit access to please commit these 2 reviewed
changes:
http://reviews.gem5.org/r/3708/
http://reviews.gem5.org/r/3740/

Thanks,
Rahul.
___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3740: commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3740/
---

(Updated Nov. 29, 2016, 11:54 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11708:02ce0fdd4929
---
commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60
Author: Rahul Thakur <rjtha...@google.com>
Date:   Thu Oct 27 20:36:16 2016 -0700

mem: Refactor CommMonitor stats, add basic atomic mode stats

Change-Id: I978f1155873b3882e16d9cd74e86400efd9c5e3b


Diffs (updated)
-

  src/mem/comm_monitor.hh 1d085f66c4ca 
  src/mem/comm_monitor.cc 1d085f66c4ca 

Diff: http://reviews.gem5.org/r/3740/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3740: commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3740/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11708:33c0089caa50
---
commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60
Author: Rahul Thakur <rjtha...@google.com>
Date:   Thu Oct 27 20:36:16 2016 -0700

mem: Refactor CommMonitor stats, add basic atomic mode stats

Change-Id: I978f1155873b3882e16d9cd74e86400efd9c5e3b


Diffs
-

  src/mem/comm_monitor.hh 1d085f66c4ca 
  src/mem/comm_monitor.cc 1d085f66c4ca 

Diff: http://reviews.gem5.org/r/3740/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3708: commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3

[Rahul Thakur]

> On Nov. 17, 2016, 11:40 a.m., Andreas Sandberg wrote:
> > src/mem/probes/mem_footprint.cc, line 87
> > <http://reviews.gem5.org/r/3708/diff/1/?file=63616#file63616line87>
> >
> > You could actually do this instead of using a custom class:
> > 
> > ```
> > registerResetCallback(new MakeCallback<MemFootprintProbe, 
> > ::statReset>(this))
> > ```

Thanks for review!


- Rahul


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3708/#review9099
-------


On Nov. 17, 2016, 8:02 p.m., Rahul Thakur wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3708/
> ---
> 
> (Updated Nov. 17, 2016, 8:02 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11705:f55d4a414fa1
> ---
> commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3
> Author: Rahul Thakur <rjtha...@google.com>
> Date:   Thu Oct 27 17:44:40 2016 -0700
> 
> mem: Add memory footprint probe
> 
> Change-Id: I0fba8995edd63df4ef49969347be6d2aefceca9f
> 
> 
> Diffs
> -
> 
>   COPYING c38fcdaa5fe5 
>   configs/dram/lat_mem_rd.py c38fcdaa5fe5 
>   src/mem/probes/MemFootprintProbe.py PRE-CREATION 
>   src/mem/probes/SConscript c38fcdaa5fe5 
>   src/mem/probes/mem_footprint.hh PRE-CREATION 
>   src/mem/probes/mem_footprint.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3708/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Rahul Thakur
> 
>

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3708: commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3708/#review9106
---

Ship it!


Ship It!

- Rahul Thakur


On Nov. 17, 2016, 8:02 p.m., Rahul Thakur wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3708/
> ---
> 
> (Updated Nov. 17, 2016, 8:02 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11705:f55d4a414fa1
> ---
> commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3
> Author: Rahul Thakur <rjtha...@google.com>
> Date:   Thu Oct 27 17:44:40 2016 -0700
> 
> mem: Add memory footprint probe
> 
> Change-Id: I0fba8995edd63df4ef49969347be6d2aefceca9f
> 
> 
> Diffs
> -
> 
>   COPYING c38fcdaa5fe5 
>   configs/dram/lat_mem_rd.py c38fcdaa5fe5 
>   src/mem/probes/MemFootprintProbe.py PRE-CREATION 
>   src/mem/probes/SConscript c38fcdaa5fe5 
>   src/mem/probes/mem_footprint.hh PRE-CREATION 
>   src/mem/probes/mem_footprint.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3708/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Rahul Thakur
> 
>

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3708: commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3708/
---

(Updated Nov. 17, 2016, 8:02 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11705:f55d4a414fa1
---
commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3
Author: Rahul Thakur <rjtha...@google.com>
Date:   Thu Oct 27 17:44:40 2016 -0700

mem: Add memory footprint probe

Change-Id: I0fba8995edd63df4ef49969347be6d2aefceca9f


Diffs (updated)
-

  COPYING c38fcdaa5fe5 
  configs/dram/lat_mem_rd.py c38fcdaa5fe5 
  src/mem/probes/MemFootprintProbe.py PRE-CREATION 
  src/mem/probes/SConscript c38fcdaa5fe5 
  src/mem/probes/mem_footprint.hh PRE-CREATION 
  src/mem/probes/mem_footprint.cc PRE-CREATION 

Diff: http://reviews.gem5.org/r/3708/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3708: commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3

[Rahul Thakur]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3708/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11705:df194a470063
---
commit 752c67b134f4cb0b7ca68a907c39a5a482de30b3
Author: Rahul Thakur <rjtha...@google.com>
Date:   Thu Oct 27 17:44:40 2016 -0700

mem: Add memory footprint probe

Change-Id: I0fba8995edd63df4ef49969347be6d2aefceca9f


Diffs
-

  src/mem/probes/mem_footprint.hh PRE-CREATION 
  src/mem/probes/mem_footprint.cc PRE-CREATION 
  COPYING c38fcdaa5fe5 
  configs/dram/lat_mem_rd.py c38fcdaa5fe5 
  src/mem/probes/MemFootprintProbe.py PRE-CREATION 
  src/mem/probes/SConscript c38fcdaa5fe5 

Diff: http://reviews.gem5.org/r/3708/diff/


Testing
---


Thanks,

Rahul Thakur

___
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] gem5-dev Digest, Vol 95, Issue 15

[Rahul Thakur]

Steve is doing some x86 locked memory access implementation in Timing mode.
I will check how he is doing it. Do you follow gem5-dev?

On Sun, Mar 15, 2015 at 9:00 AM, gem5-dev-requ...@gem5.org wrote:

 Send gem5-dev mailing list submissions to
 gem5-dev@gem5.org

 To subscribe or unsubscribe via the World Wide Web, visit
 http://m5sim.org/mailman/listinfo/gem5-dev
 or, via email, send a message with subject or body 'help' to
 gem5-dev-requ...@gem5.org

 You can reach the person managing the list at
 gem5-dev-ow...@gem5.org

 When replying, please edit your Subject line so it is more specific
 than Re: Contents of gem5-dev digest...


 Today's Topics:

1. Review Request 2688: misc: quote args in echoed command   line
   (Steve Reinhardt)
2. Review Request 2689: config: expand '~' and '~user' inpaths
   (Steve Reinhardt)
3. Review Request 2690: mem: rename Locked/LOCKED to
   LockedRMW/LOCKED_RMW (Steve Reinhardt)
4. Review Request 2691: mem: implement x86 locked accesses in
   timing-mode classic cache (Steve Reinhardt)


 --

 Message: 1
 Date: Sat, 14 Mar 2015 17:16:11 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2688: misc: quote args in echoed
 command line
 Message-ID: 20150314171611.27087.24...@daystrom2.eecs.umich.edu
 Content-Type: text/plain; charset=utf-8


 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2688/
 ---

 Review request for Default.


 Repository: gem5


 Description
 ---

 Changeset 10742:cbbf130c862c
 ---
 misc: quote args in echoed command line

 Currently if there are shell special characters in a
 command-line argument, you can't copy and paste the
 echoed command line onto a shell prompt because the
 characters aren't quoted properly.  This patch fixes
 that problem.


 Diffs
 -

   src/python/m5/main.py 655ff3f6352d7aa4021f8840b68698b22806

 Diff: http://reviews.gem5.org/r/2688/diff/


 Testing
 ---


 Thanks,

 Steve Reinhardt



 --

 Message: 2
 Date: Sat, 14 Mar 2015 17:16:59 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2689: config: expand '~' and
 '~user' in  paths
 Message-ID: 20150314171659.26849.41...@daystrom2.eecs.umich.edu
 Content-Type: text/plain; charset=utf-8


 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2689/
 ---

 Review request for Default.


 Repository: gem5


 Description
 ---

 Changeset 10743:a840cc9ada64
 ---
 config: expand '~' and '~user' in paths


 Diffs
 -

   configs/common/SysPaths.py 655ff3f6352d7aa4021f8840b68698b22806

 Diff: http://reviews.gem5.org/r/2689/diff/


 Testing
 ---


 Thanks,

 Steve Reinhardt



 --

 Message: 3
 Date: Sat, 14 Mar 2015 17:17:30 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2690: mem: rename Locked/LOCKED to
 LockedRMW/LOCKED_RMW
 Message-ID: 20150314171730.26849.54...@daystrom2.eecs.umich.edu
 Content-Type: text/plain; charset=utf-8


 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2690/
 ---

 Review request for Default.


 Repository: gem5


 Description
 ---

 Changeset 10744:a07d262a71c0
 ---
 mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW

 Makes x86-style locked operations even more distinct from
 LLSC operations.  Using locked by itself should be
 obviously ambiguous now.


 Diffs
 -

   src/arch/x86/isa/microops/ldstop.isa
 655ff3f6352d7aa4021f8840b68698b22806
   src/cpu/simple/atomic.cc 655ff3f6352d7aa4021f8840b68698b22806
   src/mem/request.hh 655ff3f6352d7aa4021f8840b68698b22806
   src/mem/ruby/system/Sequencer.cc 655ff3f6352d7aa4021f8840b68698b22806

 Diff: http://reviews.gem5.org/r/2690/diff/


 Testing
 ---


 Thanks,

 Steve Reinhardt



 --

 Message: 4
 Date: Sat, 14 Mar 2015 17:19:01 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2691: mem: implement x86 locked
 accesses in timing-mode classic cache
 Message-ID: 

Re: [gem5-dev] gem5-dev Digest, Vol 95, Issue 15

[Rahul Thakur]

My apologies for the earlier unintended spam (and this one too).
I was looking into x86 RMW lock support in gem5 classic memory and Steve
seems to be 2 steps ahead on the problem.

On Sun, Mar 15, 2015 at 9:43 PM, Rahul Thakur rjtha...@google.com wrote:

 Steve is doing some x86 locked memory access implementation in Timing mode.
 I will check how he is doing it. Do you follow gem5-dev?

 On Sun, Mar 15, 2015 at 9:00 AM, gem5-dev-requ...@gem5.org wrote:

 Send gem5-dev mailing list submissions to
 gem5-dev@gem5.org

 To subscribe or unsubscribe via the World Wide Web, visit
 http://m5sim.org/mailman/listinfo/gem5-dev
 or, via email, send a message with subject or body 'help' to
 gem5-dev-requ...@gem5.org

 You can reach the person managing the list at
 gem5-dev-ow...@gem5.org

 When replying, please edit your Subject line so it is more specific
 than Re: Contents of gem5-dev digest...


 Today's Topics:

1. Review Request 2688: misc: quote args in echoed command   line
   (Steve Reinhardt)
2. Review Request 2689: config: expand '~' and '~user' inpaths
   (Steve Reinhardt)
3. Review Request 2690: mem: rename Locked/LOCKED to
   LockedRMW/LOCKED_RMW (Steve Reinhardt)
4. Review Request 2691: mem: implement x86 locked accesses in
   timing-mode classic cache (Steve Reinhardt)


 --

 Message: 1
 Date: Sat, 14 Mar 2015 17:16:11 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2688: misc: quote args in echoed
 command line
 Message-ID: 20150314171611.27087.24...@daystrom2.eecs.umich.edu
 Content-Type: text/plain; charset=utf-8


 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2688/
 ---

 Review request for Default.


 Repository: gem5


 Description
 ---

 Changeset 10742:cbbf130c862c
 ---
 misc: quote args in echoed command line

 Currently if there are shell special characters in a
 command-line argument, you can't copy and paste the
 echoed command line onto a shell prompt because the
 characters aren't quoted properly.  This patch fixes
 that problem.


 Diffs
 -

   src/python/m5/main.py 655ff3f6352d7aa4021f8840b68698b22806

 Diff: http://reviews.gem5.org/r/2688/diff/


 Testing
 ---


 Thanks,

 Steve Reinhardt



 --

 Message: 2
 Date: Sat, 14 Mar 2015 17:16:59 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2689: config: expand '~' and
 '~user' in  paths
 Message-ID: 20150314171659.26849.41...@daystrom2.eecs.umich.edu
 Content-Type: text/plain; charset=utf-8


 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2689/
 ---

 Review request for Default.


 Repository: gem5


 Description
 ---

 Changeset 10743:a840cc9ada64
 ---
 config: expand '~' and '~user' in paths


 Diffs
 -

   configs/common/SysPaths.py 655ff3f6352d7aa4021f8840b68698b22806

 Diff: http://reviews.gem5.org/r/2689/diff/


 Testing
 ---


 Thanks,

 Steve Reinhardt



 --

 Message: 3
 Date: Sat, 14 Mar 2015 17:17:30 -
 From: Steve Reinhardt ste...@gmail.com
 To: Steve Reinhardt ste...@gmail.com, Default
 gem5-dev@gem5.org
 Subject: [gem5-dev] Review Request 2690: mem: rename Locked/LOCKED to
 LockedRMW/LOCKED_RMW
 Message-ID: 20150314171730.26849.54...@daystrom2.eecs.umich.edu
 Content-Type: text/plain; charset=utf-8


 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2690/
 ---

 Review request for Default.


 Repository: gem5


 Description
 ---

 Changeset 10744:a07d262a71c0
 ---
 mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW

 Makes x86-style locked operations even more distinct from
 LLSC operations.  Using locked by itself should be
 obviously ambiguous now.


 Diffs
 -

   src/arch/x86/isa/microops/ldstop.isa
 655ff3f6352d7aa4021f8840b68698b22806
   src/cpu/simple/atomic.cc 655ff3f6352d7aa4021f8840b68698b22806
   src/mem/request.hh 655ff3f6352d7aa4021f8840b68698b22806
   src/mem/ruby/system/Sequencer.cc
 655ff3f6352d7aa4021f8840b68698b22806

 Diff: http://reviews.gem5.org/r/2690/diff/


 Testing
 ---


 Thanks,

 Steve Reinhardt



 --

 Message: 4
 Date: Sat, 14 Mar