[gem5-dev] Change in gem5/gem5[master]: tests: Increase jenkins test timeout to 4 hours.

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23463 )


Change subject: tests: Increase jenkins test timeout to 4 hours.
..

tests: Increase jenkins test timeout to 4 hours.

Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23463
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Giacomo Travaglini 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/jenkins/presubmit.cfg
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/jenkins/presubmit.cfg b/tests/jenkins/presubmit.cfg
index 742a6fc..6c9296e 100644
--- a/tests/jenkins/presubmit.cfg
+++ b/tests/jenkins/presubmit.cfg
@@ -2,3 +2,5 @@

 # Location of the continuous batch script in repository.
 build_file: "jenkins-gem5-prod/tests/jenkins/presubmit.sh"
+
+timeout_mins: 240

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Gerrit-Change-Number: 23463
Gerrit-PatchSet: 3
Gerrit-Owner: Rahul Thakur 
Gerrit-Assignee: Bobby Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Rahul Thakur 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby Bruce 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: tests: Incrase jenkins test timeout to 4 hours.

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/23463 )



Change subject: tests: Incrase jenkins test timeout to 4 hours.
..

tests: Incrase jenkins test timeout to 4 hours.

Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
---
M tests/jenkins/presubmit.cfg
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/tests/jenkins/presubmit.cfg b/tests/jenkins/presubmit.cfg
index 742a6fc..6c9296e 100644
--- a/tests/jenkins/presubmit.cfg
+++ b/tests/jenkins/presubmit.cfg
@@ -2,3 +2,5 @@

 # Location of the continuous batch script in repository.
 build_file: "jenkins-gem5-prod/tests/jenkins/presubmit.sh"
+
+timeout_mins: 240

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Gerrit-Branch: master
Gerrit-Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Gerrit-Change-Number: 23463
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[refs/meta/config]: Review access change

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18088 )


Change subject: Review access change
..

Review access change

Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18088
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Rahul Thakur 
---
A groups
M project.config
2 files changed, 10 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Rahul Thakur: Looks good to me, approved



diff --git a/groups b/groups
new file mode 100644
index 000..16dba15
--- /dev/null
+++ b/groups
@@ -0,0 +1,4 @@
+# UUID Group Name
+#
+mdb:kokoro mdb/kokoro
+mdb:kokoro-dedicated   mdb/kokoro-dedicated
diff --git a/project.config b/project.config
index 9617eda..876c893 100644
--- a/project.config
+++ b/project.config
@@ -2,3 +2,9 @@
inheritFrom = public
 [submit]
action = rebase always
+[access "refs/*"]
+   read = group mdb/kokoro
+   read = group mdb/kokoro-dedicated
+[access "refs/heads/*"]
+   label-Verified = -1..+1 group mdb/kokoro
+   label-Verified = -1..+1 group mdb/kokoro-dedicated

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Gerrit-Project: public/gem5
Gerrit-Branch: refs/meta/config
Gerrit-Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
Gerrit-Change-Number: 18088
Gerrit-PatchSet: 2
Gerrit-Owner: Rahul Thakur 
Gerrit-Assignee: Jason Lowe-Power 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Rahul Thakur 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[refs/meta/config]: Review access change

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18088



Change subject: Review access change
..

Review access change

Change-Id: I4ec5c15111b91efb0c98a654ba7335c640c079e8
---
A groups
M project.config
2 files changed, 10 insertions(+), 0 deletions(-)



diff --git a/groups b/groups
new file mode 100644
index 000..16dba15
--- /dev/null
+++ b/groups
@@ -0,0 +1,4 @@
+# UUID Group Name
+#
+mdb:kokoro mdb/kokoro
+mdb:kokoro-dedicated   mdb/kokoro-dedicated
diff --git a/project.config b/project.config
index 9617eda..876c893 100644
--- a/project.config
+++ b/project.config
@@ -2,3 +2,9 @@
inheritFrom = public
 [submit]
action = rebase always
+[access "refs/*"]
+   read = group mdb/kokoro
+   read = group mdb/kokoro-dedicated
+[access "refs/heads/*"]
+   label-Verified = -1..+1 group mdb/kokoro
+   label-Verified = -1..+1 group mdb/kokoro-dedicated

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Gerrit-Branch: refs/meta/config
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Gerrit-Change-Number: 18088
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur 
Gerrit-MessageType: newchange
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[gem5-dev] Change in public/gem5[master]: mem: Fix uncacheable write snoop flow

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/8681



Change subject: mem: Fix uncacheable write snoop flow
..

mem: Fix uncacheable write snoop flow

Earlier patches fixed handling of uncacheable IO WriteReq snoops hit in
caches by allowing in-place modification of cache block.

This patch proposes a few fixes in that:
1. Update upstream snoop packet with current snoop pkt data
2. Update mshr and cache block for WriteReq and additionally
   WriteLineReq which was previously left out.

Change-Id: Ia6fbdf53e92427f8e6ec74028b73769accc27562
---
M src/mem/cache/cache.cc
M src/mem/cache/mshr.cc
M src/mem/packet.hh
3 files changed, 49 insertions(+), 3 deletions(-)



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 1821f18..9cdc490 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -2069,6 +2069,15 @@
 // there is a snoop hit in upper levels
 Packet snoopPkt(pkt, true, true);
 snoopPkt.setExpressSnoop();
+
+// Set data for the upstream snoop pkt from the current pkt
+// which is write transaction and carries modified data
+if ((pkt->cmd == MemCmd::WriteReq ||
+ pkt->cmd == MemCmd::WriteLineReq) && !alreadyResponded) {
+assert(pkt->req->isUncacheable());
+snoopPkt.setData(pkt->getConstPtr());
+}
+
 // the snoop packet does not need to wait any additional
 // time
 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
@@ -2211,6 +2220,18 @@
 // we already called setHasSharers above
 }

+// For uncacheable write, update the dirty data
+if (pkt->cmd == MemCmd::WriteReq || pkt->cmd ==  
MemCmd::WriteLineReq) {

+assert(pkt->req->isUncacheable());
+// write the partial line to the right part of the block
+pkt->writeDataToBlock(blk->data, blkSize);
+
+// the block is not going to end up with a cache
+// allocation, but set the flag to indicate that there are
+// sharers, also to avoid the panic below
+pkt->setHasSharers();
+}
+
 // if we are returning a writable and dirty (Modified) line,
 // we should be invalidating the line
 panic_if(!invalidate && !pkt->hasSharers(),
@@ -2356,6 +2377,19 @@
 pkt->setResponderHadWritable();
 }

+// partial line uncacheable write, update the dirty data
+if (pkt->cmd == MemCmd::WriteReq ||
+pkt->cmd == MemCmd::WriteLineReq) {
+assert(pkt->req->isUncacheable());
+// write the partial line to the right part of the
+// writeback packet
+pkt->writeDataToBlock(wb_pkt->getPtr(), blkSize);
+
+// not strictly necessary, but set the flag indicating
+// that the packet has sharers
+pkt->setHasSharers();
+}
+
 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr(),
false, false);
 }
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 493b7f0..5af4f6a 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -425,8 +425,19 @@
 // the latter case the cache is responsible for deleting both
 // the packet and the request as part of handling the deferred
 // snoop.
-PacketPtr cp_pkt = will_respond ? new Packet(pkt, true, true) :
-new Packet(new Request(*pkt->req), pkt->cmd, blkSize, pkt->id);
+PacketPtr cp_pkt = nullptr;
+if (will_respond) {
+cp_pkt = new Packet(pkt, true, true);
+//  Update the data if request is write carrying updated data
+if (pkt->cmd == MemCmd::WriteReq ||
+pkt->cmd == MemCmd::WriteLineReq) {
+assert(pkt->req->isUncacheable());
+cp_pkt->allocate();
+cp_pkt->setData(pkt->getConstPtr());
+}
+} else {
+cp_pkt = new Packet(new Request(*pkt->req), pkt->cmd, blkSize);
+}

 if (will_respond) {
 // we are the ordering point, and will consequently
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 66625b3..1f481db 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -530,7 +530,8 @@
 // look at the hasSharers flag (if not set, the response is to
 // be considered writable)
 assert(isRequest());
-return cmd.needsWritable();
+// ignore the needsWritable flag if the packet is uncacheable
+return cmd.needsWritable() && !req->isUncacheable();
 }
 bool needsResponse() const   { return cmd.needsResponse(); }
 bool isInvalidate() const{ return cmd.isInvalidate(); }

--
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[gem5-dev] Change in public/gem5[master]: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2261 )


Change subject: arm, kvm: enable running 32-bit Guest under ARM KVM64
..

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Reviewed-on: https://gem5-review.googlesource.com/2261
Maintainer: Rahul Thakur 
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 10 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Rahul Thakur: Looks good to me, approved



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 08b9011..67e2e46 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -268,7 +268,13 @@
 for (int i = 0; i < NUM_XREGS; ++i) {
 const auto value(getOneRegU64(kvmXReg(i)));
 DPRINTF(KvmContext, "  X%i := 0x%x\n", i, value);
-tc->setIntReg(INTREG_X0 + i, value);
+// KVM64 returns registers in 64-bit layout. If we are in aarch32
+// mode, we need to map these to banked ARM32 registers.
+if (inAArch64(tc)) {
+tc->setIntReg(INTREG_X0 + i, value);
+} else {
+tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
+}
 }

 for (const auto  : intRegMap) {
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index e511fd6..e25112c 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -79,6 +79,9 @@
 memset(_config, 0, sizeof(target_config));

 vm.kvmArmPreferredTarget(target_config);
+if (!((ArmSystem *)system)->highestELIs64()) {
+target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
+}
 kvmArmVCpuInit(target_config);
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Gerrit-Change-Number: 2261
Gerrit-PatchSet: 4
Gerrit-Owner: Rahul Thakur 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2261

to look at the new patch set (#3).

Change subject: arm, kvm: enable running 32-bit Guest under ARM KVM64
..

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 10 insertions(+), 1 deletion(-)


--
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Gerrit-Branch: master
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Gerrit-Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Gerrit-Change-Number: 2261
Gerrit-PatchSet: 3
Gerrit-Owner: Rahul Thakur 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: arm, kvm: fix saving/restoring conditional flags in ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2260 )


Change subject: arm, kvm: fix saving/restoring conditional flags in ARM  
KVM64

..

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Reviewed-on: https://gem5-review.googlesource.com/2260
Reviewed-by: Rahul Thakur 
Maintainer: Rahul Thakur 
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 28 insertions(+), 3 deletions(-)

Approvals:
  Rahul Thakur: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index e8a77b0..08b9011 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -102,7 +102,6 @@
 };

 const std::vector ArmV8KvmCPU::miscRegMap = {
-MiscRegInfo(INT_REG(regs.pstate), MISCREG_CPSR, "PSTATE"),
 MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]),  
MISCREG_SPSR_EL1, "SPSR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]),  
MISCREG_SPSR_ABT, "SPSR(ABT)"),

@@ -135,6 +134,8 @@

 for (const auto  : intRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
+
+inform("  %s: %s\n", "PSTATE",  
getAndFormatOneReg(INT_REG(regs.pstate)));


 for (const auto  : miscRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
@@ -188,6 +189,20 @@
 ArmV8KvmCPU::updateKvmState()
 {
 DPRINTF(KvmContext, "In updateKvmState():\n");
+
+// update pstate register state
+CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
+cpsr.nz = tc->readCCReg(CCREG_NZ);
+cpsr.c = tc->readCCReg(CCREG_C);
+cpsr.v = tc->readCCReg(CCREG_V);
+if (cpsr.width) {
+cpsr.ge = tc->readCCReg(CCREG_GE);
+} else {
+cpsr.ge = 0;
+}
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr);
+setOneReg(INT_REG(regs.pstate), cpsr);
+
 for (const auto  : miscRegMap) {
 const uint64_t value(tc->readMiscReg(ri.idx));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
@@ -231,7 +246,18 @@
 {
 DPRINTF(KvmContext, "In updateThreadContext():\n");

-// Update core misc regs first as they (particularly PSTATE/CPSR)
+// Update pstate thread context
+const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr);
+tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr);
+tc->setCCReg(CCREG_NZ, cpsr.nz);
+tc->setCCReg(CCREG_C, cpsr.c);
+tc->setCCReg(CCREG_V, cpsr.v);
+if (cpsr.width) {
+tc->setCCReg(CCREG_GE, cpsr.ge);
+}
+
+// Update core misc regs first as they
 // affect how other registers are mapped.
 for (const auto  : miscRegMap) {
 const auto value(getOneRegU64(ri.kvm));
@@ -266,7 +292,6 @@
 tc->setMiscRegNoEffect(ri.idx, value);
 }

-const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
 PCState pc(getOneRegU64(INT_REG(regs.pc)));
 pc.aarch64(inAArch64(tc));
 pc.thumb(cpsr.t);

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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Gerrit-Change-Number: 2260
Gerrit-PatchSet: 3
Gerrit-Owner: Rahul Thakur 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: arm, kvm: fix saving/restoring conditional flags in ARM KVM64

[Rahul Thakur (Gerrit)]

Hello Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2260

to look at the new patch set (#2).

Change subject: arm, kvm: fix saving/restoring conditional flags in ARM  
KVM64

..

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 28 insertions(+), 3 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Gerrit-Change-Number: 2260
Gerrit-PatchSet: 2
Gerrit-Owner: Rahul Thakur 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: arm, kvm: fix saving/restoring conditional flags in ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/2260



Change subject: arm, kvm: fix saving/restoring conditional flags in ARM  
KVM64

..

arm, kvm: fix saving/restoring conditional flags in ARM KVM64

The gem5 stores flags separately from other fields CPSR, so we need to
split them out and recombine on trips to/from KVM.

Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 29 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index e8a77b0..5145fba 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -102,7 +102,6 @@
 };

 const std::vector ArmV8KvmCPU::miscRegMap = {
-MiscRegInfo(INT_REG(regs.pstate), MISCREG_CPSR, "PSTATE"),
 MiscRegInfo(INT_REG(elr_el1), MISCREG_ELR_EL1, "ELR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_EL1]),  
MISCREG_SPSR_EL1, "SPSR(EL1)"),
 MiscRegInfo(INT_REG(spsr[KVM_SPSR_ABT]),  
MISCREG_SPSR_ABT, "SPSR(ABT)"),

@@ -135,6 +134,8 @@

 for (const auto  : intRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
+
+inform("  %s: %s\n", "PSTATE",  
getAndFormatOneReg(INT_REG(regs.pstate)));


 for (const auto  : miscRegMap)
 inform("  %s: %s\n", ri.name, getAndFormatOneReg(ri.kvm));
@@ -188,6 +189,20 @@
 ArmV8KvmCPU::updateKvmState()
 {
 DPRINTF(KvmContext, "In updateKvmState():\n");
+
+// update pstate register state
+CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
+cpsr.nz = tc->readCCReg(CCREG_NZ);
+cpsr.c = tc->readCCReg(CCREG_C);
+cpsr.v = tc->readCCReg(CCREG_V);
+if (cpsr.width) {
+cpsr.ge = tc->readCCReg(CCREG_GE);
+} else {
+cpsr.ge = 0;
+}
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr);
+setOneReg(INT_REG(regs.pstate), cpsr);
+
 for (const auto  : miscRegMap) {
 const uint64_t value(tc->readMiscReg(ri.idx));
 DPRINTF(KvmContext, "  %s := 0x%x\n", ri.name, value);
@@ -231,7 +246,19 @@
 {
 DPRINTF(KvmContext, "In updateThreadContext():\n");

-// Update core misc regs first as they (particularly PSTATE/CPSR)
+// Update pstate thread context
+const auto cpsr_value(getOneRegU64(INT_REG(regs.pstate)));
+DPRINTF(KvmContext, "  %s := 0x%x\n", "PSTATE", cpsr_value);
+tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr_value);
+const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
+tc->setCCReg(CCREG_NZ, cpsr.nz);
+tc->setCCReg(CCREG_C, cpsr.c);
+tc->setCCReg(CCREG_V, cpsr.v);
+if (cpsr.width) {
+tc->setCCReg(CCREG_GE, cpsr.ge);
+}
+
+// Update core misc regs first as they
 // affect how other registers are mapped.
 for (const auto  : miscRegMap) {
 const auto value(getOneRegU64(ri.kvm));
@@ -266,7 +293,6 @@
 tc->setMiscRegNoEffect(ri.idx, value);
 }

-const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
 PCState pc(getOneRegU64(INT_REG(regs.pc)));
 pc.aarch64(inAArch64(tc));
 pc.thumb(cpsr.t);

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I28ed00eb6f0e2a1436adfbc51b6ccf056958afeb
Gerrit-Change-Number: 2260
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur 
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[gem5-dev] Change in public/gem5[master]: arm, kvm: enable running 32-bit Guest under ARM KVM64

[Rahul Thakur (Gerrit)]

Rahul Thakur has uploaded this change for review. (  
https://gem5-review.googlesource.com/2261



Change subject: arm, kvm: enable running 32-bit Guest under ARM KVM64
..

arm, kvm: enable running 32-bit Guest under ARM KVM64

1) Pass KVM_ARM_VCPU_EL1_32BIT to kvmArmVCpuInit
   when running 32-bit OS

2) Correctly map 64-bit registers to banked 32-bit ones

Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
---
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/kvm/base_cpu.cc
2 files changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 5145fba..af99cbe 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -269,7 +269,13 @@
 for (int i = 0; i < NUM_XREGS; ++i) {
 const auto value(getOneRegU64(kvmXReg(i)));
 DPRINTF(KvmContext, "  X%i := 0x%x\n", i, value);
-tc->setIntReg(INTREG_X0 + i, value);
+// KVM64 returns registers in 64-bit layout. If we are in aarch32
+// mode, we need to map these to banked ARM32 registers.
+if (inAArch64(tc)) {
+tc->setIntReg(INTREG_X0 + i, value);
+} else {
+tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
+}
 }

 for (const auto  : intRegMap) {
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index e511fd6..e25112c 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -79,6 +79,9 @@
 memset(_config, 0, sizeof(target_config));

 vm.kvmArmPreferredTarget(target_config);
+if (!((ArmSystem *)system)->highestELIs64()) {
+target_config.features[0] |= (1 << KVM_ARM_VCPU_EL1_32BIT);
+}
 kvmArmVCpuInit(target_config);
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1dec6427d6f5c3bba599ccdd804f1dfe80d3e670
Gerrit-Change-Number: 2261
Gerrit-PatchSet: 1
Gerrit-Owner: Rahul Thakur 
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