[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export the reset signals of the GIC.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67575?usp=email )
Change subject: fastmodel: Export the reset signals of the GIC.
..
fastmodel: Export the reset signals of the GIC.
These are the "reset" and "po_reset" lines. It seems reasonable that
these are the normal reset and the power on reset signals, but that's
not spelled out in the fast model "lisa" file, nor does it explain
exactly what the difference is between them.
Change-Id: I686b4d973fc3cfff8a3ec05f8c95ee2cb6ff6698
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67575
Reviewed-by: Jui-min Lee
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/fastmodel/GIC/GIC.lisa
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
4 files changed, 54 insertions(+), 1 deletion(-)
Approvals:
Jui-min Lee: Looks good to me, approved
kokoro: Regressions pass
Gabe Black: Looks good to me, approved
diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
index ce0a8c5..b1a9a3c 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -42,6 +42,7 @@
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.Gic import BaseGic
from m5.objects.IntPin import VectorIntSourcePin
+from m5.objects.ResetPort import ResetResponsePort
from m5.objects.SystemC import SystemC_ScModule
GICV3_COMMS_TARGET_ROLE = "GICV3 COMMS TARGET"
@@ -850,6 +851,9 @@
wake_request = VectorIntSourcePin("GIC wake request initiator")
+reset = ResetResponsePort("Reset")
+po_reset = ResetResponsePort("Power on reset")
+
# Used for DTB autogeneration
_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
diff --git a/src/arch/arm/fastmodel/GIC/GIC.lisa
b/src/arch/arm/fastmodel/GIC/GIC.lisa
index 34b09c8..5443b55 100644
--- a/src/arch/arm/fastmodel/GIC/GIC.lisa
+++ b/src/arch/arm/fastmodel/GIC/GIC.lisa
@@ -56,6 +56,10 @@
// Outgoing wake requests.
gic.wake_request => self.wake_request;
+// Reset signals.
+self.normal_reset => gic.reset;
+self.po_reset => gic.po_reset;
+
// Internal ports for PPI and SPI programmatic access.
self.ppi_0 => gic.ppi_in_0;
self.ppi_1 => gic.ppi_in_1;
@@ -405,6 +409,9 @@
}
}
+slave port normal_reset;
+slave port po_reset;
+
internal slave port spi[988];
internal slave port ppi_0[16];
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc
b/src/arch/arm/fastmodel/GIC/gic.cc
index 493aa81..5f01cfb 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -72,10 +72,15 @@
SCGIC::SCGIC(const SCFastModelGICParams ,
sc_core::sc_module_name _name)
-: scx_evs_GIC(_name), _params(params)
+: scx_evs_GIC(_name), _params(params),
+ resetPort(params.name + ".reset", 0),
+ poResetPort(params.name + ".po_reset", 0)
{
signalInterrupt.bind(signal_interrupt);
+resetPort.signal_out.bind(scx_evs_GIC::normal_reset);
+poResetPort.signal_out.bind(scx_evs_GIC::po_reset);
+
for (int i = 0; i < wake_request.size(); i++) {
wakeRequests.emplace_back(
new SignalReceiver(csprintf("%s.wakerequest[%d]", name(), i)));
@@ -298,6 +303,18 @@
set_parameter("gic.consolidators", params.consolidators);
}
+Port &
+SCGIC::gem5_getPort(const std::string _name, int idx)
+{
+if (if_name == "reset") {
+return resetPort;
+} else if (if_name == "po_reset") {
+return poResetPort;
+} else {
+return scx_evs_GIC::gem5_getPort(if_name, idx);
+}
+}
+
void
SCGIC::before_end_of_elaboration()
{
@@ -341,6 +358,8 @@
return *ptr;
} else if (if_name == "wake_request") {
return *wakeRequestPorts.at(idx);
+} else if (if_name == "reset" || if_name == "po_reset") {
+return scGIC->gem5_getPort(if_name, idx);
} else {
return BaseGic::getPort(if_name, idx);
}
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh
b/src/arch/arm/fastmodel/GIC/gic.hh
index 0e502fc..070fe3b 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -37,6 +37,7 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
+#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "dev/arm/base_gic.hh"
#include "dev/intpin.hh"
#include "params/FastModelGIC.hh"
@@ -91,9 +92,13 @@
SCGIC(const SCFastModelGICParams ) : SCGIC(p, p.name.c_str()) {}
SCGIC(const SCFastModelGICParams , sc_core::sc_module_name
_name);
+Port _getPort(const std::string _name, int idx) override;
+
SignalInterruptInitiatorSocket signalInterrupt;
std::vector> wakeRequests;
+SignalSender
[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: Export the reset signals of the GIC.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67575?usp=email )
Change subject: fastmodel: Export the reset signals of the GIC.
..
fastmodel: Export the reset signals of the GIC.
These are the "reset" and "po_reset" lines. It seems reasonable that
these are the normal reset and the power on reset signals, but that's
not spelled out in the fast model "lisa" file, nor does it explain
exactly what the difference is between them.
Change-Id: I686b4d973fc3cfff8a3ec05f8c95ee2cb6ff6698
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
M src/arch/arm/fastmodel/GIC/GIC.lisa
M src/arch/arm/fastmodel/GIC/gic.cc
M src/arch/arm/fastmodel/GIC/gic.hh
4 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
index ce0a8c5..24ab660 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -42,6 +42,7 @@
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.Gic import BaseGic
from m5.objects.IntPin import VectorIntSourcePin
+from m5.objects.ResetPort import ResetResponsePort
from m5.objects.SystemC import SystemC_ScModule
GICV3_COMMS_TARGET_ROLE = "GICV3 COMMS TARGET"
@@ -850,6 +851,9 @@
wake_request = VectorIntSourcePin("GIC wake request initiator")
+reset = ResetResponsePort('Reset')
+po_reset = ResetResponsePort('Power on reset')
+
# Used for DTB autogeneration
_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
diff --git a/src/arch/arm/fastmodel/GIC/GIC.lisa
b/src/arch/arm/fastmodel/GIC/GIC.lisa
index 34b09c8..5443b55 100644
--- a/src/arch/arm/fastmodel/GIC/GIC.lisa
+++ b/src/arch/arm/fastmodel/GIC/GIC.lisa
@@ -56,6 +56,10 @@
// Outgoing wake requests.
gic.wake_request => self.wake_request;
+// Reset signals.
+self.normal_reset => gic.reset;
+self.po_reset => gic.po_reset;
+
// Internal ports for PPI and SPI programmatic access.
self.ppi_0 => gic.ppi_in_0;
self.ppi_1 => gic.ppi_in_1;
@@ -405,6 +409,9 @@
}
}
+slave port normal_reset;
+slave port po_reset;
+
internal slave port spi[988];
internal slave port ppi_0[16];
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc
b/src/arch/arm/fastmodel/GIC/gic.cc
index 493aa81..5f01cfb 100644
--- a/src/arch/arm/fastmodel/GIC/gic.cc
+++ b/src/arch/arm/fastmodel/GIC/gic.cc
@@ -72,10 +72,15 @@
SCGIC::SCGIC(const SCFastModelGICParams ,
sc_core::sc_module_name _name)
-: scx_evs_GIC(_name), _params(params)
+: scx_evs_GIC(_name), _params(params),
+ resetPort(params.name + ".reset", 0),
+ poResetPort(params.name + ".po_reset", 0)
{
signalInterrupt.bind(signal_interrupt);
+resetPort.signal_out.bind(scx_evs_GIC::normal_reset);
+poResetPort.signal_out.bind(scx_evs_GIC::po_reset);
+
for (int i = 0; i < wake_request.size(); i++) {
wakeRequests.emplace_back(
new SignalReceiver(csprintf("%s.wakerequest[%d]", name(), i)));
@@ -298,6 +303,18 @@
set_parameter("gic.consolidators", params.consolidators);
}
+Port &
+SCGIC::gem5_getPort(const std::string _name, int idx)
+{
+if (if_name == "reset") {
+return resetPort;
+} else if (if_name == "po_reset") {
+return poResetPort;
+} else {
+return scx_evs_GIC::gem5_getPort(if_name, idx);
+}
+}
+
void
SCGIC::before_end_of_elaboration()
{
@@ -341,6 +358,8 @@
return *ptr;
} else if (if_name == "wake_request") {
return *wakeRequestPorts.at(idx);
+} else if (if_name == "reset" || if_name == "po_reset") {
+return scGIC->gem5_getPort(if_name, idx);
} else {
return BaseGic::getPort(if_name, idx);
}
diff --git a/src/arch/arm/fastmodel/GIC/gic.hh
b/src/arch/arm/fastmodel/GIC/gic.hh
index 0e502fc..070fe3b 100644
--- a/src/arch/arm/fastmodel/GIC/gic.hh
+++ b/src/arch/arm/fastmodel/GIC/gic.hh
@@ -37,6 +37,7 @@
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/common/signal_receiver.hh"
+#include "arch/arm/fastmodel/common/signal_sender.hh"
#include "dev/arm/base_gic.hh"
#include "dev/intpin.hh"
#include "params/FastModelGIC.hh"
@@ -91,9 +92,13 @@
SCGIC(const SCFastModelGICParams ) : SCGIC(p, p.name.c_str()) {}
SCGIC(const SCFastModelGICParams , sc_core::sc_module_name
_name);
+Port _getPort(const std::string _name, int idx) override;
+
SignalInterruptInitiatorSocket signalInterrupt;
std::vector> wakeRequests;
+SignalSender resetPort;
+SignalSender poResetPort;
void before_end_of_elaboration() override;
--
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