Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/65274?usp=email )
Change subject: arch-riscv: Add VS field to the STATUS CSR
..
arch-riscv: Add VS field to the STATUS CSR
Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.
Change-Id: Ifda1c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65274
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/regs/misc.hh
1 file changed, 30 insertions(+), 10 deletions(-)
Approvals:
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index cb8c907..5f07447 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -562,6 +562,7 @@
Bitfield<16, 15> xs;
Bitfield<14, 13> fs;
Bitfield<12, 11> mpp;
+Bitfield<10, 9> vs;
Bitfield<8> spp;
Bitfield<7> mpie;
Bitfield<5> spie;
@@ -612,6 +613,7 @@
const RegVal STATUS_XS_MASK = 3ULL << 15;
const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
const RegVal STATUS_MPP_MASK = 3ULL << 11;
+const RegVal STATUS_VS_MASK = 3ULL << 9;
const RegVal STATUS_SPP_MASK = 1ULL << 8;
const RegVal STATUS_MPIE_MASK = 1ULL << 7;
const RegVal STATUS_SPIE_MASK = 1ULL << 5;
@@ -624,21 +626,21 @@
STATUS_TW_MASK | STATUS_TVM_MASK |
STATUS_MXR_MASK | STATUS_SUM_MASK |
STATUS_MPRV_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_MPP_MASK |
-STATUS_SPP_MASK | STATUS_MPIE_MASK |
-STATUS_SPIE_MASK | STATUS_UPIE_MASK |
-STATUS_MIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_MPP_MASK | STATUS_SPP_MASK |
+STATUS_MPIE_MASK | STATUS_SPIE_MASK |
+STATUS_UPIE_MASK | STATUS_MIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
STATUS_MXR_MASK | STATUS_SUM_MASK |
STATUS_XS_MASK | STATUS_FS_MASK |
-STATUS_SPP_MASK | STATUS_SPIE_MASK |
-STATUS_UPIE_MASK | STATUS_SIE_MASK |
-STATUS_UIE_MASK;
+STATUS_VS_MASK | STATUS_SPP_MASK |
+STATUS_SPIE_MASK | STATUS_UPIE_MASK |
+STATUS_SIE_MASK | STATUS_UIE_MASK;
const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
STATUS_SUM_MASK | STATUS_XS_MASK |
-STATUS_FS_MASK | STATUS_UPIE_MASK |
-STATUS_UIE_MASK;
+STATUS_FS_MASK | STATUS_VS_MASK |
+STATUS_UPIE_MASK | STATUS_UIE_MASK;
const RegVal MEI_MASK = 1ULL << 11;
const RegVal SEI_MASK = 1ULL << 9;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifda1c551a23ed892fb8ac7ef31fa98f0b6db
Gerrit-Change-Number: 65274
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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