[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmISA namespace requirement for TME instructions
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34235 )
Change subject: arch-arm: Fix ArmISA namespace requirement for TME
instructions
..
arch-arm: Fix ArmISA namespace requirement for TME instructions
This is needed after:
https://gem5-review.googlesource.com/c/public/gem5/+/34155
Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34235
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
M src/arch/arm/insts/tme64classic.cc
M src/arch/arm/insts/tme64ruby.cc
5 files changed, 36 insertions(+), 29 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 7aedd55..a077882 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -234,14 +234,14 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
-class RegNone : public ArmStaticInst
+class RegNone : public ArmISA::ArmStaticInst
{
protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;
-RegNone(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest) :
-ArmStaticInst(mnem, _machInst, __opClass),
+RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
+OpClass __opClass, ArmISA::IntRegIndex _dest) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest)
{}
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index da228c4..30aff20 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -40,6 +40,8 @@
#include
+using namespace ArmISA;
+
namespace ArmISAInst {
std::string
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index dada664..b75adc1 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -44,18 +44,19 @@
namespace ArmISAInst {
-class MicroTmeOp : public MicroOp
+class MicroTmeOp : public ArmISA::MicroOp
{
protected:
-MicroTmeOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) :
- MicroOp(mnem, machInst, __opClass)
+MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass)
+ : ArmISA::MicroOp(mnem, machInst, __opClass)
{}
};
class MicroTmeBasic64 : public MicroTmeOp
{
protected:
-MicroTmeBasic64(const char *mnem, ExtMachInst machInst,
+MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst,
OpClass __opClass) :
MicroTmeOp(mnem, machInst, __opClass)
{}
@@ -64,30 +65,30 @@
const Loader::SymbolTable *symtab)
const;
};
-class TmeImmOp64 : public ArmStaticInst
+class TmeImmOp64 : public ArmISA::ArmStaticInst
{
protected:
uint64_t imm;
-TmeImmOp64(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, uint64_t _imm) :
- ArmStaticInst(mnem, machInst, __opClass),
- imm(_imm)
+TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass, uint64_t _imm)
+ : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+imm(_imm)
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab)
const;
};
-class TmeRegNone64 : public ArmStaticInst
+class TmeRegNone64 : public ArmISA::ArmStaticInst
{
protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;
-TmeRegNone64(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex _dest) :
- ArmStaticInst(mnem, machInst, __opClass),
- dest(_dest)
+TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass, ArmISA::IntRegIndex _dest)
+ : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+dest(_dest)
{}
std::string generateDisassembly(Addr pc,
@@ -97,7 +98,7 @@
class Tstart64 : public TmeRegNone64
{
public:
-Tstart64(ExtMachInst, IntRegIndex);
+Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -107,7 +108,7 @@
class Ttest64 : public TmeRegNone64
{
public:
-Ttest64(ExtMachInst, IntRegIndex);
+Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
};
@@ -115,7 +116,7 @@
class Tcancel64 : public TmeImmOp64
{
public:
-
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix ArmISA namespace requirement for TME instructions
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34235 )
Change subject: arch-arm: Fix ArmISA namespace requirement for TME
instructions
..
arch-arm: Fix ArmISA namespace requirement for TME instructions
This is needed after:
https://gem5-review.googlesource.com/c/public/gem5/+/34155
Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/insts/misc64.hh
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
M src/arch/arm/insts/tme64classic.cc
M src/arch/arm/insts/tme64ruby.cc
5 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 7aedd55..a077882 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -234,14 +234,14 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
-class RegNone : public ArmStaticInst
+class RegNone : public ArmISA::ArmStaticInst
{
protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;
-RegNone(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest) :
-ArmStaticInst(mnem, _machInst, __opClass),
+RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
+OpClass __opClass, ArmISA::IntRegIndex _dest) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest)
{}
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index da228c4..30aff20 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -40,6 +40,8 @@
#include
+using namespace ArmISA;
+
namespace ArmISAInst {
std::string
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index dada664..b75adc1 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -44,18 +44,19 @@
namespace ArmISAInst {
-class MicroTmeOp : public MicroOp
+class MicroTmeOp : public ArmISA::MicroOp
{
protected:
-MicroTmeOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) :
- MicroOp(mnem, machInst, __opClass)
+MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass)
+ : ArmISA::MicroOp(mnem, machInst, __opClass)
{}
};
class MicroTmeBasic64 : public MicroTmeOp
{
protected:
-MicroTmeBasic64(const char *mnem, ExtMachInst machInst,
+MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst,
OpClass __opClass) :
MicroTmeOp(mnem, machInst, __opClass)
{}
@@ -64,30 +65,30 @@
const Loader::SymbolTable *symtab)
const;
};
-class TmeImmOp64 : public ArmStaticInst
+class TmeImmOp64 : public ArmISA::ArmStaticInst
{
protected:
uint64_t imm;
-TmeImmOp64(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, uint64_t _imm) :
- ArmStaticInst(mnem, machInst, __opClass),
- imm(_imm)
+TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass, uint64_t _imm)
+ : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+imm(_imm)
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab)
const;
};
-class TmeRegNone64 : public ArmStaticInst
+class TmeRegNone64 : public ArmISA::ArmStaticInst
{
protected:
-IntRegIndex dest;
+ArmISA::IntRegIndex dest;
-TmeRegNone64(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex _dest) :
- ArmStaticInst(mnem, machInst, __opClass),
- dest(_dest)
+TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
+ OpClass __opClass, ArmISA::IntRegIndex _dest)
+ : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
+dest(_dest)
{}
std::string generateDisassembly(Addr pc,
@@ -97,7 +98,7 @@
class Tstart64 : public TmeRegNone64
{
public:
-Tstart64(ExtMachInst, IntRegIndex);
+Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -107,7 +108,7 @@
class Ttest64 : public TmeRegNone64
{
public:
-Ttest64(ExtMachInst, IntRegIndex);
+Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
};
@@ -115,7 +116,7 @@
class Tcancel64 : public TmeImmOp64
{
public:
-Tcancel64(ExtMachInst, uint64_t);
+Tcancel64(ArmISA::ExtMachInst, uint64_t);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -125,7 +126,7 @@
class MicroTfence64 : public
