[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding style in self_debug.[cc, hh]

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31082 )


Change subject: arch-arm: Fix coding style in self_debug.[cc, hh]
..

arch-arm: Fix coding style in self_debug.[cc, hh]

Change-Id: I67be98af412b745ea9e16d4e8c6d422c9fbb29fc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31082
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 229 insertions(+), 209 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Nikos Nikoleris: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 63ddb45..94d2f23 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -107,7 +107,7 @@


 Fault
-SelfDebug::triggerException(ThreadContext * tc, Addr vaddr)
+SelfDebug::triggerException(ThreadContext *tc, Addr vaddr)
 {
 if (to32) {
 return std::make_shared(vaddr,
@@ -164,15 +164,17 @@
 SelfDebug::isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el,
  bool secure, bool mask)
 {
-bool route_to_el2 =  ArmSystem::haveEL(tc, EL2)
- && !secure && enableTdeTge;
-ExceptionLevel target_el = route_to_el2? EL2 : EL1;
-if (oslk || (bSDD && secure && ArmSystem::haveEL(tc, EL3))){
+bool route_to_el2 =  ArmSystem::haveEL(tc, EL2) &&
+!secure && enableTdeTge;
+
+ExceptionLevel target_el = route_to_el2 ? EL2 : EL1;
+if (oslk || (bSDD && secure && ArmSystem::haveEL(tc, EL3))) {
 return false;
 }
-if (el == target_el){
+
+if (el == target_el) {
 return bKDE  && !mask;
-}else{
+} else {
 return target_el > el;
 }
 }
@@ -181,15 +183,16 @@
 SelfDebug::isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el,
  bool secure, bool mask)
 {
-if (el==EL0 && !ELStateUsingAArch32(tc, EL1, secure)){
+if (el == EL0 && !ELStateUsingAArch32(tc, EL1, secure)) {
 return isDebugEnabledForEL64(tc, el, secure, mask);
 }
-if (oslk){
+
+if (oslk) {
 return false;
 }

 bool enabled;
-if (secure && ArmSystem::haveEL(tc, EL3)){
+if (secure && ArmSystem::haveEL(tc, EL3)) {
 // We ignore the check for invasive External debug checking SPIDEN
 // and DBGEN signals. They are not implemented
 bool spd32 = bits(tc->readMiscReg(MISCREG_MDCR_EL3), 14);
@@ -197,9 +200,7 @@

 bool suiden = bits(tc->readMiscReg(MISCREG_SDER), 0);
 enabled  = el == EL0 ? (enabled || suiden) : enabled;
-}
-else
-{
+} else {
 enabled = el != EL2;
 }
 return enabled;
@@ -306,6 +307,61 @@
 return v;
 }

+void
+SelfDebug::init(ThreadContext *tc)
+{
+if (initialized)
+return;
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+aarch32 = cpsr.width == 1;
+
+const AA64DFR0 dfr = tc->readMiscReg(MISCREG_ID_AA64DFR0_EL1);
+const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
+const AA64MMFR1 mm_fr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+
+for (int i = 0; i <= dfr.brps; i++) {
+const bool isctxaw = i >= (dfr.brps - dfr.ctx_cmps);
+
+BrkPoint bkp = BrkPoint((MiscRegIndex)(MISCREG_DBGBCR0_EL1 + i),
+(MiscRegIndex)(MISCREG_DBGBVR0_EL1 + i),
+this, isctxaw, (bool)mm_fr2.varange,
+mm_fr1.vmidbits, aarch32);
+const DBGBCR ctr = tc->readMiscReg(MISCREG_DBGBCR0_EL1 + i);
+
+bkp.updateControl(ctr);
+arBrkPoints.push_back(bkp);
+}
+
+for (int i = 0; i <= dfr.wrps; i++) {
+WatchPoint wtp = WatchPoint((MiscRegIndex)(MISCREG_DBGWCR0 + i),
+(MiscRegIndex)(MISCREG_DBGWVR0 + i),
+this, (bool)mm_fr2.varange, aarch32);
+const DBGWCR ctr = tc->readMiscReg(MISCREG_DBGWCR0 + i);
+
+wtp.updateControl(ctr);
+arWatchPoints.push_back(wtp);
+}
+
+initialized = true;
+
+RegVal oslar_el1 = tc->readMiscReg(MISCREG_OSLAR_EL1);
+updateOSLock(oslar_el1);
+// Initialize preloaded control booleans
+uint64_t mdscr_el1 = tc->readMiscReg(MISCREG_MDSCR_EL1);
+setMDSCRvals(mdscr_el1);
+
+const uint64_t mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
+setbSDD(mdcr_el3);
+
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
+setenableTDETGE(hcr, mdcr);
+
+// Enable Vector Catch Exceptions
+const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
+vcExcpt = new 

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding style in self_debug.[cc, hh]

[Giacomo Travaglini (Gerrit) via gem5-dev]

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/31082

to review the following change.


Change subject: arch-arm: Fix coding style in self_debug.[cc, hh]
..

arch-arm: Fix coding style in self_debug.[cc, hh]

Change-Id: I67be98af412b745ea9e16d4e8c6d422c9fbb29fc
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 229 insertions(+), 209 deletions(-)



diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 63ddb45..94d2f23 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -107,7 +107,7 @@


 Fault
-SelfDebug::triggerException(ThreadContext * tc, Addr vaddr)
+SelfDebug::triggerException(ThreadContext *tc, Addr vaddr)
 {
 if (to32) {
 return std::make_shared(vaddr,
@@ -164,15 +164,17 @@
 SelfDebug::isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el,
  bool secure, bool mask)
 {
-bool route_to_el2 =  ArmSystem::haveEL(tc, EL2)
- && !secure && enableTdeTge;
-ExceptionLevel target_el = route_to_el2? EL2 : EL1;
-if (oslk || (bSDD && secure && ArmSystem::haveEL(tc, EL3))){
+bool route_to_el2 =  ArmSystem::haveEL(tc, EL2) &&
+!secure && enableTdeTge;
+
+ExceptionLevel target_el = route_to_el2 ? EL2 : EL1;
+if (oslk || (bSDD && secure && ArmSystem::haveEL(tc, EL3))) {
 return false;
 }
-if (el == target_el){
+
+if (el == target_el) {
 return bKDE  && !mask;
-}else{
+} else {
 return target_el > el;
 }
 }
@@ -181,15 +183,16 @@
 SelfDebug::isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el,
  bool secure, bool mask)
 {
-if (el==EL0 && !ELStateUsingAArch32(tc, EL1, secure)){
+if (el == EL0 && !ELStateUsingAArch32(tc, EL1, secure)) {
 return isDebugEnabledForEL64(tc, el, secure, mask);
 }
-if (oslk){
+
+if (oslk) {
 return false;
 }

 bool enabled;
-if (secure && ArmSystem::haveEL(tc, EL3)){
+if (secure && ArmSystem::haveEL(tc, EL3)) {
 // We ignore the check for invasive External debug checking SPIDEN
 // and DBGEN signals. They are not implemented
 bool spd32 = bits(tc->readMiscReg(MISCREG_MDCR_EL3), 14);
@@ -197,9 +200,7 @@

 bool suiden = bits(tc->readMiscReg(MISCREG_SDER), 0);
 enabled  = el == EL0 ? (enabled || suiden) : enabled;
-}
-else
-{
+} else {
 enabled = el != EL2;
 }
 return enabled;
@@ -306,6 +307,61 @@
 return v;
 }

+void
+SelfDebug::init(ThreadContext *tc)
+{
+if (initialized)
+return;
+CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+aarch32 = cpsr.width == 1;
+
+const AA64DFR0 dfr = tc->readMiscReg(MISCREG_ID_AA64DFR0_EL1);
+const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
+const AA64MMFR1 mm_fr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+
+for (int i = 0; i <= dfr.brps; i++) {
+const bool isctxaw = i >= (dfr.brps - dfr.ctx_cmps);
+
+BrkPoint bkp = BrkPoint((MiscRegIndex)(MISCREG_DBGBCR0_EL1 + i),
+(MiscRegIndex)(MISCREG_DBGBVR0_EL1 + i),
+this, isctxaw, (bool)mm_fr2.varange,
+mm_fr1.vmidbits, aarch32);
+const DBGBCR ctr = tc->readMiscReg(MISCREG_DBGBCR0_EL1 + i);
+
+bkp.updateControl(ctr);
+arBrkPoints.push_back(bkp);
+}
+
+for (int i = 0; i <= dfr.wrps; i++) {
+WatchPoint wtp = WatchPoint((MiscRegIndex)(MISCREG_DBGWCR0 + i),
+(MiscRegIndex)(MISCREG_DBGWVR0 + i),
+this, (bool)mm_fr2.varange, aarch32);
+const DBGWCR ctr = tc->readMiscReg(MISCREG_DBGWCR0 + i);
+
+wtp.updateControl(ctr);
+arWatchPoints.push_back(wtp);
+}
+
+initialized = true;
+
+RegVal oslar_el1 = tc->readMiscReg(MISCREG_OSLAR_EL1);
+updateOSLock(oslar_el1);
+// Initialize preloaded control booleans
+uint64_t mdscr_el1 = tc->readMiscReg(MISCREG_MDSCR_EL1);
+setMDSCRvals(mdscr_el1);
+
+const uint64_t mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
+setbSDD(mdcr_el3);
+
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
+setenableTDETGE(hcr, mdcr);
+
+// Enable Vector Catch Exceptions
+const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
+vcExcpt = new VectorCatch(dvid.vectorcatch==0x0, this);
+}
+
 bool
 BrkPoint::testAddrMatch(ThreadContext *tc, Addr in_pc, uint8_t bas)
 {
@@ -316,7 +372,7 @@
 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 bool thumb = cpsr.t;

-if (thumb){
+if (thumb) {
 if (bas == 0xc)