[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing SecureEL2 feature for Armv8
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31394 )
Change subject: arch-arm: Implementing SecureEL2 feature for Armv8
..
arch-arm: Implementing SecureEL2 feature for Armv8
This patch adds Secure EL2 feature. This allows stage1
EL2/EL&0 and stage2 secure translation.
The changes are organized as follow:
+ insts/static_inst.cc: Modify checks for illegalInstruction on eret
+ isa.cc/hh: Enabling contorl bits
+ isa/insts/misc.hh/64.hh: Smc fault trigger.
+ miscregs.cc/hh: Declaration and initialization of new registers
+ self_debug.cc/hh: Add secureEL2 types for breakpoints
+ stage2_lookup.cc/hh: Allow stage2 in secure state.
+ tlb.cc/table_walker.cc: Allow secure state for stage2 and stage 1 EL2&0
translation regime
+ utility.cc/hh: New function InSecure and refactor of other helpers
to enable secure state
JIRA: https://gem5.atlassian.net/browse/GEM5-686
Change-Id: Ie59438b1828508e944334420da1d8f4745649056
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31394
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/faults.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/interrupts.cc
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/insts/branch.isa
M src/arch/arm/isa/insts/fp.isa
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/semihosting.cc
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tracers/tarmac_record.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
27 files changed, 211 insertions(+), 139 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c4cc51f..333ae5f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -75,6 +75,8 @@
"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
+have_secel2 = Param.Bool(True,
+"True if Secure EL2 is implemented (ARMv8)")
semihosting = Param.ArmSemihosting(NULL,
"Enable support for the Arm semihosting by settings this
parameter")
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 4016d2b..4e2bfd2 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -59,7 +59,7 @@
break;
}
-Iris::CanonicalMsn out_msn = inSecureState(this) ?
+Iris::CanonicalMsn out_msn = isSecure(this) ?
Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
// Figure out what memory spaces match the canonical numbers we need.
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 40cf634..300c82c 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -977,10 +977,12 @@
} else {
bool lower_32 = false;
if (toEL == EL3) {
-if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2))
+if (EL2Enabled(tc))
lower_32 = ELIs32(tc, EL2);
else
lower_32 = ELIs32(tc, EL1);
+} else if (ELIsInHost(tc, fromEL) && fromEL == EL0 && toEL == EL2)
{
+lower_32 = ELIs32(tc, EL0);
} else {
lower_32 = ELIs32(tc, static_cast(toEL - 1));
}
@@ -1310,7 +1312,7 @@
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
toHyp = fromEL == EL2;
-toHyp |= ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
+toHyp |= ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
currEL(tc) <= EL1 && (hcr.tge || stage2 ||
(source == DebugEvent && hdcr.tde));
return toHyp;
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 0cbd776..12586c7 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -634,9 +634,8 @@
const auto tc = xc->tcBase();
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
-if ((ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
- !ELIs32(tc, EL2) && (hcr.tge == 1 || mdcr.tde == 1)) ||
- !ELIs32(tc, EL1)) {
+if ((EL2Enabled(tc) && !ELIs32(tc, EL2) &&
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implementing SecureEL2 feature for Armv8
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31394 )
Change subject: arch-arm: Implementing SecureEL2 feature for Armv8
..
arch-arm: Implementing SecureEL2 feature for Armv8
This patch adds Secure EL2 feature. This allows stage1
EL2/EL&0 and stage2 secure translation.
The changes are organized as follow:
+ insts/static_inst.cc: Modify checks for illegalInstruction on eret
+ isa.cc/hh: Enabling contorl bits
+ isa/insts/misc.hh/64.hh: Smc fault trigger.
+ miscregs.cc/hh: Declaration and initialization of new registers
+ self_debug.cc/hh: Add secureEL2 types for breakpoints
+ stage2_lookup.cc/hh: Allow stage2 in secure state.
+ tlb.cc/table_walker.cc: Allow secure state for stage2 and stage 1 EL2&0
translation regime
+ utility.cc/hh: New function InSecure and refactor of other helpers
to enable secure state
Change-Id: Ie59438b1828508e944334420da1d8f4745649056
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/stage2_lookup.cc
M src/arch/arm/stage2_lookup.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
15 files changed, 177 insertions(+), 96 deletions(-)
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index c7f3c27..cb89def 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -634,9 +634,8 @@
const auto tc = xc->tcBase();
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
-if ((ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
- !ELIs32(tc, EL2) && (hcr.tge == 1 || mdcr.tde == 1)) ||
- !ELIs32(tc, EL1)) {
+if ((EL2Enabled(tc) && !ELIs32(tc, EL2)
+ && (hcr.tge || mdcr.tde)) || !ELIs32(tc, EL1)) {
// Route to AArch64 Software Breakpoint
return std::make_shared(machInst, imm);
} else {
@@ -1094,22 +1093,33 @@
if (unknownMode(mode))
return true;
-const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
-const ExceptionLevel target_el = opModeToEL(mode);
+SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
-HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
-SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
-
-if (target_el > opModeToEL(cur_mode))
+//ELFromSPSR
+bool valid;
+ExceptionLevel target_el = opModeToEL(mode);
+if (!spsr.width) {
+if (!ArmSystem::highestELIs64(tc)) {
+valid = false;
+} else if (!ArmSystem::haveEL(tc, target_el)) {
+valid = false;
+} else if (spsr & 0x2) {
+valid = false;
+} else if (target_el == EL0 && spsr.sp) {
+valid = false;
+} else if (target_el == EL2 && ArmSystem::haveEL(tc, EL3)
&& !scr.ns
+&& !IsSecureEL2Enabled(tc)){
+valid = false;
+} else
+valid = true;
+} else {
+valid = !unknownMode32(mode);
+}
+if (!valid)
return true;
-if (!ArmSystem::haveEL(tc, target_el))
-return true;
-
-if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && scr.ns &&
hcr.tge)
-return true;
-
-if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) && !scr.ns)
+if (target_el > currEL(tc))
return true;
bool spsr_mode_is_aarch32 = (spsr.width == 1);
@@ -1120,17 +1130,9 @@
if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))
return true;
-if (!spsr.width) {
-// aarch64
-if (!ArmSystem::highestELIs64(tc))
-return true;
-if (spsr & 0x2)
-return true;
-if (target_el == EL0 && spsr.sp)
-return true;
-} else {
-// aarch32
-return unknownMode32(mode);
+if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && hcr.tge &&
+(IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc))) {
+return true;
}
return false;
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9cb8c2b..40c589a 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -397,6 +397,11 @@
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
haveSVE ? 0x1 : 0x0);
+// SecEL2
+miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36, 0x1);
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36, 0x1);
// Large ASID support
