[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Move breakpoint/watchpoint check out of the TLB
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31079 )
Change subject: arch-arm: Move breakpoint/watchpoint check out of the TLB
..
arch-arm: Move breakpoint/watchpoint check out of the TLB
The breakpoint, watchpoint, vector catch and software step checks
have been moved from the TLB to the SelfDebug class.
This is cleaningup the TLB model which is simply asking the SelfDebug
class if there is a pending debug fault
Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31079
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
3 files changed, 35 insertions(+), 19 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 9a60aab..96c7822 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -45,6 +45,31 @@
using namespace std;
Fault
+SelfDebug::testDebug(ThreadContext *tc, const RequestPtr ,
+ BaseTLB::Mode mode)
+{
+Fault fault = NoFault;
+
+if (mode == BaseTLB::Execute) {
+const bool d_step = softStep->advanceSS(tc);
+if (!d_step) {
+fault = testVectorCatch(tc, req->getVaddr(), nullptr);
+if (fault == NoFault)
+fault = testBreakPoints(tc, req->getVaddr());
+}
+} else if (!req->isCacheMaintenance() ||
+ (req->isCacheInvalidate() && !req->isCacheClean())) {
+bool md = mode == BaseTLB::Write ? true: false;
+fault = testWatchPoints(tc, req->getVaddr(), md,
+req->isAtomic(),
+req->getSize(),
+req->isCacheMaintenance());
+}
+
+return fault;
+}
+
+Fault
SelfDebug::testBreakPoints(ThreadContext *tc, Addr vaddr)
{
if (!enableFlag)
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 67654d2..121ddde 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -44,6 +44,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/types.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/tlb.hh"
#include "cpu/thread_context.hh"
class ThreadContext;
@@ -322,14 +323,19 @@
delete vcExcpt;
}
+Fault testDebug(ThreadContext *tc, const RequestPtr ,
+BaseTLB::Mode mode);
+
+ protected:
Fault testBreakPoints(ThreadContext *tc, Addr vaddr);
Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
bool atomic, unsigned size, bool cm);
-Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
Fault triggerException(ThreadContext * tc, Addr vaddr);
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm);
+ public:
+Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
inline BrkPoint* getBrkPoint(uint8_t index)
{
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f007f93..db0d55c 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1213,24 +1213,9 @@
//Check for Debug Exceptions
if (fault == NoFault) {
auto *isa = static_cast(tc->getIsaPtr());
-SelfDebug * sd = isa->getSelfDebug();
-if (mode == Execute)
-{
-const bool d_step = sd->getSstep()->advanceSS(tc);
-if (!d_step) {
-fault = sd->testVectorCatch(tc, req->getVaddr(), nullptr);
-if (fault == NoFault)
-fault = sd->testBreakPoints(tc, req->getVaddr());
-}
-}
-else if (!req->isCacheMaintenance() ||
- (req->isCacheInvalidate() && !req->isCacheClean())) {
-bool md = mode == Write ? true: false;
-fault = sd->testWatchPoints(tc, req->getVaddr(), md,
-req->isAtomic(),
-req->getSize(),
-req->isCacheMaintenance());
-}
+SelfDebug *sd = isa->getSelfDebug();
+
+fault = sd->testDebug(tc, req, mode);
}
return fault;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31079
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Gerrit-Change-Number: 31079
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer:
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Move breakpoint/watchpoint check out of the TLB
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/31079
to review the following change.
Change subject: arch-arm: Move breakpoint/watchpoint check out of the TLB
..
arch-arm: Move breakpoint/watchpoint check out of the TLB
The breakpoint, watchpoint, vector catch and software step checks
have been moved from the TLB to the SelfDebug class.
This is cleaningup the TLB model which is simply asking the SelfDebug
class if there is a pending debug fault
Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/tlb.cc
3 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 9a60aab..96c7822 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -45,6 +45,31 @@
using namespace std;
Fault
+SelfDebug::testDebug(ThreadContext *tc, const RequestPtr ,
+ BaseTLB::Mode mode)
+{
+Fault fault = NoFault;
+
+if (mode == BaseTLB::Execute) {
+const bool d_step = softStep->advanceSS(tc);
+if (!d_step) {
+fault = testVectorCatch(tc, req->getVaddr(), nullptr);
+if (fault == NoFault)
+fault = testBreakPoints(tc, req->getVaddr());
+}
+} else if (!req->isCacheMaintenance() ||
+ (req->isCacheInvalidate() && !req->isCacheClean())) {
+bool md = mode == BaseTLB::Write ? true: false;
+fault = testWatchPoints(tc, req->getVaddr(), md,
+req->isAtomic(),
+req->getSize(),
+req->isCacheMaintenance());
+}
+
+return fault;
+}
+
+Fault
SelfDebug::testBreakPoints(ThreadContext *tc, Addr vaddr)
{
if (!enableFlag)
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 67654d2..121ddde 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -44,6 +44,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/types.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/tlb.hh"
#include "cpu/thread_context.hh"
class ThreadContext;
@@ -322,14 +323,19 @@
delete vcExcpt;
}
+Fault testDebug(ThreadContext *tc, const RequestPtr ,
+BaseTLB::Mode mode);
+
+ protected:
Fault testBreakPoints(ThreadContext *tc, Addr vaddr);
Fault testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
bool atomic, unsigned size, bool cm);
-Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
Fault triggerException(ThreadContext * tc, Addr vaddr);
Fault triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm);
+ public:
+Fault testVectorCatch(ThreadContext *tc, Addr addr, ArmFault* flt);
inline BrkPoint* getBrkPoint(uint8_t index)
{
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f007f93..db0d55c 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1213,24 +1213,9 @@
//Check for Debug Exceptions
if (fault == NoFault) {
auto *isa = static_cast(tc->getIsaPtr());
-SelfDebug * sd = isa->getSelfDebug();
-if (mode == Execute)
-{
-const bool d_step = sd->getSstep()->advanceSS(tc);
-if (!d_step) {
-fault = sd->testVectorCatch(tc, req->getVaddr(), nullptr);
-if (fault == NoFault)
-fault = sd->testBreakPoints(tc, req->getVaddr());
-}
-}
-else if (!req->isCacheMaintenance() ||
- (req->isCacheInvalidate() && !req->isCacheClean())) {
-bool md = mode == Write ? true: false;
-fault = sd->testWatchPoints(tc, req->getVaddr(), md,
-req->isAtomic(),
-req->getSize(),
-req->isCacheMaintenance());
-}
+SelfDebug *sd = isa->getSelfDebug();
+
+fault = sd->testDebug(tc, req, mode);
}
return fault;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31079
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Gerrit-Change-Number: 31079
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: newchange
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