[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove getters/setters from SelfDebug class
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31081 )
Change subject: arch-arm: Remove getters/setters from SelfDebug class
..
arch-arm: Remove getters/setters from SelfDebug class
Change-Id: I63e5ed25e453cb8fcb2c39ba0728cc81c499c166
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31081
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 13 insertions(+), 40 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index c964b11..63ddb45 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -90,13 +90,13 @@
Addr pc = vaddr;
if (pcst.itstate() != 0x0)
pc = pcst.pc();
-if (p.getEnable() && p.isActive(pc) &&(!to32 || !p.isSet())){
+if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
const DBGBCR ctr = p.getControlReg(tc);
if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
bool debug = p.test(tc, pc, el, ctr, false);
if (debug){
if (to32)
-p.setOnUse();
+p.onUse = true;
return triggerException(tc, pc);
}
}
@@ -109,7 +109,7 @@
Fault
SelfDebug::triggerException(ThreadContext * tc, Addr vaddr)
{
-if (isTo32()) {
+if (to32) {
return std::make_shared(vaddr,
ArmFault::DebugEvent, false,
ArmFault::UnknownTran,
@@ -134,8 +134,7 @@
int idxtmp = -1;
for (auto : arWatchPoints){
idxtmp ++;
-if (p.getEnable())
-{
+if (p.enable) {
bool debug = p.test(tc, vaddr, el, write, atomic, size);
if (debug){
return triggerWatchpointException(tc, vaddr, write, cm);
@@ -149,7 +148,7 @@
SelfDebug::triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm)
{
-if (isTo32()) {
+if (to32) {
ArmFault::DebugType d = cm? ArmFault::WPOINT_CM:
ArmFault::WPOINT_NOCM;
return std::make_shared(vaddr,
@@ -211,7 +210,7 @@
{
bool debug = false;
const DBGBCR ctr = getControlReg(tc);
-if ((ctr.bt & 0x1) && getEnable()){
+if ((ctr.bt & 0x1) && enable) {
debug = test(tc, vaddr, el, ctr, true);
}
return debug;
@@ -527,7 +526,6 @@
uint8_t mask, unsigned size)
{
Addr addr_tocmp = getAddrfromReg(tc);
-int maxAddrSize = getMaxAddrSize();
int maxbits = isDoubleAligned(addr_tocmp) ? 4: 8;
int bottom = isDoubleAligned(addr_tocmp) ? 2: 3;
Addr addr = bits(in_addr, maxAddrSize, 0);
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 121ddde..c185223 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -68,6 +68,8 @@
bool onUse;
public:
+friend class SelfDebug;
+
BrkPoint(MiscRegIndex _ctrlIndex, MiscRegIndex _valIndex,
MiscRegIndex _xIndex, SelfDebug* _conf, bool _ctxAw, bool lva,
bool vmid16, bool aarch32):
@@ -77,20 +79,9 @@
{
maxAddrSize = lva ? 52: 48 ;
maxAddrSize = aarch32 ? 31 : maxAddrSize;
-onUse=false;
-}
-void setOnUse()
-{
-onUse = true;
-}
-void unsetOnUse()
-{
onUse = false;
}
-bool isSet()
-{
-return onUse;
-}
+
bool testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el);
bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr,
bool from_link);
@@ -138,11 +129,6 @@
{
enable = val.e == 0x1;
}
-bool getEnable()
-{
-return enable;
-}
-
};
class WatchPoint
@@ -154,13 +140,9 @@
bool enable;
int maxAddrSize;
-inline int getMaxAddrSize()
-{
-return maxAddrSize;
-}
-
-
public:
+friend class SelfDebug;
+
WatchPoint(MiscRegIndex _ctrlIndex, MiscRegIndex _valIndex,
SelfDebug* _conf, bool lva, bool aarch32):
ctrlRegIndex(_ctrlIndex),
@@ -188,10 +170,6 @@
{
enable = val.e == 0x1;
}
-bool getEnable()
-{
-return enable;
-}
bool isEnabled(ThreadContext* tc, ExceptionLevel el, bool hmc,
uint8_t ssc, uint8_t pac);
@@ -368,7 +346,7 @@
void activateDebug()
{
for (auto : arBrkPoints){
-p.unsetOnUse();
+
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Remove getters/setters from SelfDebug class
Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/31081
to review the following change.
Change subject: arch-arm: Remove getters/setters from SelfDebug class
..
arch-arm: Remove getters/setters from SelfDebug class
Change-Id: I63e5ed25e453cb8fcb2c39ba0728cc81c499c166
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
---
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
2 files changed, 13 insertions(+), 40 deletions(-)
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index c964b11..63ddb45 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -90,13 +90,13 @@
Addr pc = vaddr;
if (pcst.itstate() != 0x0)
pc = pcst.pc();
-if (p.getEnable() && p.isActive(pc) &&(!to32 || !p.isSet())){
+if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
const DBGBCR ctr = p.getControlReg(tc);
if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
bool debug = p.test(tc, pc, el, ctr, false);
if (debug){
if (to32)
-p.setOnUse();
+p.onUse = true;
return triggerException(tc, pc);
}
}
@@ -109,7 +109,7 @@
Fault
SelfDebug::triggerException(ThreadContext * tc, Addr vaddr)
{
-if (isTo32()) {
+if (to32) {
return std::make_shared(vaddr,
ArmFault::DebugEvent, false,
ArmFault::UnknownTran,
@@ -134,8 +134,7 @@
int idxtmp = -1;
for (auto : arWatchPoints){
idxtmp ++;
-if (p.getEnable())
-{
+if (p.enable) {
bool debug = p.test(tc, vaddr, el, write, atomic, size);
if (debug){
return triggerWatchpointException(tc, vaddr, write, cm);
@@ -149,7 +148,7 @@
SelfDebug::triggerWatchpointException(ThreadContext *tc, Addr vaddr,
bool write, bool cm)
{
-if (isTo32()) {
+if (to32) {
ArmFault::DebugType d = cm? ArmFault::WPOINT_CM:
ArmFault::WPOINT_NOCM;
return std::make_shared(vaddr,
@@ -211,7 +210,7 @@
{
bool debug = false;
const DBGBCR ctr = getControlReg(tc);
-if ((ctr.bt & 0x1) && getEnable()){
+if ((ctr.bt & 0x1) && enable) {
debug = test(tc, vaddr, el, ctr, true);
}
return debug;
@@ -527,7 +526,6 @@
uint8_t mask, unsigned size)
{
Addr addr_tocmp = getAddrfromReg(tc);
-int maxAddrSize = getMaxAddrSize();
int maxbits = isDoubleAligned(addr_tocmp) ? 4: 8;
int bottom = isDoubleAligned(addr_tocmp) ? 2: 3;
Addr addr = bits(in_addr, maxAddrSize, 0);
diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh
index 121ddde..c185223 100644
--- a/src/arch/arm/self_debug.hh
+++ b/src/arch/arm/self_debug.hh
@@ -68,6 +68,8 @@
bool onUse;
public:
+friend class SelfDebug;
+
BrkPoint(MiscRegIndex _ctrlIndex, MiscRegIndex _valIndex,
MiscRegIndex _xIndex, SelfDebug* _conf, bool _ctxAw, bool lva,
bool vmid16, bool aarch32):
@@ -77,20 +79,9 @@
{
maxAddrSize = lva ? 52: 48 ;
maxAddrSize = aarch32 ? 31 : maxAddrSize;
-onUse=false;
-}
-void setOnUse()
-{
-onUse = true;
-}
-void unsetOnUse()
-{
onUse = false;
}
-bool isSet()
-{
-return onUse;
-}
+
bool testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el);
bool test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr,
bool from_link);
@@ -138,11 +129,6 @@
{
enable = val.e == 0x1;
}
-bool getEnable()
-{
-return enable;
-}
-
};
class WatchPoint
@@ -154,13 +140,9 @@
bool enable;
int maxAddrSize;
-inline int getMaxAddrSize()
-{
-return maxAddrSize;
-}
-
-
public:
+friend class SelfDebug;
+
WatchPoint(MiscRegIndex _ctrlIndex, MiscRegIndex _valIndex,
SelfDebug* _conf, bool lva, bool aarch32):
ctrlRegIndex(_ctrlIndex),
@@ -188,10 +170,6 @@
{
enable = val.e == 0x1;
}
-bool getEnable()
-{
-return enable;
-}
bool isEnabled(ThreadContext* tc, ExceptionLevel el, bool hmc,
uint8_t ssc, uint8_t pac);
@@ -368,7 +346,7 @@
void activateDebug()
{
for (auto : arBrkPoints){
-p.unsetOnUse();
+p.onUse = false;
}
}
@@ -432,10 +410,6 @@
return aarch32;
}
-inline bool isTo32()
-{
-return to32;
-}
inline void setAArch32(ThreadContext * tc)
{
ExceptionLevel fromEL = (ExceptionLevel)
