Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30934 )
Change subject: arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented
..
arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented
The feature was implemented at: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28
Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30934
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmISA.py
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index f701f7d..b2513f7 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2019 ARM Limited
+# Copyright (c) 2012-2013, 2015-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -101,8 +101,8 @@
id_aa64isar0_el1 = Param.UInt64(0x,
"AArch64 Instruction Set Attribute Register 0")
-# GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1 | FCMA
-id_aa64isar1_el1 = Param.UInt64(0x01010010,
+# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
+id_aa64isar1_el1 = Param.UInt64(0x01011010,
"AArch64 Instruction Set Attribute Register 1")
# 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84
Gerrit-Change-Number: 30934
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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