[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-30 Thread Anthony Gutierrez (Gerrit) via gem5-dev
Anthony Gutierrez has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28127 )


Change subject: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)
..

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

Decoder: gpu_decoder.hh and decoder.cc:
The decoder is defined in these files. The decoder
is implemented as a lookup table of function pointers
where each decode function will decode to a unique
ISA instruction, or do some sub-decoding to infer
the next decode function to call.

The format for each OP encoding is defined in the
header file.

Registers:
registers.[hh|cc] define the special registers and
operand selector values, which are used to map
operands to registers/special values. many
convenience functions are also provides to determine
the source/type of an operand, for example vector
vs. scalar, register operand vs. constant, etc.

GPU ISA:
Some special GPU ISA state is maintained in gpu_isa.hh
and isa.cc. This class is used to hold some special
registers and values that can be used as operands
by ISA instructions. Eventually more ISA-specific
state should be moved here, and out of the WF class.

Vector Operands:
The operands for GCN3 instructions are defined in
operand.hh. This file defines both scalar and
vector operands wth GCN3 specific semantics. The
vector operand class is desgned around the generic
vec_reg.hh that is already present in gem5.

Instructions:
The GCN3 instructions are defined and implemented
throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
all fall under one of the OP encoding types; for example
scalar memory operands are of the type SMEM, vector
ALU instructions can be VOP3, VOP2, etc. The base code
common to all instructions of a certain OP encoding type
is implemented in the OP encodings files, which includes
operand information, disassembly methods, encoding type,
etc.

Each individual ISA isntruction is implemented as
a class object in instructions.[hh|cc] and are derived
from one of the OP encoding types. The instructions.cc
file is primarily for the execute() methods of each
individual instruction, and the header file provides
the class definition and a few instruction specific
API calls.

Note that these instruction classes were auto-generated
but not using the gem5 ISA description language. A
custom ISA description was used and that cannot be released
publicly, therefore we are providing them already in C++.

Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28127
Reviewed-by: Matt Sinclair 
Reviewed-by: Jason Lowe-Power 
Maintainer: Anthony Gutierrez 
Tested-by: kokoro 
---
M MAINTAINERS
A src/arch/gcn3/SConscript
A src/arch/gcn3/SConsopts
A src/arch/gcn3/decoder.cc
A src/arch/gcn3/gpu_decoder.hh
A src/arch/gcn3/gpu_isa.hh
A src/arch/gcn3/gpu_types.hh
A src/arch/gcn3/insts/gpu_static_inst.cc
A src/arch/gcn3/insts/gpu_static_inst.hh
A src/arch/gcn3/insts/inst_util.hh
A src/arch/gcn3/insts/instructions.cc
A src/arch/gcn3/insts/instructions.hh
A src/arch/gcn3/insts/op_encodings.cc
A src/arch/gcn3/insts/op_encodings.hh
A src/arch/gcn3/isa.cc
A src/arch/gcn3/operand.hh
A src/arch/gcn3/registers.cc
A src/arch/gcn3/registers.hh
M util/git-commit-msg.py
19 files changed, 139,749 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Matt Sinclair: Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved
  kokoro: Regressions pass




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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Gerrit-Change-Number: 28127
Gerrit-PatchSet: 2
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-23 Thread Anthony Gutierrez (Gerrit) via gem5-dev

Hello Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28127

to review the following change.


Change subject: arch-gcn3: Add files for arch gcn3 (GPU machine ISA)
..

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

Decoder: gpu_decoder.hh and decoder.cc:
The decoder is defined in these files. The decoder
is implemented as a lookup table of function pointers
where each decode function will decode to a unique
ISA instruction, or do some sub-decoding to infer
the next decode function to call.

The format for each OP encoding is defined in the
header file.

Registers:
registers.[hh|cc] define the special registers and
operand selector values, which are used to map
operands to registers/special values. many
convenience functions are also provides to determine
the source/type of an operand, for example vector
vs. scalar, register operand vs. constant, etc.

GPU ISA:
Some special GPU ISA state is maintained in gpu_isa.hh
and isa.cc. This class is used to hold some special
registers and values that can be used as operands
by ISA instructions. Eventually more ISA-specific
state should be moved here, and out of the WF class.

Vector Operands:
The operands for GCN3 instructions are defined in
operand.hh. This file defines both scalar and
vector operands wth GCN3 specific semantics. The
vector operand class is desgned around the generic
vec_reg.hh that is already present in gem5.

Instructions:
The GCN3 instructions are defined and implemented
throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
all fall under one of the OP encoding types; for example
scalar memory operands are of the type SMEM, vector
ALU instructions can be VOP3, VOP2, etc. The base code
common to all instructions of a certain OP encoding type
is implemented in the OP encodings files, which includes
operand information, disassembly methods, encoding type,
etc.

Each individual ISA isntruction is implemented as
a class object in instructions.[hh|cc] and are derived
from one of the OP encoding types. The instructions.cc
file is primarily for the execute() methods of each
individual instruction, and the header file provides
the class definition and a few instruction specific
API calls.

Note that these instruction classes were auto-generated
but not using the gem5 ISA description language. A
custom ISA description was used and that cannot be released
publicly, therefore we are providing them already in C++.

Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
---
M MAINTAINERS
A src/arch/gcn3/SConscript
A src/arch/gcn3/SConsopts
A src/arch/gcn3/decoder.cc
A src/arch/gcn3/gpu_decoder.hh
A src/arch/gcn3/gpu_isa.hh
A src/arch/gcn3/gpu_types.hh
A src/arch/gcn3/insts/gpu_static_inst.cc
A src/arch/gcn3/insts/gpu_static_inst.hh
A src/arch/gcn3/insts/inst_util.hh
A src/arch/gcn3/insts/instructions.cc
A src/arch/gcn3/insts/instructions.hh
A src/arch/gcn3/insts/op_encodings.cc
A src/arch/gcn3/insts/op_encodings.hh
A src/arch/gcn3/isa.cc
A src/arch/gcn3/operand.hh
A src/arch/gcn3/registers.cc
A src/arch/gcn3/registers.hh
M util/git-commit-msg.py
19 files changed, 139,749 insertions(+), 7 deletions(-)




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To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28127
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Gerrit-Change-Number: 28127
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-MessageType: newchange
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