[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Fix VOP2 dissasembly prints

[Anthony Gutierrez (Gerrit) via gem5-dev]

Anthony Gutierrez has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/29936 )


Change subject: arch-gcn3: Fix VOP2 dissasembly prints
..

arch-gcn3: Fix VOP2 dissasembly prints

VOP2 prints VSRC1 register index as hex instead of decimal if the
instruction contains a literal operand.  This patch resets the
format specifiers in the stream to print the register correctly.

Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29936
Tested-by: kokoro 
Reviewed-by: Anthony Gutierrez 
Maintainer: Anthony Gutierrez 
---
M src/arch/gcn3/insts/op_encodings.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/gcn3/insts/op_encodings.cc  
b/src/arch/gcn3/insts/op_encodings.cc

index 2eb4042..fe501f2 100644
--- a/src/arch/gcn3/insts/op_encodings.cc
+++ b/src/arch/gcn3/insts/op_encodings.cc
@@ -763,7 +763,8 @@
<< extData.imm_u32 << ", ";
 }

-dis_stream << "v" << instData.VSRC1;
+dis_stream << std::resetiosflags(std::ios_base::basefield) << "v"
+<< instData.VSRC1;

 if (readsVCC())
 dis_stream << ", vcc";

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
Gerrit-Change-Number: 29936
Gerrit-PatchSet: 9
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Michael LeBeane 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-Reviewer: Tuan Ta 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: Fix VOP2 dissasembly prints

[Anthony Gutierrez (Gerrit) via gem5-dev]

Hello Michael LeBeane, Tony Gutierrez,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/29936

to review the following change.


Change subject: arch-gcn3: Fix VOP2 dissasembly prints
..

arch-gcn3: Fix VOP2 dissasembly prints

VOP2 prints VSRC1 register index as hex instead of decimal if the
instruction contains a literal operand.  This patch resets the
format specifiers in the stream to print the register correctly.

Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
---
M src/arch/gcn3/insts/op_encodings.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/gcn3/insts/op_encodings.cc  
b/src/arch/gcn3/insts/op_encodings.cc

index 2eb4042..fe501f2 100644
--- a/src/arch/gcn3/insts/op_encodings.cc
+++ b/src/arch/gcn3/insts/op_encodings.cc
@@ -763,7 +763,8 @@
<< extData.imm_u32 << ", ";
 }

-dis_stream << "v" << instData.VSRC1;
+dis_stream << std::resetiosflags(std::ios_base::basefield) << "v"
+<< instData.VSRC1;

 if (readsVCC())
 dis_stream << ", vcc";

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29936
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f
Gerrit-Change-Number: 29936
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez 
Gerrit-Reviewer: Michael LeBeane 
Gerrit-Reviewer: Tony Gutierrez 
Gerrit-MessageType: newchange
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