[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add MSR and associated dependencies
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40943 )
Change subject: arch-power: Add MSR and associated dependencies
..
arch-power: Add MSR and associated dependencies
This adds the definition of the Machine State Register
(MSR) in preparation for multi-mode support. The MSR
has bits that define the state of the processor. This
defines all the bitfields and sets the ones that are
typically used for userspace environments.
In preparation for multi-mode support, the SF and LE
bits are used by instructions to check if the simulation
is running in 64-bit mode and if memory accesses are to
be performed in little endian byte order respectively.
This introduces changes in areas such as target address
computation for branch instructions, carry and overflow
computation for arithmetic instructions, etc.
Change-Id: If9ac69415ca85b0c873bd8579e7d1bd2219eac62
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40943
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/operands.isa
M src/arch/power/process.cc
M src/arch/power/regs/int.hh
M src/arch/power/regs/misc.hh
9 files changed, 127 insertions(+), 41 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index ca52d83..a1b6d8c 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -27,6 +27,8 @@
*/
#include "arch/power/insts/branch.hh"
+#include "arch/power/regs/int.hh"
+#include "arch/power/regs/misc.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
@@ -54,12 +56,17 @@
PowerISA::PCState
-BranchOp::branchTarget(const PowerISA::PCState ) const
+BranchOp::branchTarget(ThreadContext *tc) const
{
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr;
+
if (aa)
-return li;
+addr = li;
else
-return pc.pc() + li;
+addr = tc->pcState().pc() + li;
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -97,13 +104,17 @@
PowerISA::PCState
-BranchDispCondOp::branchTarget(const PowerISA::PCState ) const
+BranchDispCondOp::branchTarget(ThreadContext *tc) const
{
-if (aa) {
-return bd;
-} else {
-return pc.pc() + bd;
-}
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr;
+
+if (aa)
+addr = bd;
+else
+addr = tc->pcState().pc() + bd;
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -146,8 +157,9 @@
PowerISA::PCState
BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return addr & -4ULL;
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
+return msr.sf ? addr : addr & UINT32_MAX;
}
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 5c5982c..cad91c2 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -87,7 +87,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
@@ -158,7 +158,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
diff --git a/src/arch/power/isa/formats/branch.isa
b/src/arch/power/isa/formats/branch.isa
index b970bc0..efb5f06 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -87,11 +87,11 @@
# Check the condition register (CR) allows the branch to be taken.
def GetCondCode(br_code):
-cond_code = 'if (condOk(CR)) {\n'
+cond_code = 'Msr msr = MSR;\n'
+cond_code += 'if (condOk(CR)) {\n'
cond_code += '' + br_code + '\n'
-cond_code += '} else {\n'
-cond_code += 'NIA = NIA;\n'
cond_code += '}\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
return cond_code
# Check the condition register (CR) and count register (CTR) allow the
@@ -99,11 +99,11 @@
# register too. This takes place in ctrOk within BranchCondOp classes.
def GetCtrCondCode(br_code):
cond_code = 'uint64_t ctr = CTR;\n'
+cond_code += 'Msr msr = MSR;\n'
cond_code += 'if (ctrOk(ctr) && condOk(CR)) {\n'
cond_code
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add MSR and associated dependencies
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40943 )
Change subject: arch-power: Add MSR and associated dependencies
..
arch-power: Add MSR and associated dependencies
This adds the definition of the Machine State Register
(MSR) in preparation for multi-mode support. The MSR
has bits that define the state of the processor. This
defines all the bitfields and sets the ones that are
typically used for userspace environments.
In preparation for multi-mode support, the SF and LE
bits are used by instructions to check if the simulation
is running in 64-bit mode and if memory accesses are to
be performed in little endian byte order respectively.
This introduces changes in areas such as target address
computation for branch instructions, carry and overflow
computation for arithmetic instructions, etc.
Change-Id: If9ac69415ca85b0c873bd8579e7d1bd2219eac62
Signed-off-by: Sandipan Das
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/operands.isa
M src/arch/power/miscregs.hh
M src/arch/power/process.cc
8 files changed, 122 insertions(+), 34 deletions(-)
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 3747bf1..f54185a 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -54,13 +54,18 @@
PowerISA::PCState
-BranchOp::branchTarget(const PowerISA::PCState ) const
+BranchOp::branchTarget(ThreadContext *tc) const
{
+Msr msr = tc->readMiscReg(MISCREG_MSR);
+Addr addr;
+
if (aaSet) {
-return disp;
+addr = disp;
} else {
-return pc.pc() + disp;
+addr = tc->pcState().pc() + disp;
}
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -96,13 +101,18 @@
PowerISA::PCState
-BranchDispCondOp::branchTarget(const PowerISA::PCState ) const
+BranchDispCondOp::branchTarget(ThreadContext *tc) const
{
+Msr msr = tc->readMiscReg(MISCREG_MSR);
+Addr addr;
+
if (aaSet) {
-return disp;
+addr = disp;
} else {
-return pc.pc() + disp;
+addr = tc->pcState().pc() + disp;
}
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -143,8 +153,9 @@
PowerISA::PCState
BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return addr & -4ULL;
+Msr msr = tc->readMiscReg(MISCREG_MSR);
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
+return msr.sf ? addr : addr & UINT32_MAX;
}
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 8c311a2..40555aa 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -84,7 +84,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
@@ -163,7 +163,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
diff --git a/src/arch/power/isa/formats/branch.isa
b/src/arch/power/isa/formats/branch.isa
index b107cb3..29f1df3 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -125,10 +125,12 @@
# Check the condition register (CR) allows the branch to be taken.
def GetCondCode(br_code):
-cond_code = 'if (checkCond(CR)) {\n'
+cond_code = 'Msr msr = MSR;\n'
+cond_code += 'if (checkCond(CR)) {\n'
cond_code += '' + br_code + '\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
cond_code += '} else {\n'
-cond_code += 'NIA = NIA;\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
cond_code += '}\n'
return cond_code
@@ -139,10 +141,12 @@
cond_code = 'uint64_t ctr = CTR;\n'
cond_code += 'bool ctrOk = checkCtr(ctr);\n'
cond_code += 'bool condOk = checkCond(CR);\n'
+cond_code += 'Msr msr = MSR;\n'
cond_code += 'if (ctrOk && condOk) {\n'
cond_code += '' + br_code + '\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
cond_code += '} else {\n'
-cond_code += 'NIA = NIA;\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
cond_code += '}\n'
cond_code += 'CTR = ctr;\n'
return cond_code
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 3ab9ad9..5a353d0 100644
--- a/src/arch/power/isa/formats/integer.isa
