[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add byte-reversed load-store instructions

[Boris Shingarov (Gerrit) via gem5-dev]

Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40896 )


Change subject: arch-power: Add byte-reversed load-store instructions
..

arch-power: Add byte-reversed load-store instructions

This adds the following instructions.
  * Load Halfword Byte-Reverse Indexed (lhbrx)
  * Load Word Byte-Reverse Indexed (lwbrx)
  * Load Doubleword Byte-Reverse Indexed (ldbrx)
  * Store Halfword Byte-Reverse Indexed (sthbrx)
  * Store Word Byte-Reverse Indexed (stwbrx)
  * Store Doubleword Byte-Reverse Indexed (stdbrx)

Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40896
Reviewed-by: Boris Shingarov 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/power/isa/decoder.isa
1 file changed, 14 insertions(+), 2 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e00ce3b..0cf6201 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -285,7 +285,11 @@
 }});
 }

-535: LoadIndexOp::lfsx({{ Ft_sf = Mem_sf; }});
+format LoadIndexOp {
+532: ldbrx({{ Rt = swap_byte(Mem); }});
+534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
+535: lfsx({{ Ft_sf = Mem_sf; }});
+}

 536: IntLogicOp::srw({{
 if (Rb & 0x20) {
@@ -299,10 +303,17 @@
 598: MiscOp::sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
 599: LoadIndexOp::lfdx({{ Ft = Mem_df; }});
 631: LoadIndexUpdateOp::lfdux({{ Ft = Mem_df; }});
-663: StoreIndexOp::stfsx({{ Mem_sf = Fs_sf; }});
+
+format StoreIndexOp {
+660: stdbrx({{ Mem = swap_byte(Rs); }});
+662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
+663: stfsx({{ Mem_sf = Fs_sf; }});
+}
+
 695: StoreIndexUpdateOp::stfsux({{ Mem_sf = Fs_sf; }});
 727: StoreIndexOp::stfdx({{ Mem_df = Fs; }});
 759: StoreIndexUpdateOp::stfdux({{ Mem_df = Fs; }});
+790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});

 792: IntLogicOp::sraw({{
 bool shiftSetCA = false;
@@ -364,6 +375,7 @@

 854: MiscOp::eieio({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
 855: LoadIndexOp::lfiwax({{ Ft_uw = Mem; }});
+918: StoreIndexOp::sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});

 format IntLogicOp {
 922: extsh({{ Ra = sext<16>(Rs); }});

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40896
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Gerrit-Change-Number: 40896
Gerrit-PatchSet: 7
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add byte-reversed load-store instructions

[Sandipan Das (Gerrit) via gem5-dev]

Sandipan Das has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40896 )



Change subject: arch-power: Add byte-reversed load-store instructions
..

arch-power: Add byte-reversed load-store instructions

This adds the following instructions.
  * Load Halfword Byte-Reverse Indexed (lhbrx)
  * Load Word Byte-Reverse Indexed (lwbrx)
  * Load Doubleword Byte-Reverse Indexed (ldbrx)
  * Store Halfword Byte-Reverse Indexed (sthbrx)
  * Store Word Byte-Reverse Indexed (stwbrx)
  * Store Doubleword Byte-Reverse Indexed (stdbrx)

Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Signed-off-by: Sandipan Das 
---
M src/arch/power/isa/decoder.isa
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 67eebcd..a0b9179 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -248,10 +248,13 @@
 87: lbzx({{ Rt = Mem_ub; }});
 279: lhzx({{ Rt = Mem_uh; }});
 343: lhax({{ Rt = Mem_sh; }});
+790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
 23: lwzx({{ Rt = Mem_uw; }});
 341: lwax({{ Rt = Mem_sw; }});
 20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA;  
}});

+534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
 21: ldx({{ Rt = Mem; }});
+532: ldbrx({{ Rt = swap_byte(Mem); }});
 535: lfsx({{ Ft_sf = Mem_sf; }});
 599: lfdx({{ Ft = Mem_df; }});
 855: lfiwax({{ Ft_uw = Mem; }});
@@ -271,6 +274,7 @@
 format StoreIndexOp {
 215: stbx({{ Mem_ub = Rs_ub; }});
 407: sthx({{ Mem_uh = Rs_uh; }});
+918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
 151: stwx({{ Mem_uw = Rs_uw; }});
 150: stwcx({{
 bool store_performed = false;
@@ -288,7 +292,9 @@
 CR = cr;
 Rsv = 0;
 }});
+662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
 149: stdx({{ Mem = Rs }});
+660: stdbrx({{ Mem = swap_byte(Rs); }});
 }

 format StoreIndexUpdateOp {

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40896
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Gerrit-Change-Number: 40896
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das 
Gerrit-MessageType: newchange
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