[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40895 )
Change subject: arch-power: Add doubleword load-store instructions
..
arch-power: Add doubleword load-store instructions
This introduces new formats for DS form instructions and
adds the following instructions.
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40895
Reviewed-by: Boris Shingarov
Reviewed-by: lkcl
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
2 files changed, 57 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved
lkcl: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index c81e65b..d0d3dc9 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -201,6 +201,7 @@
Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
+21: ldx({{ Rt = Mem; }});
23: lwzx({{ Rt = Mem_uw; }});
}
@@ -223,6 +224,7 @@
CR = insertCRField(CR, BF, cr);
}});
+53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
@@ -230,6 +232,7 @@
124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
format StoreIndexOp {
+149: stdx({{ Mem = Rs }});
150: stwcx({{
bool store_performed = false;
Mem_uw = Rs_uw;
@@ -250,7 +253,11 @@
151: stwx({{ Mem_uw = Rs_uw; }});
}
-183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
+format StoreIndexUpdateOp {
+181: stdux({{ Mem = Rs; }});
+183: stwux({{ Mem_uw = Rs_uw; }});
+}
+
215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
@@ -543,6 +550,8 @@
55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});
58: decode DS_XO {
+0: LoadDispShiftOp::ld({{ Rt = Mem; }});
+1: LoadDispShiftUpdateOp::ldu({{ Rt = Mem; }});
2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
}
@@ -559,6 +568,11 @@
}
}
+62: decode DS_XO {
+0: StoreDispShiftOp::std({{ Mem = Rs; }});
+1: StoreDispShiftUpdateOp::stdu({{ Mem = Rs; }});
+}
+
63: decode A_XO {
format FloatArithOp {
20: fsub({{ Ft = Fa - Fb; }});
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index d2b3ab7..4886296 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -311,6 +311,16 @@
}};
+def format StoreDispShiftOp(memacc_code,
+ea_code = {{ EA = Ra + (ds << 2); }},
+ea_code_ra0 = {{ EA = (ds << 2); }},
+mem_flags = [], inst_flags = []) {{
+(header_output, decoder_output, decode_block, exec_output) = \
+GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+ 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }},
mem_flags = [], inst_flags = []) {{
@@ -339,3 +349,35 @@
decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (ds << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
+ base_class = 'MemDispShiftOp',
+ decode_template = CheckRaRtDecode,
+ exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (ds << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword load-store instructions
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40895 )
Change subject: arch-power: Add doubleword load-store instructions
..
arch-power: Add doubleword load-store instructions
This introduces new formats for DS form instructions and
adds the following instructions.
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e2b3929..67eebcd 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -134,6 +134,21 @@
58: decode DS_XO {
format LoadDispShiftOp {
2: lwa({{ Rt = Mem_sw; }});
+0: ld({{ Rt = Mem; }});
+}
+
+format LoadDispShiftUpdateOp {
+1: ldu({{ Rt = Mem; }});
+}
+}
+
+62: decode DS_XO {
+format StoreDispShiftOp {
+0: std({{ Mem = Rs; }});
+}
+
+format StoreDispShiftUpdateOp {
+1: stdu({{ Mem = Rs; }});
}
}
@@ -236,6 +251,7 @@
23: lwzx({{ Rt = Mem_uw; }});
341: lwax({{ Rt = Mem_sw; }});
20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
+21: ldx({{ Rt = Mem; }});
535: lfsx({{ Ft_sf = Mem_sf; }});
599: lfdx({{ Ft = Mem_df; }});
855: lfiwax({{ Ft_uw = Mem; }});
@@ -247,6 +263,7 @@
375: lhaux({{ Rt = Mem_sh; }});
55: lwzux({{ Rt = Mem_uw; }});
373: lwaux({{ Rt = Mem_sw; }});
+53: ldux({{ Rt = Mem; }});
567: lfsux({{ Ft_sf = Mem_sf; }});
631: lfdux({{ Ft = Mem_df; }});
}
@@ -271,12 +288,14 @@
CR = cr;
Rsv = 0;
}});
+149: stdx({{ Mem = Rs }});
}
format StoreIndexUpdateOp {
247: stbux({{ Mem_ub = Rs_ub; }});
439: sthux({{ Mem_uh = Rs_uh; }});
183: stwux({{ Mem_uw = Rs_uw; }});
+181: stdux({{ Mem = Rs; }});
}
format IntOp {
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index 1dd9854..1cddc40 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -311,6 +311,16 @@
}};
+def format StoreDispShiftOp(memacc_code,
+ea_code = {{ EA = Ra + (disp << 2); }},
+ea_code_ra0 = {{ EA = (disp << 2); }},
+mem_flags = [], inst_flags = []) {{
+(header_output, decoder_output, decode_block, exec_output) = \
+GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+ 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
mem_flags = [], inst_flags = []) {{
@@ -339,3 +349,35 @@
decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (disp << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
+ base_class = 'MemDispShiftOp',
+ decode_template = CheckRaRtDecode,
+ exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (disp << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
+ base_class = 'MemDispShiftOp',
+ decode_template = CheckRaZeroDecode,
+ exec_template_base = 'Store')
+}};
--
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